JP2646771B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having three logic output voltage levels.

[Prior Art] A conventional technique will be described with reference to the drawings. FIG. 3 is a circuit diagram for explaining a conventional example. The input signal 22 is data output from the output terminal 30, and the control signal 23 is
A control signal for selecting a high level output, a first positive power supply 24,
Each of the second positive power supplies 25 is a power supply for determining a potential of a high-level output. The p-ch transistor 26 and the p-ch transistor 27 are p-ch transistors for outputting a high level, the n-ch transistor 28 is an n-ch transistor for outputting a low level, and the output terminal 30 is an input signal 22 and control. An output terminal for outputting an output signal according to the signal 23.

In the present embodiment, the first positive power supply 24 is the second positive power supply.
It has a potential lower than 25 and can be changed arbitrarily.

At this time, if the input signal 22 is low level, the control signal
Regardless of 23, the p-ch transistor 26 and the p-ch transistor are both turned off and the n-ch transistor 28 is turned on, so that a low level is output from the output terminal 30.

Next, when the input signal 22 is at a high level and the control signal 23 is at a low level, the p-ch transistor 27 and the n-ch transistor 28 are turned off, and the p-ch transistor 26 is turned on, so that the power supply follows the first positive power supply 24. Output high level output. When the input signal 22 is high and the control signal 23 is high, the p-ch transistor 26 and the n-ch transistor 28 are turned off, and the p-ch
When the transistor 27 is turned on, a high-level output according to the positive power supply 25 is output.

At this time, since a voltage according to the second positive power supply 25 is applied to the drain of the p-ch transistor 26, it is necessary to apply an equal voltage to the back gate of the p-ch transistor 26. Therefore, the back gate is connected to the second positive power supply 25. Therefore, the gate voltage when the p-ch transistor 26 is turned on is determined by the second positive power supply 25. Therefore, when the second positive power supply 25 fluctuates, the p-ch transistor
The output current capability of 26 fluctuates. Also, in the conventional circuit shown in FIG. 2, when the second positive power supply 15 fluctuates, the output current capability of the p-ch transistor 16 fluctuates.

[Problems to be solved by the invention]

In the above-described conventional semiconductor integrated circuit, all the back gates of the p-ch transistors for outputting a high level lower than the highest potential are connected to the highest potential. Therefore, when these p-ch transistors are turned on, the potential difference of the gate is determined by the highest potential, and there is a disadvantage that the current capability of these p-ch transistors changes due to the fluctuation of the potential.

An object of the present invention is to provide a semiconductor integrated circuit having a constant output current capability even when the maximum potential fluctuates.

[Means for solving the problem]

In a semiconductor integrated circuit according to the present invention, a first one-conductivity-type transistor whose source / drain path is connected between a first power supply line receiving a first power supply and an output terminal; A second power supply line receiving a second power supply having a voltage level higher than that of the first power supply and a second one-conductivity-type transistor connected between the output terminal; A third power supply line receiving a third power supply having a lower voltage level than each of the two power supplies, and a reverse conductivity type transistor connected between the output terminal and the third power supply line; Means for controlling which of the first one-conductivity-type transistor and the second one-conductivity-type transistor is turned on, and a buffer of the first one-conductivity-type transistor when the first one-conductivity-type transistor is on. Means for connecting a gate to the first power supply; and means for connecting the back gate of the first one conductivity type transistor to the second power supply when the second conductivity type transistor is conductive. The current driving capability of the first one conductivity type transistor is kept constant.

Further, when the potential of the output terminal is equal to or higher than the voltage level of the first power supply while the second one-conductivity-type transistor is in a conductive state, the back gate bias of the first one-conductivity-type transistor is changed to the second level. And a power supply voltage level.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention. The input signal 1 is data output from the output terminal 11, the control signal 2 is a control signal for controlling the potential of the positive output, and the first positive power supply 3 and the second positive power supply 4 are output from the output terminal 11. Two power supplies on the high level side of two outputs, a level conversion circuit 10 is a level conversion circuit for converting a logical output level, p-channel transistors 5 to 6 are transistors for controlling the output of an output terminal 11, and an n-channel transistor 9
Is a transistor for controlling the output of the output terminal 11. However, it is assumed that the second positive power supply 4 has a higher voltage than the first positive power supply 3.

First, when the input signal 1 is at the low level, the p-ch transistor 5 and the p-ch transistor 8 are independent of the control signal 2.
Are turned off, and the n-ch transistor 9 is turned on, so that the output terminal 10 outputs the GND level.

Next, when the input signal 1 is at the high level and the control signal 2 is also at the high level, the p-ch transistor 5 and the n-ch transistor 9 are turned off and the p-ch transistor 8 is turned on, so that the output terminal 10 Outputs a high level determined by the second positive power supply 4. At this time, the p-ch transistor 6 is turned on and the p-ch transistor 7 is turned off, so that the second positive power supply 4 is applied to the back gate of the p-ch transistor 5 and the second positive power supply 3 side No current flows through

Next, when the input signal 1 is at the high level and the control signal 2 is also at the low level, the p-ch transistor 5 is turned on, the p-ch transistor 8 and the n-ch transistor 9 are turned off, Output voltage is output. At this time,
According to the control signal 2, the p-ch transistor 7 is turned on,
By turning off the -ch transistor 6, the first positive power supply 3 is supplied to the back gate of the p-ch transistor 5, and the gate-source voltage of the p-ch transistor 5 becomes the potential of the first positive power supply 3. Only the second
, The high-level output current of the output terminal 11 does not change.

That is, the drive current of the p-ch transistor 5 can be made constant.

The conductivity type of the MOS transistor in the embodiment described above is not limited to this in the present invention, and the same effect can be obtained by changing the respective signals even if they are of the opposite conductivity type.

〔The invention's effect〕

As described above, according to the present invention, by supplying a constant voltage to the back gate for an element having an output lower than the highest potential, the output current characteristic of the output terminal can be made constant regardless of the fluctuation of the highest potential. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention, FIG. 2 is a circuit diagram for explaining a conventional example, and FIG. 3 is a circuit diagram for explaining another conventional example. It is. 1,12,22 …… Input signal, 2,13,23 …… Control signal, 3,14,24
... First positive power supply, 4, 15, 25... Second positive power supply, 5 to 8, 1
6-18,26-27 ... p-ch transistor, 9,19,28 ... n
-Ch transistor, 10,20,29 …… Level conversion circuit, 11,2
1,30 …… Output terminals.

Claims (2)

(57) [Claims] A first conductive type transistor having a source / drain path connected between a first power supply line receiving a first power supply and an output terminal; and a source / drain path connected to the first power supply line.
A second power supply line receiving a second power supply having a voltage level higher than that of the first power supply and a second one-conductivity-type transistor connected between the output terminal;
A third power supply line receiving a third power supply having a lower voltage level than each of the second power supply and a third conductive line connected between the output terminal and the reverse conductive type transistor; Means for controlling which of the first one-conductivity-type transistor and the second one-conductivity-type transistor is turned on, and the first one-conductivity-type transistor is turned on when the first one-conductivity-type transistor is on. Means for connecting a back gate to the first power supply;
Means for connecting a back gate of the first conduction type transistor to the second power supply when the one conduction type transistor is in a conducting state, so that the current driving capability of the first one conduction type transistor is kept constant. A semiconductor integrated circuit characterized by maintaining. 2. A back gate bias of the first one conductivity type transistor when the potential of the output terminal is equal to or higher than the voltage level of the first power supply while the second one conductivity type transistor is in a conductive state. 2. The semiconductor integrated circuit according to claim 1, wherein the voltage level is set to a voltage level of the second power supply.