JPH04269011A - Level shift circuit - Google Patents

Abstract

PURPOSE:To reduce the through-current and to improve the response speed by adding an N-channel MOSFET and a differentiating circuit to an input terminal and an output terminal of an inverter respectively. CONSTITUTION:An N-channel MOSFET Q5 and a differentiating circuit A are added to an input terminal of an inverter INV 1 of a conventional circuit and an N-channel MOSFET Q6 and a differentiating circuit B are added to an output terminal. FETs Q5, Q6 are turned on in the normal state. When a level of a signal D changes from H to L, a FET Q3 is turned from OFF to ON, a potential at a point (c) of the FET Q5 changes from VDD2 into (VDD2-VDD1) by the differentiating circuit A and the FET Q5 is turned off and no through-current is caused. A potential at a point (a) is equal to a voltage VSS2 immediately, a FET Q1 is turned off and the FET Q5 is gradually turned on. In this case, a potential at a point (d) is changed from VDD2 into (VDD2+ VDD1), but since the FET Q6 keeps the ON state, the level at the point (b) is equal to the voltage VDD2 and the FET Q6 is made stable. Since the processing of the circuit is similarly when the level of the signal D changes from L to H, no through-current is caused.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to a level shift circuit composed of MOSFETs.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional level shift circuit includes first MOSFETs Q1 and Q2 and a second MOSFET
It has FETQ3 and Q4.

Next, the operation of the circuit shown in FIG. 3 will be explained.

When signal D is “H”, FET Q3 is “O”.
FF”, FETQ4 is turned “ON”, and the potential at point b becomes the same potential as the power supply voltage VSS2.
Q1 becomes “ON” and the potential at point a is the power supply voltage VDD2.
The potential becomes the same as that of FETQ2, and FETQ2 turns "OFF" and becomes stable.

When the signal D is "L", FETQ3 is "ON", FETQ4 is "OFF", and the potential at point a becomes the same potential as power supply voltage VSS2. This allows F
ETQ2 turns "ON", the potential at point b becomes the same potential as VDD2, and FETQ1 turns "OFF", resulting in a stable state.

Therefore, when signal D changes from "H" to "L", FETQ3 changes from "OFF" to "ON", but at this time, FETQ1 is also "ON", so a through current flows. The current consumption increases. Furthermore, because of this through current, it takes time to determine the potentials at points a and b, which impairs the response speed. Similarly, signal D
A through current also flows when the voltage changes from "L" to "H".

[0007]

SUMMARY OF THE INVENTION As mentioned above, this conventional level shift circuit has the problem of not only large current consumption but also poor response speed due to the large through current.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to solve the above-mentioned problems inherent in the conventional technology, reduce current consumption, and improve the response speed of level shift operation. The object of the present invention is to provide a novel level shift circuit that makes it possible to improve the level shift circuit.

[0009]

[Means for Solving the Problems] In order to achieve the above object, a level shift circuit according to the present invention includes a first MOSFET.
One end of the ET is connected to one end of the second MOSFET, and the other end of the second MOSFET is connected to one end of the third MOSFET, forming a basic circuit. A basic circuit is arranged, the gate of the second MOSFET of the opposing basic circuit and the connection point of the second and third MOSFET are respectively connected in a sash shape, and the output end of the first inverter is connected to the first group. The input terminal of the first inverter is connected to the gate of the third MOSFET of the basic circuit of the second set and one end of the first capacitor. and connect the other end of the first capacitor to one end of the first capacitor.
one end of the resistor and the first M of the second set of basic circuits.
the other end of the second capacitor is connected to the gate of the OSFET, and the other end of the second capacitor is connected to a second resistor and the first MOSFET of the first set.
It is configured by connecting to the gate of ET.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Referring to FIG. 1, the first embodiment according to the present invention connects the drains of P-type MOSFETs Q1 and Q2 and the drains of N-type MOSFETs Q3 and Q4, respectively.
Connect the gates of FETQ1 and Q2 and the drains of FETQ4 and Q3, respectively, to create a depletion N-type MOSFE.
Connect the drains of TQ5 and Q6 to the sources of FETQ1 and Q2, respectively, and connect the input terminal of inverter INV1 to the FET
Connect the gate of Q4 to one end of capacitor C1, connect the other end of capacitor C1 to one end of resistor R1 and the gate of FET Q5, connect the output end of inverter INV1 to the gate of FET Q3 and one end of capacitor C2, and connect the other end of capacitor C1 to one end of resistor R1 and the gate of FET Q5.
This circuit has a configuration in which the other end of the resistor R2 is connected to one end of the resistor R2 and the gate of the FET Q6.

Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be explained.

[0014] Depletion N-type MOSFETQ5,
Q6 is "ON" in a steady state. Signal D is “H”
→ When FETQ3 is “L”, FETQ3 changes from “OFF” to “ON”, but FETQ5 changes to “OFF” because the potential at point C becomes VDD2 →VDD2 −VDD1 due to differentiating circuit A.
”, and the through current disappears.The potential at point a immediately becomes the voltage V
It becomes the same potential as SS2, FETQ1 turns “OFF”,
Gradually, FETQ5 becomes "ON". At this time, the potential at point d is changed by differentiating circuit B to VDD2 → VDD2 +V
DD1, but since FETQ6 maintains the "ON" state, the potential at point b becomes the same potential as voltage VDD2 and becomes stable. The same thing happens when the signal D changes from "L" to "H", so there is no through current.

FIG. 4 is an operation timing chart of the first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a second embodiment of the present invention.

The difference between the second embodiment shown in FIG. 2 and the first embodiment shown in FIG. 1 is that the depletion N type M
OSFETQ5 and Q6 are depletion P type MOSF
It has been replaced by ETQ7 and Q8. Therefore, the way the wiring is routed is different. The operation of this second embodiment is almost the same as that of the first embodiment described above.

[0018]

As explained above, in the conventional level shift circuit shown in FIG. 3, when the high-voltage side high-level power supply VDD2 = 30V and the high-voltage side low-level power supply VSS1 = 0V, the through current is 600V.
However, according to the level shift circuit of the present invention,
The effect is that the current is reduced to 30 μA, 1/20, and the response speed is also increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment according to the present invention.

FIG. 3 is a circuit diagram of a conventional level shift circuit.

FIG. 4 is a timing chart showing changes in potential at each point in FIG. 1;

[Explanation of symbols]

Q1...P type (enhancement) MOSFETQ2...P
Type (enhancement) MOSFETQ3...N type (enhancement) MOSFETQ4...N type (enhancement) MOSFETQ5...N type (depression) M
OSFETQ6...N type (depression) MOSFE
TQ7...P type (depletion) MOSFETQ8...
P-type (depression) MOSFET R1...Resistor R2...Resistor C1...Capacitor C2...Capacitor A...Differentiating circuit B...Differentiating circuit INV1...Inverter D...Data signal

Claims (2)

[Claims] Claim 1: One end of the first MOSFET and the second MOSFET
One end of the OSFET is connected, and the other end of the second MOSFET and one end of the third MOSFET are connected as a basic circuit, and a second set of basic circuits is arranged to form a pair with this basic circuit. The second MOSF of the basic circuit
The gate of the ET and the connection points of the second and third MOSFETs are connected in a sash shape, and the output terminal of the first inverter is connected to the gate of the third MOSFET of the first set of basic circuits and the first capacitor. and connect the input terminal of the first inverter to one end of the third MOS of the second set of basic circuits.
connecting the gate of the FET to one end of a second capacitor, and connecting the other end of the first capacitor to one end of a first resistor and the gate of the first MOSFET of the second set of basic circuits; A level shift circuit characterized in that the other end of the second capacitor is connected to a second resistor and a gate of the first MOSFET of the first set. 2. The first MOSFET is a depletion N-type MOSFET or a depletion P MOSFET.
Claim 1 further characterized in that a type MOSFET is used.
The level shift circuit described in .