JPH01154620A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a steady-state current from being caused to flow to the input by connecting a gate of a FET used for pull-up or pull-down input to an output of an input inverter. CONSTITUTION:A gate of a FET 4 acting like pull-up operation is connected to an output of an inverter 3. When an input terminal 5 used in the open state, the outpnt of the inverter 3 goes to a low level and the gate of the EET 4 goes to a zero potential and the FET 4 is sable in the on-state. This is applied similarly to the case with the input terminal 5 applied with a high level. With the input terminal 5 applied with a low level, the output of the inverter 3 goes to a high level, the FET 4 is turned off to open the power terminal and the input terminal 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that pulls up or pulls down an input terminal of an integrated circuit.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit is shown in FIGS.
), the inverter output 6 is provided on the output side of the inverter 3 from the input terminal 5 through the input protection circuit 1, and either terminal of the input protection resistor and one end of the power supply are connected with a resistor to create a pull-up or pull-down circuit. was forming. Further, as shown in FIGS. 3(e) and 3(f), an input protection circuit 2 is provided on the input side in place of the resistor 41, and a P-type MO5FET or an N-type MO3FET is connected to the positive terminal or negative terminal of the power supply, respectively. was connected to form a pull-up or pull-down circuit.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuit described above is shown in FIGS. 3(a) to 3(d).
), the disadvantage is that increasing the resistance requires a large area and increases the size of the semiconductor integrated circuit. Since it uses on-resistance, the third
Although the circuits in FIGS. 3(a), (c), and (e) have the advantage of being smaller in area than the cases in FIGS. 3(a) to 3(d), the input terminal 5 is forced to be low. In this case, a potential difference equal to the power supply voltage occurs between the input terminal 5 and the pull-up power supply terminal, and the circuits of FIGS. 3(b), (d), and (f) force input terminal 5 to be high. In this case, a potential difference equal to the power supply voltage occurs between the input terminal 5 and the pull-down ground terminal, and the pull-up/pull-down element (i.e., resistor 41 or MOSFET 4) and protection circuit 2 in both cases
The operation of integrated circuits has the disadvantage that unnecessary direct current flows through them.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a first input protection circuit and a second input protection circuit, one end of which is connected to an input terminal of an integrated circuit that is connected to an input of an inverter via the first input protection circuit. and a MOS whose drain is connected to the other end of the second input protection circuit, whose gate is connected to the output of the inverter, and whose source is connected to either one of the power supply terminals.
FET.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention.

1 and 2 are input protection circuits for the integrated circuit, 3 is an input inverter, 5 is an input terminal, 6 is an inverter output connected to the inside of the integrated circuit, and 4 acts as a pull-up (here, P
The source of the FET 4 is connected to the power supply terminal, and the drain is connected to the protection circuit 2. Here, the feature of the present invention is that the gate of FET 4 is connected to the output of inverter 3.

When the input terminal 5 of the integrated circuit is used open, the input terminal 5 becomes the same potential as the power supply terminal due to subthreshold leakage of the FET 4, the output 6 of the inverter 3 becomes low, and the gate of the P-type MOSFET 4 becomes zero potential. As a result, MOSFET 4 is stabilized in the on state. When high is applied to input terminal 5, the state is 0, which is the same as the above state.
Next, when a low voltage is applied to the input terminal 5, the output 6 of the inverter 3 becomes high, the gate potential of the P-type MOSFET 4 becomes the power supply voltage, the MOSFET 4 turns off, and the connection between the power supply terminal and the input terminal 5 becomes high. The space will be open.

That is, although current flows transiently, no steady current flows through the input protection circuit 2 and MOSFET 4.

Next, FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention. This is the case for pull-down inputs and MO
SFET4 uses an N-type MOSFET. When the input terminal 5 is open, the output 6 of the inverter 3 becomes high, and the MOSFET 4 becomes on and stable. The same applies when the input terminal 5 is open. Furthermore, when the input terminal 5 is high, the output 6 of the inverter 3 becomes low and M
03FET4 is turned off, protection circuit 2 and MOSFE
No steady current flows through T4.

In all embodiments, the input protection circuit 2 is composed of a series element of a resistor and a semiconductor diode connected to -m so that a potential in the opposite direction to the conduction direction of the diode is applied.

〔Effect of the invention〕

As explained above, by connecting the gate of the FET used for the pull-up or pull-down input to the output of the input inverter, the present invention can be used not only when the input is open but also when the input is forced to a high or low level. This has the effect that no steady current flows through the input even when applied.

In other words, even if you want to use the same integrated circuit with the input open in one device and the input at high or low level in another device, the integrated circuit can be used without input current flowing, and external It has the advantage of traditional circuits of not requiring pull-up or pull-down resistors,
Even when voltage is applied to the input, direct current unnecessary for circuit operation is not caused to flow, and this plays a major role in reducing the current consumption of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention, and FIG.
The figure is a circuit diagram showing a configuration according to a conventional technique. 1.2...Input protection circuit, 3.Inverter, 4.
...MOSFET, 5...input terminal, 6...inverter output.

Claims (3)

[Claims] (1) a first input protection circuit; a second input protection circuit having one end connected to an input terminal of an integrated circuit connected to an input of an inverter via the first input protection circuit; 1. A semiconductor integrated circuit comprising: a MOSFET having a drain connected to the other end of the input protection circuit, a gate connected to the output of the inverter, and a source connected to either one of the power supply terminals. (2) The semiconductor integrated circuit according to claim 1, wherein the MOSFET is a P-channel FET, and the source of the P-channel FET is connected to a positive power supply terminal. (3) The semiconductor integrated circuit according to claim 1, wherein the MOSFET is an N-channel FET, and the source of the N-channel FET is connected to a negative power supply terminal.