JPS633513A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS633513A
JPS633513A JP61147507A JP14750786A JPS633513A JP S633513 A JPS633513 A JP S633513A JP 61147507 A JP61147507 A JP 61147507A JP 14750786 A JP14750786 A JP 14750786A JP S633513 A JPS633513 A JP S633513A
Authority
JP
Japan
Prior art keywords
fet
mos
logic circuit
threshold voltage
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61147507A
Other languages
Japanese (ja)
Inventor
Hiroyuki Obata
弘之 小畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61147507A priority Critical patent/JPS633513A/en
Publication of JPS633513A publication Critical patent/JPS633513A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To eliminate the power voltage dependance of a threshold value by interposing one conduction type depletion MOS-FET of having a large ON- resistance whose gate is connected to an output terminal in series between the said output terminal and the other conduction type MOS-FET constituting a CMOS logic circuit. CONSTITUTION:Since the on-resistance of a P-channel enhancement MOSFETQ1 of a CMOS inverter is sufficiently smaller than the on-resistance of an N-channel depletion MOSFETQ3 to be inserted, the threshold voltage depends on the threshold voltage of the N-channel depletion MOSFETQ3 and the N-channel enhancement MOSFETQ2, but the threshold voltage of the depletion MOSFETQ3 is independent of the power voltage, then the logical threshold voltage is independent of the power voltage. Further, the power consumption is less.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体回路に関し、特に相補型ＭＯ３−ＦＥＴ
″′Ｃ−構成された論理回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor circuits, and particularly to complementary MO3-FETs.
″′C-Relating to constructed logic circuits.

〔従来の技術〕[Conventional technology]

従来の相補型ＭＯ３−ＦＥＴで構成された論理回路は、
第３図にその一例を示したように、Ｐチャンネル　エン
ハンスメント型ＭＯ３−ＦＥＴＱ１１とＮチャンネル・
エンハンスメント型Ｍ　ＯＳ　−ＦＥＴＱ、□で構成さ
れている。A logic circuit composed of conventional complementary MO3-FETs is
As an example is shown in Fig. 3, P-channel enhancement type MO3-FETQ11 and N-channel enhancement type MO3-FETQ11
It is composed of enhancement type MOS-FETQ, □.

第３図の論理回路は、入力ＩＮの２値信号に応答してオ
ンオフし、入力ＩＮと逆極性の出力ＯＵＴを発生するイ
ンバータである。The logic circuit shown in FIG. 3 is an inverter that turns on and off in response to a binary signal at the input IN and generates an output OUT having a polarity opposite to that of the input IN.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の相補型ＭＯＳ−ＦＥＴて構成された論理
回路は、第４図のＢ（破線）で示したように、論理しき
い値電圧が電源電圧■ｃｃに依存する為、広い電源電圧
の範囲で論理回路の論理しきい値電圧を狭い入力レベル
の範囲内に設定することができないという問題点がある
。　　゛〔問題点を解決するための手段〕 本発明の回路は、−導電チャンネル・エンハンスメント
型の第１のＭ　ＯＳ　　Ｆ　Ｅ　Ｔと、該第１のＭＯ８
−ＦＥＴと逆導電チャンネル・エンハンスメント型の第
２のＭＯ３−ＦＥＴで構成された論理回路において、前
記第１のＭＯ３−ＦＥＴと該論理回路の出力との間に第
１のＭＯ３−ＦＥＴのＯＮ抵抗より充分高いＯＮ抵抗を
有する逆導電チャンネル・ディプリーション型の第３の
ＭＯ３−ＦＥＴを直列接続すると共に該第３のＭＯ３−
ＦＥＴのゲート電極を該論理回路の出力に接続したこと
を特徴とする。The logic circuit configured with the conventional complementary MOS-FET described above has a logic threshold voltage that depends on the power supply voltage ■cc, as shown by B (broken line) in FIG. There is a problem in that the logic threshold voltage of the logic circuit cannot be set within a narrow input level range. [Means for Solving the Problems] The circuit of the present invention includes: - a first MOSFET of conductive channel enhancement type;
- In a logic circuit configured with a FET and a second MO3-FET of a reverse conduction channel enhancement type, an ON resistance of the first MO3-FET is provided between the first MO3-FET and the output of the logic circuit. A reverse conduction channel depletion type third MO3-FET having a sufficiently higher ON resistance is connected in series, and the third MO3-FET is connected in series.
It is characterized in that the gate electrode of the FET is connected to the output of the logic circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明による第１の実施例を示す回路図であり
、Ｐチャンネル・エンハンスメント型ＭＯＳ　−Ｆ　Ｅ
ＴＱ、とＮチャンネル・エンハンスメント型Ｍ　ＯＳ　
　Ｆ　Ｅ　Ｔ　Ｑ　２で構成されたインバータ回路であ
って、Ｐチャンネル・エンハンスメント型Ｍ　ＯＳ　−
Ｆ　Ｅ　Ｔ　Ｑ　１　とインバータの出力ＯＵＴとの間
にＮチャンネル・ディプリーション型ＭＯ３−ＦＥＴＱ
３を直列接続すると共にＮチャンネル・ディプリーショ
ン型Ｍ　ＯＳ　−Ｆ　Ｅ　Ｔ　Ｑ　３のゲート電極をイ
ンバータ回路の出力ＯＵＴに接続している。FIG. 1 is a circuit diagram showing a first embodiment according to the present invention, in which a P-channel enhancement type MOS-FE
TQ, and N-channel enhancement type MOS
An inverter circuit composed of FETQ2, which is a P-channel enhancement type MOS-
An N-channel depletion type MO3-FETQ is connected between FETQ1 and the inverter output OUT.
3 are connected in series, and the gate electrode of the N-channel depletion type MOS-FET Q 3 is connected to the output OUT of the inverter circuit.

第１図において、入力ＩＮに論理しきい値電圧近傍の電
圧が印加された場合のＰチャンネル・エンハンスメント
型Ｍ　ＯＳ　　Ｆ　Ｅ　Ｔ　Ｑ　１のＯＮ抵抗がＮチャ
ンネル・ディプリーション型ＭＯ３ＦＥＴＱ、の○Ｎ抵
抗に比べて十分小さければ、論理しきい値電圧はＮチャ
ンネル・ディプリーションＭ　ＯＳ　−Ｆ　Ｅ　Ｔ　Ｑ
　３及びＮチャンネル・エンハンスメント型Ｍ　ＯＳ　
　Ｆ　Ｅ　Ｔ　Ｑ　２のしきい値電圧だけで決定される
が、−般にデイプリージョンＭＯ３−ＦＥＴの論理しき
い値電圧は電源電圧に依存しない為、第４図のＡ（実線
）で示したように論理しきい値電圧は電源電圧に依存し
ない。In Fig. 1, when a voltage near the logic threshold voltage is applied to the input IN, the ON resistance of P-channel enhancement type MOSFET Q1 is equal to ○N of N-channel depletion type MO3FETQ. If it is sufficiently small compared to the resistance, the logic threshold voltage will be N-channel depletion MOS -FETQ
3 and N channel enhancement type MOS
Although it is determined only by the threshold voltage of FETQ2, in general, the logical threshold voltage of a depletion MO3-FET does not depend on the power supply voltage, so it is shown by A (solid line) in Fig. 4. As mentioned above, the logic threshold voltage does not depend on the power supply voltage.

又、入力ＩＮに電源電圧ＶＣＣに等しい電圧のＨｉｇｈ
レベルが印加された場合、Ｐチャンネル・エンハンスメ
ント型Ｍ　ＯＳ　−Ｆ　Ｅ　Ｔ　Ｑ　１がＯＦＦする為
、インバータ回路を貫通してり、Ｃ，的に電流が流れず
消費電力が非常に小さくなる。In addition, a high voltage equal to the power supply voltage VCC is applied to the input IN.
When a level is applied, the P-channel enhancement type MOS-FET Q1 is turned off, so that no current flows through the inverter circuit, and the power consumption becomes extremely small.

上述した第１の実施例はインバータ回路であるが、本発
明によればＮｏｐ、回路若しくはＮ　ＡＮ　Ｄ回路も構
成できることは明らかであり、本発明による第２の実施
例としてＮＯＲ回路を第２図に示す。Although the first embodiment described above is an inverter circuit, it is clear that according to the present invention, a NOR circuit or a NAND circuit can also be configured. Shown below.

第２図において、直列接続されたＰチャンネル・エンハ
ンスメント型Ｍ　ＯＳ　−Ｆ　Ｅ　Ｔ　Ｑ　４及ヒＱ５
と並列接続されたＮチャンネル・エンハンスメント型Ｍ
　ＯＳ　　Ｆ　Ｅ　Ｔ　Ｑ　６及びＱ７でＮＯＲが構成
されまた、Ｐチャンネル・エンハンスメント型ＭＯ３−
ＦＥＴＱ、とＮＯＲの出力ＯＵＴとの間にＮチャン′ネ
ル・デイプリージョン型ＭＯ３−ＦＥＴＱ３を直列接続
すると共にＮチャンネル・ディプリーション型〜１０Ｓ
−ＦＥＴＱ３のゲート電極がＮＯＲの出力に接続されて
いる。このＮＯＲ回路の動作は上述したインバータ回路
と同様であるので、動作の説明は省略する。In FIG. 2, P-channel enhancement type MOS-FET Q4 and HQ5 are connected in series.
N-channel enhancement type M connected in parallel with
A NOR is configured with OS FET Q6 and Q7, and a P channel enhancement type MO3-
N-channel depletion type MO3-FETQ3 is connected in series between FETQ and NOR output OUT, and N-channel depletion type ~10S
- The gate electrode of FETQ3 is connected to the output of NOR. Since the operation of this NOR circuit is similar to that of the inverter circuit described above, a description of the operation will be omitted.

［、発明の効果〕 以上説明したように本発明は、−導電チャンネル・エン
ハンスメント型の第１のＭＯＳ　−Ｆ　Ｅ　Ｔと、第１
のＭＯＳ−ＦＥＴと逆導電チャンネル・エンハンスメン
ト型の第２のＭＯＳ−ＦＥＴで構成された論理回路にお
いて、第１のＭＯ３ＦＥＴと論理回路の出力との間に第
１のＭＯ３−ＦＥＴのＯＮ抵抗より充分高いＯＮ抵抗を
有する逆導電チャンネル・ディプリーション型の第３の
ＭＯ５−ＦＥＴを直列接続すると共に第３のＭＯ３−Ｆ
　Ｅ　Ｔのゲート電極を論理回路の出力に接続すること
により、電源電圧を依存しない論理しきい値電圧が得ら
れるという効果がある。[Effects of the Invention] As explained above, the present invention provides a conductive channel enhancement type first MOS FET;
In a logic circuit composed of a MOS-FET and a second MOS-FET of reverse conduction channel enhancement type, the distance between the first MO3-FET and the output of the logic circuit is more than the ON resistance of the first MO3-FET. A reverse conduction channel depletion type third MO5-FET having high ON resistance is connected in series, and a third MO3-F
By connecting the gate electrode of ET to the output of the logic circuit, there is an effect that a logic threshold voltage that is independent of the power supply voltage can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は本発明による第１及び第２の実施
例を示す回路図、第３図は従来例を示す回路図および第
４図は論理回路の特性を示した図である。 ■ｃｃ・・・・・・電源、ＩＮ・・・・・・入力、ＯＵ
Ｔ・・・・・・出力、１・・・・・・信号端子、Ｑｌ、
Ｑ４．Ｑｓ　、Ｑｌｌ・・・・・・Ｐチャンネル・エン
ハンスメント型Ｍ　ＯＳ　−Ｆ　Ｅ　′ｒ、Ｑｓ　・・
・・・Ｎチャンネル・ディプリーション型ＭＯＳ　−Ｆ
　ＥＴ、　Ｑ２　、　Ｑ６　、　Ｑ７　、　Ｑ１０・・
・・・・Ｎチャンネル・エンハンスメント型ＭＯＳ−Ｆ
ＥＴ。 Ｙ１固　　　　　　　　　＄ｚダ 嚇 第３別 Ｙ＋図1 and 2 are circuit diagrams showing first and second embodiments according to the present invention, FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a diagram showing characteristics of a logic circuit. ■cc...Power supply, IN...Input, OU
T...Output, 1...Signal terminal, Ql,
Q4. Qs, Qll...P channel enhancement type MOS-FE'r, Qs...
...N-channel depletion type MOS -F
ET, Q2, Q6, Q7, Q10...
...N-channel enhancement type MOS-F
E.T. Y1 solid $z da threat 3rd separate Y+ figure

Claims (1)

【特許請求の範囲】[Claims] 一導電チャンネル・エンハンスメント型の第１のＭＯＳ
−ＦＥＴと、該第１のＭＯＳ−ＦＥＴと逆導電チャンネ
ル・エンハンスメント型の第２のＭＯＳ−ＦＥＴで構成
された論理回路において、前記第１のＭＯＳ−ＦＥＴと
該論理回路の出力との間に第１のＭＯＳ−ＦＥＴのＯＮ
抵抗より充分高いＯＮ抵抗を有する逆導電チャンネル・
ディプリーション型の第３のＭＯＳ−ＦＥＴを直列接続
すると共に該第３のＭＯＳ−ＦＥＴのゲート電極を該論
理回路の出力に接続したことを特徴とする論理回路。One conductive channel enhancement type first MOS
-FET, and a logic circuit configured of the first MOS-FET and a second MOS-FET of a reverse conduction channel enhancement type, between the first MOS-FET and the output of the logic circuit. Turning on the first MOS-FET
Reverse conducting channel with ON resistance sufficiently higher than the resistance
A logic circuit comprising a depletion type third MOS-FET connected in series and a gate electrode of the third MOS-FET connected to an output of the logic circuit.
JP61147507A 1986-06-23 1986-06-23 Logic circuit Pending JPS633513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61147507A JPS633513A (en) 1986-06-23 1986-06-23 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61147507A JPS633513A (en) 1986-06-23 1986-06-23 Logic circuit

Publications (1)

Publication Number Publication Date
JPS633513A true JPS633513A (en) 1988-01-08

Family

ID=15431924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61147507A Pending JPS633513A (en) 1986-06-23 1986-06-23 Logic circuit

Country Status (1)

Country Link
JP (1) JPS633513A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7677850B2 (en) 2006-06-01 2010-03-16 Newfrey Llc Clip comprising a pin and a bush
US7862272B2 (en) 2004-05-31 2011-01-04 Piolax Inc. Clip
JP2022083085A (en) * 2020-11-24 2022-06-03 株式会社東芝 Semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548683A (en) * 1978-09-29 1980-04-07 Mitetsuku Moderune Ind Tech Gm Method of measuring time with high accuracy

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548683A (en) * 1978-09-29 1980-04-07 Mitetsuku Moderune Ind Tech Gm Method of measuring time with high accuracy

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7862272B2 (en) 2004-05-31 2011-01-04 Piolax Inc. Clip
US7677850B2 (en) 2006-06-01 2010-03-16 Newfrey Llc Clip comprising a pin and a bush
JP2022083085A (en) * 2020-11-24 2022-06-03 株式会社東芝 Semiconductor integrated circuit

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