JPS62222713A - Cmos inverter circuit for delay - Google Patents

Abstract

PURPOSE:To decrease the change in the delay due to the fluctuation of power voltage by operating a CMOS inverter circuit while using a constant current circuit comprising MOSFET as a current source in a semiconductor integrated circuit using insulation gate field effect transistor (TR) MOSFET. CONSTITUTION:Gates comprising a P-channel MOSFET 11 and an N-channel MOSFET 12 are connected together to form an input terminal as a CMOS inverter. Further, a depletion type is used for an N-channel MOSFET 13 and the current I1 flowing to the MOSFET 13 is expressed as I1=(1/2)beta.(VTND)<2> because the source and gate of the MOSFET 13 are both connected to -VSS, where beta is a conductance constant and -VTND is a threshold voltage. That is, the current flowing to the MOSFET 13 is constant independently of the fluctuation of power voltage. Since the CMOS inverter circuit comprising the MOSFETs 11, 12 uses the MOSFET 13 as the constant current source, the response speed, that is, the delay time is constant independently of the power voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as M
The present invention relates to improving the voltage characteristics of a delay circuit constituted by an inverter circuit in a semiconductor integrated circuit using an OS FET (abbreviated as OSFET).

[Prior art] As one of the delay elements in a semiconductor integrated circuit using a conventional MOSFET, a P-type MOSF as shown in Fig. 6 is used.
A CMOS inverter circuit consisting of an ET and an N-type MOSFET has been used as an easily usable delay circuit by setting the conductance constant β to a small value.

[Problem that the invention seeks to solve]

However, if a CMOS inverter circuit as shown in FIG. 6 is used as a delay circuit, the delay time will fluctuate as the power supply voltage fluctuates, which may cause malfunctions.
Alternatively, there is a problem in that the operating power supply voltage is limited. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a delay inverter circuit in which the amount of delay changes little even when the power supply voltage fluctuates, and further provides a semiconductor integrated circuit using the delay CMOS inverter circuit of the present invention. The purpose is to expand the operating power supply voltage range of the circuit.

[Means for solving problems]

The delay CMOS inverter circuit of the present invention is a) MOSF
In a semiconductor integrated circuit using ET, b) a CMOS inverter circuit consisting of a P-type MOSFET and an N-type MOSFET whose gates and drains are connected in common, respectively; and C) one electrode is a t current source on one side of the CMOS inverter circuit. A constant current circuit consisting of MOS FETs connected so that

[Effect]

According to the above configuration of the present invention, the responsiveness of the CMOS inverter circuit is not dominated by the current value of the constant current circuit, and the current value of the constant current circuit remains constant even when the power supply voltage fluctuates. The responsiveness, or delay time, of an inverter circuit remains constant even when the power supply voltage fluctuates.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, the source of the P-type MOSFET M1 is connected to +VDD, which is the positive power supply potential, and the drain is connected to the N-type MOSFET M1.
Connected to the drain of SFET. P-type MOSFE
The gates of T11 and N-type MOSFET 12 are connected to each other and serve as input terminals of a CMOS inverter circuit. The drains are also connected to each other and serve as output terminals as a CMOS inverter circuit. N-type MO3FET
The source and gate of 13 are negative power supply potentials - V8B
The drain is connected to the source of MOSFET 12. The N-type MOSFET 13 is a depletion type MOSFET with a conductance constant β and a threshold voltage f, −VTx.

Then, the current flowing through MOSFET 13 is MOS
Since the source and gate of FET 13 are both connected to "-vss," it is expressed as 1!=-β・(Vtd)2.In other words, the current flowing through MOSFET Is is not affected by fluctuations in the power supply voltage and remains a constant value. Adashi.

It can be seen that MOSFET 15 serves as a constant current source. Since the CMOS inverter circuit consisting of MOSFETs 11 and 12 uses MO8FE'l'13 as a constant current source, the response speed and delay time are constant values independent of the power supply voltage.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The circuit shown in FIG. 2 is a modified version of the constant current circuit. In the circuit shown in Figure 2, N-type MOS FET23.25 and P
A constant current circuit is configured by the type MOSFET 24. P-type MOSFET 240 source and gate are 10Vnn
It is connected to the.

The source of N-type MOSFET 25 is connected to -VS8,
The gate and drain are connected to each other, and the MOS F
Connected to the drain of E T 24.

7- and < of the N-type MOSFET 23 are connected to -VSS, and the gate is connected to the drain of the MOSFET 25. The P-type MOSFET 24 is a depletion type with a conductance constant βPi and a threshold voltage -VTPD, and the conductance constants of the N-type MOSFETs 23 and 25 are βNo and β81, respectively. Also, assuming the drain potential of MO8F'FJT2s to be Vat, 5-
If Vat1 is set to 0 potential, and the currents flowing through MOSFETs 23 and 25 are respectively IO and If, the following equation holds true.

Solving the above equation gives us. From this IoO equation, it can be seen that the V10SFET 23 serves as a constant current source that is independent of the power supply voltage. In addition, a CMOS inverter circuit is configured by a P-type MOSFET 21 and an N-type MOSFET 22, and the P-type MOSFET 11 and N-type MOSFET + 2 of the circuit shown in
are equivalent to each.

From the above, it can be seen that the circuit shown in FIG. 2 also constitutes a delay CMOS inverter circuit that is not affected by fluctuations in the power supply voltage. It can be seen from the circuit of FIG. 2 that there are various ways of configuring the constant current circuit.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. In Fig. 3, P-type MOSFET 51 and N-type MOSFET
32 constitutes a CMOS inverter circuit, and the P-type depletion MOSFET 63 constitutes a constant current circuit. The constant current source MOSFET 33 is composed of a P-channel depletion type transistor, and +vDD
MOSFET 1 of the circuit in Figure 1 except that the side is used as a power supply.
MOSFETs 31 and 32 respectively correspond to MOSFETs 11 and 12 in the circuit of FIG. 1, and the principle is the same as that of the circuit of FIG. The circuit shown in FIG. 5 is an example showing that the constant current source may be configured on the +Voo side.

Is Fig. 4 the fourth embodiment of the present invention? FIG. Although FIGS. 1 to 3 show an example of one inverter circuit, it is of course applicable to a case of a plurality of inverter circuits, and FIG. 4 shows an example of two inverter circuits. In the circuit shown in Figure 4, P-type MOSFET41 and N-type MOS
One CMOS inverter circuit is configured by FET42, and P-type MOSFET44 and N-type MOSFET45
Another CMOS inverter circuit is configured. N-type MOSFET 45 is the MOS of the circuit in Figure 1.
A constant current circuit corresponding to FET13 with two CMO
It serves as a common constant current source for the S inverter circuit. Therefore, the circuit shown in FIG. 4 also constitutes a delay CMOS inverter circuit that is less susceptible to fluctuations in the power supply voltage.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention. In the circuit shown in Figure 5, P-type MOSFET51 and N-type MOS
One CMOS inverter circuit is configured by the FET 52, and the P-type MOSFET 54 and the N-type MOSFET 5
5 constitutes another CMOS inverter circuit. The N-type MOSFETs 53 and 56 are both depletion type, and constitute separate constant current circuits. The circuit of FIG. 5 shows an example in which a plurality of constant current circuits are also prepared when there are a plurality of inverter circuits.

〔Effect of the invention〕

As described above, according to the present invention, a constant current circuit is used as a current source in a CMO.
Since the S inverter circuit is operated, there is an effect of providing a delay CMOS inverter circuit in which the amount of delay changes little even if the power supply voltage fluctuates. Further, there is an effect of expanding the operating power supply voltage range of a semiconductor integrated circuit using the delay CMOS inverter circuit of the present invention. Furthermore, the fact that the influence of fluctuations in the power supply voltage is small has the effect of providing a delay CMOS inverter circuit and a semiconductor integrated circuit that are resistant to noise caused by transient currents and the like.

[Brief explanation of drawings]

FIGS. 1, 2, 3, 4, and 5 are the first and second embodiments of the present invention, respectively. Second. 6th. 4th. A circuit diagram showing the fifth embodiment, and FIG. 6 is a circuit diagram showing an example of a conventional delay inverter circuit. 11.21, 51, 41, 44, 51, 54...
・P-type MOSFET 12.22, 23, 25, 32, 42, 45°52.5
5...N-type MOSFET24.33...
・PWf7'resion MOSFET15, 45, 5
5, 56... Kawa-N type depression MO8FwaT Applicant: Seiko Epson Co., Ltd.

Claims (1)

[Claims] (1)a) Insulated gate field effect transistor (hereinafter M
b) a CMOS inverter circuit consisting of a P-type MOSFET and an N-type MOSFET whose gates and drains are connected in common, respectively, and c) one electrode of which is connected to one side of the CMOS inverter circuit. 1. A delay CMOS inverter circuit comprising: a constant current circuit including a MOSFET connected to serve as a current source.