JPH04117721A - Input circuit with pull-up function - Google Patents

Input circuit with pull-up function

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Publication number
JPH04117721A
JPH04117721A JP2236443A JP23644390A JPH04117721A JP H04117721 A JPH04117721 A JP H04117721A JP 2236443 A JP2236443 A JP 2236443A JP 23644390 A JP23644390 A JP 23644390A JP H04117721 A JPH04117721 A JP H04117721A
Authority
JP
Japan
Prior art keywords
pull
mosfet
input circuit
power supply
current flowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2236443A
Other languages
Japanese (ja)
Inventor
Masayuki Oshima
大嶋　正幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2236443A priority Critical patent/JPH04117721A/en
Publication of JPH04117721A publication Critical patent/JPH04117721A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make a current flowing to a pull-up MOSFET constant independently of a power supply voltage by adopting a depletion type MOSFET for the pull-up MOSFET. CONSTITUTION:A source electrode 105 and a gate electrode 106 in a depletion P-channel MOSFET 102 are connected to a power supply VDD and a drain electrode 107 is connected to an input terminal 103 to form a pull-up circuit. Since the gate electrode 106 of the depletion type P-channel MOSFET 102 is connected to the power supply VDD, when the voltage between the source 105 and the drain 107 exceeds the threshold voltage of the depletion type P- channel MOSFET 102, a current flowing between the source and the drain is constant independently of the power supply voltage. Thus, the current flowing to the pull-up MOSFET is constant independently of the power supply voltage.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体集積回路におけるプルアップ付入力回
路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit with a pull-up in a semiconductor integrated circuit.

［従来の技術］ 従来のプルアップ付入力回路のプルアップ用ＭＯＳＦＥ
Ｔは、第２図に示されるようにエンハンスメント型ＭＯ
ＳＦＥＴであった。[Prior art] Pull-up MOSFE of conventional input circuit with pull-up
T is an enhancement type MO as shown in FIG.
It was an SFET.

［発明が解決しようとする課題］ 従来のプルアップ付入力回路は前述したようにプルアッ
プ用ＭＯＳＦＥＴがエンハンスメント型ＭＯＳＦＥＴで
形成されている為、電ｆｉ電圧によりプルアップ用ＭＯ
ＳＦＥＴを流れる電流が変化するという問題点を有する
。[Problems to be Solved by the Invention] As mentioned above, in the conventional input circuit with a pull-up, the pull-up MOSFET is formed of an enhancement type MOSFET, so the pull-up MOSFET is
The problem is that the current flowing through the SFET changes.

そこで本発明は従来のプルアップ付入力回路の問題点を
解決するもので、その目的とするところは、ブルア・ン
ブＭＯＳＦＥＴを流れる電ン蚕が電源電圧に依存せず定
電流であるプルアップ付入力回路を提供するところにあ
る。Therefore, the present invention solves the problems of the conventional input circuit with a pull-up.The purpose of the present invention is to provide a pull-up input circuit in which the current flowing through the blue MOSFET is a constant current independent of the power supply voltage. This is where the input circuit is provided.

［課題を解決するための手段］ 本発明のプルアップ付入力回路は、 ａ）ＭＯＳＦＥＴを用いた半導体集積回路においで、 ｂ）入力回路と、 Ｃ）前記入力回路内に設けられたプルアップ用ＭＯＳＦ
ＥＴとからなり、 ｄ）前記プルアップ用ＭＯＳＦＥＴがデプリーション型
ＭＯＳＦＥＴであることを特徴とする。[Means for Solving the Problems] An input circuit with a pull-up according to the present invention includes: a) a semiconductor integrated circuit using MOSFET, b) an input circuit, and C) a pull-up provided in the input circuit. MOSF
d) The pull-up MOSFET is a depletion type MOSFET.

〔実　施　例ｊ 本発明の第１の実施例として第１図にプルアップ付入力
回路の回路図を示す。[Embodiment j] FIG. 1 shows a circuit diagram of an input circuit with a pull-up as a first embodiment of the present invention.

第１図において１０１は入力回路であり、１０３は入力
回路１０１の入力端子であり、１０４は入力回路１０１
の出力端子である。In FIG. 1, 101 is an input circuit, 103 is an input terminal of the input circuit 101, and 104 is an input terminal of the input circuit 101.
This is the output terminal of

１０２はデブリ〜ジョンＰ型ＭＯＳＦＥＴであり、ソー
ス電極１０５とゲート電極１．０６がＶ。０に接続し、
ドレイン電極１０７が入力端子１０３に接続してプルア
ップ回路を形成している。102 is a debris P-type MOSFET, and the source electrode 105 and gate electrode 1.06 are at V. Connect to 0,
Drain electrode 107 is connected to input terminal 103 to form a pull-up circuit.

ここでデプリーションＰ型ＭＯＳ　Ｆ　ＥＴのゲト電極
１０６が■。Ｄに接続している為、ソース電極］０５と
ドレイン電極１０７の間の電位差が、デプリーションＰ
型ＭＯ５ＦＥ丁１０６のスレッショルド電圧以上になる
とソース・ドレイン間を流れる電流は電？Ｉ！電圧に依
存せず一定となる。Here, the gate electrode 106 of the depletion P-type MOS FET is . Since it is connected to D, the potential difference between the source electrode] 05 and the drain electrode 107 becomes depletion P.
When the threshold voltage of the MO5FE type 106 is exceeded, the current flowing between the source and drain becomes a current. I! It remains constant regardless of voltage.

このように第１図のようなプルアップ用ＭＯ３ＦＥＴに
デプリーションＰ型Ｍ　ＯＳ　Ｆ　Ｅ　Ｔを用いる構成
により、プルアップ用ＭＯＳＦＥＴを流れる電流が電源
電圧に依存せず一定であるプルアップ付入力回路を作成
することが出来る。尚１本発明の実施例におけるＭ　Ｏ
Ｓ　Ｆ　Ｅ　ＴのタイプをＮチャンネルとし、ｉｔ源の
関係を逆にすれば、プルダウン抵抗としても実施するこ
とができる。In this way, by using a depletion P-type MOSFET as the pull-up MOSFET as shown in Figure 1, it is possible to create an input circuit with a pull-up in which the current flowing through the pull-up MOSFET is constant regardless of the power supply voltage. Can be created. Note 1: M O in the embodiment of the present invention
If the type of SFET is set to N-channel and the relationship between the IT sources is reversed, it can also be implemented as a pull-down resistor.

［発明の効果］ 以上述べたように、本発明によればプルアップ用ＭＯＳ
ＦＥＴをデプリーション型ＭＯＳＦＥＴにすることによ
り、プルアップ用Ｍ　ＯＳ　Ｆ　Ｅ　Ｔを流れる電流が
電源電圧に依存せず一定であるプルアップ付入力回路を
得られるという効果がある。[Effects of the Invention] As described above, according to the present invention, the pull-up MOS
By using a depletion type MOSFET as the FET, it is possible to obtain an input circuit with a pull-up in which the current flowing through the pull-up MOSFET is constant regardless of the power supply voltage.

また、プルアップ用ＭＯＳＦＥＴのゲート電極の電位が
ソース電極の電源と同一であるため、パターンのレイア
ウトが容易で配線面積を縮小できるという効果もある。Further, since the potential of the gate electrode of the pull-up MOSFET is the same as the power source of the source electrode, there is an effect that the pattern layout is easy and the wiring area can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の第１の実施例を示すプルアップ付入
力回路の回路図である。 第２図は、従来例を示すプルアップ付入力回路の回路図
である。 １０１　　、２０１　・ １０２　・ ２０２　・ １０３． １０４． １０５． １０６． １０７． ２０３　・ ２０４　・ ２０５　　・ ２０６　・ ２０７　・ ・入力回路 デプリーションＰ型ＭＯＳ ＥＴ ・エンハンスメントＰ型ＭＯ ＦＥＴ ・入力端子 出力端子 ・ソース電極 ・ゲート電極 ・ドレイン電極 以上 出願人　セイコーエプソン株式会社 代理人　弁理士　鈴　木　喜三部（他１名）￥ ユFIG. 1 is a circuit diagram of an input circuit with a pull-up, showing a first embodiment of the present invention. FIG. 2 is a circuit diagram of a conventional input circuit with pull-up. 101 , 201 ・ 102 ・ 202 ・ 103. 104. 105. 106. 107. 203 ・ 204 ・ 205 ・ 206 ・ 207 ・ ・Input circuit Depletion P-type MOS ET ・Enhancement P-type MO FET ・Input terminal Output terminal ・Source electrode ・Gate electrode ・Drain electrode Applicant Seiko Epson Corporation Agent Patent attorney Suzu Kisanbe (1 other person) ￥ Yu

Claims (1)

【特許請求の範囲】 ａ）絶縁ゲート電界効果トランジスタ（以下、Ｍ＠Ｏ＠
ＳＦＥＴと略す）を用いた半導体集積回路において、 ｂ）入力回路と、 ｃ）前記入力回路内に設けられたプルアップ用Ｍ＠Ｏ＠
ＳＦＥＴとからなり、 ｄ）前記プルアップ用Ｍ＠Ｏ＠ＳＦＥＴがデプリーショ
ン型Ｍ＠Ｏ＠ＳＦＥＴであることを特徴とした、プルア
ップ付入力回路[Claims] a) Insulated gate field effect transistor (hereinafter referred to as M@O@
In a semiconductor integrated circuit using a semiconductor integrated circuit (abbreviated as SFET), b) an input circuit, and c) a pull-up M@O@ provided in the input circuit.
d) An input circuit with a pull-up, characterized in that the pull-up M@O@SFET is a depletion type M@O@SFET.
JP2236443A 1990-09-06 1990-09-06 Input circuit with pull-up function Pending JPH04117721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2236443A JPH04117721A (en) 1990-09-06 1990-09-06 Input circuit with pull-up function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2236443A JPH04117721A (en) 1990-09-06 1990-09-06 Input circuit with pull-up function

Publications (1)

Publication Number Publication Date
JPH04117721A true JPH04117721A (en) 1992-04-17

Family

ID=17000831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2236443A Pending JPH04117721A (en) 1990-09-06 1990-09-06 Input circuit with pull-up function

Country Status (1)

Country Link
JP (1) JPH04117721A (en)

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