JP2734531B2 - Logic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and particularly to a magnitude comparison logic circuit configured by a semiconductor integrated circuit.

[Conventional technology]

FIG. 3 shows a conventional size comparison logic circuit of this kind. Third
In the circuit shown in the figure, 11 NAND gate circuits 26 and 4 NOR gates are provided.
A gate circuit 28 and eight AND gate circuits 27 were provided. 15 to 25 are input terminals, and 29 is an output terminal.

[Problems to be solved by the invention]

The size comparison logic circuit in the prior art has a very large number of elements, significantly increases the current consumption and chip area of the semiconductor integrated circuit, and has a very complicated circuit configuration. There is a disadvantage that it is difficult to configure a circuit.

An object of the present invention is to provide a magnitude comparison logic circuit that solves the above-mentioned problem.

[Means for solving the problem]

To achieve the above object, a logic circuit according to the present invention comprises:
A first pair of P-channel and N-channel MOS transistors, a second pair of P-channel and N-channel MOS transistors, a third P-channel and N-channel MOS
Complementary circuits are respectively constituted by a pair of transistors and a pair of fourth P-channel and N-channel MOS transistors, and the source electrodes of the first, third and fifth P-channel MOS transistors are connected to a positive power supply. , The drain electrodes of the first and third P-channel MOS transistors are connected to the drain electrodes of the first and third N-channel MOS transistors, and the drain electrode of the fifth P-channel MOS transistor is connected to the fourth P-channel MOS transistor. A source electrode of a channel type MOS transistor is connected, an output terminal 16 is connected to a source electrode of a first N channel type MOS transistor, and a source electrode of a second P channel type MOS transistor. The drain electrode of the fourth P-channel MOS transistor and the drain electrodes of the second and fourth N-channel MOS transistors are connected to the drain electrode of the transistor, Connecting the drain electrode of the sixth N-channel MOS transistor to the source electrode of the third N-channel MOS transistor; connecting the source electrodes of the second, fourth, and sixth N-channel MOS transistors to a negative power supply; The gate electrodes of the first and fifth P-channel MOS transistors and the gate electrodes of the second and sixth N-channel MOS transistors are connected to a first input terminal, and the gate of the second P-channel MOS transistor is connected. An electrode and a gate electrode of the first N-channel MOS transistor are connected to a second input terminal; a gate electrode of a third and fourth P-channel MOS transistor; and a third and fourth N-channel MOS transistor The gate electrode of the transistor was connected to the third input terminal.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of a magnitude comparison logic circuit of the present invention.

The magnitude comparison logic circuit of the present invention comprises a pair of first P-channel type and N-channel type MOS transistors 3, 4, a second pair of P-channel type and N-channel type MOS transistors 5, 6, and a third pair.
The pair of P-channel and N-channel MOS transistors 7 and 8 and the pair of fourth P-channel and N-channel MOS transistors 11 and 12 constitute complementary circuits.

Then, the first, third and fifth P-channel type MOs are connected to the positive power supply.
The source electrodes of the S transistors 3, 7, and 10 are connected, and the drain electrodes of the first and third P-channel MOS transistors 3, 7 and the drain electrodes of the first and third N-channel MOS transistors 4, 8 are connected. Connected to the fifth P-channel MOS transistor 1
Fourth P-channel MOS transistor at the drain electrode of 0
11 is connected to the source electrode of the first N-channel MOS transistor 4, the output terminal 16 is connected to the source electrode of the second P-channel MOS transistor 5, and the second
The drain electrode of the fourth P-channel MOS transistor 11 and the drain electrodes of the second and fourth N-channel MOS transistors 6 and 12 are connected to the drain electrode of the P-channel MOS transistor 5 of FIG. The drain electrode of the sixth N-channel MOS transistor 9 is connected to the source electrode of the N-type MOS transistor 8, and the source electrodes of the second, fourth and sixth N-channel MOS transistors 6, 9, 12 are connected to the negative power source 2 And the gate electrodes of the first and fifth P-channel MOS transistors 3 and 10 and the second and sixth N-channel MOS transistors.
The gate electrodes of the transistors 9 and 6 are connected to the first input terminal 14, and the gate electrode of the second P-channel MOS transistor 5 and the gate electrode of the first N-channel MOS transistor 5 are connected to the second input terminal. 13 and the gate electrodes of the third and fourth P-channel MOS transistors 7, 11 and the third,
The gate electrodes of the fourth N-channel MOS transistors 8 and 12 are connected to a third input terminal 15.

Here, in the present invention, the input terminal 1 of the magnitude comparison circuit
FIG. 2 shows a truth table for 3, 14, 15 and the output terminal 16. As is apparent from FIG. 2, the input terminal 13 is represented by a binary number.
When the logical value applied to the input terminal 14 is greater than the logical value applied to the input terminal 14, a logical value “1” is output to the output terminal 16 and the logical value applied to the input terminal 13 is applied to the input terminal 14. When the value is smaller than the applied logical value, “0” is output to the output terminal 16 as a logical value. When the same logical value is applied to the input terminals 13 and 14, a logical value obtained by logically inverting the logical value applied to the input terminal 15 is output to the output terminal 16.

〔The invention's effect〕

As described above, according to the present invention, by employing a circuit configuration using complementary circuits, it is possible to reduce the number of elements constituting the size comparison logic circuit in a semiconductor integrated circuit, reduce current consumption and chip area, and further reduce bit slices. The configuration has an effect that a magnitude comparison logic circuit having an arbitrary bit width can be easily configured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a truth table showing the operation of a magnitude comparing logic circuit of the present invention, and FIG. FIG. 3 is a circuit diagram illustrating a logic circuit. 1 Positive power supply 2 Negative power supply 3,5,7,10,11 P-channel MOS transistor 4,6,8,9,12 N-channel MOS transistor 13,14,15 Input terminal, 16 Output terminal

Claims (1)

(57) [Claims] 1. A first P-channel type and N-channel type MOS
A transistor pair, a second P-channel and N-channel MOS transistor pair, a third P-channel and N-channel MOS transistor pair, and a fourth P-channel and N-channel MOS transistor pair. Complementary circuits are formed respectively, and the source electrodes of the first, third, and fifth P-channel MOS transistors are connected to the positive power supply, and the first and third P-channel MOS transistors are connected.
The drain electrode of the MOS transistor is connected to the drain electrodes of the first and third N-channel MOS transistors, and the source electrode of the fourth P-channel MOS transistor is connected to the drain electrode of the fifth P-channel MOS transistor. The output terminal 16 is connected to the source electrode of the first N-channel MOS transistor and the source electrode of the second P-channel MOS transistor, and the fourth P-channel MOS transistor is connected to the drain electrode of the second P-channel MOS transistor. The drain electrode of the N-type MOS transistor is connected to the drain electrodes of the second and fourth N-channel MOS transistors, and the drain electrode of the sixth N-channel MOS transistor is connected to the source electrode of the third N-channel MOS transistor. Connecting the source electrodes of the second, fourth, and sixth N-channel MOS transistors to a negative power source;
Connecting the gate electrode of the MOS transistor and the gate electrodes of the second and sixth N-channel MOS transistors to a first input terminal;
A gate electrode of the first N-channel MOS transistor is connected to the second input terminal; a gate electrode of the third and fourth P-channel MOS transistors; and a gate of the third and fourth N-channel MOS transistors A logic circuit comprising an electrode connected to a third input terminal.