JP2917693B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor integrated circuit, and more particularly to an interface for a semiconductor integrated circuit having different power supply voltages.

[0002]

2. Description of the Related Art As shown in FIG. 6, an interface of a conventional semiconductor integrated circuit has an input buffer as shown in FIG.
Channel MOS transistor (hereinafter, PMOS) 10
And an N-channel MOS transistor (hereinafter, NMOS)
20 and a CMOS gate 30, the PMOS1
The gate of the NMOS 20 and the N-type buried region (hereinafter referred to as N-well) constituting the PMOS 10 are connected to a power source, the gate of the NMOS 20 and the P-type semiconductor substrate constituting the NMOS 20 are connected to the ground.
The input terminal of the OS gate 30 is connected to the external terminal 60.

Further, in a conventional three-state output buffer, as shown in FIG.
It comprises an OS 20, a two-input NAND gate 31, a two-input NOR gate 32, and an inverter gate 33. As in the case of the input buffer, the P-type semiconductor substrate forming the NMOS 20 is powered by the N-well forming the PMOS 20 as a power supply. Connected to ground. Here, by setting the enable terminal 40 to a low level, a two-input NAND
The output of gate 31 is a high level, two-input NOR gate 32
Output becomes low level, and each output is connected to PM
Both the OS 10 and the NMOS 20 are turned off, and the output becomes high impedance. At this time, the states of the PMOS 10 and the NMOS 20 are the same as those in FIG.

[0004]

As described above, in the conventional semiconductor integrated circuit shown in FIGS.
When the voltage higher than the power supply voltage is applied to the external terminal 60 and exceeds the forward voltage Vf of the parasitic diode 50, the power supply 70 Current flows through When the threshold voltage Vt of the PMOS 10 is smaller than the forward voltage Vf of the parasitic diode 50, the PMO
S10 is turned on, and a current flows similarly. Therefore, there is a problem that an interface between chips having different power supply voltages cannot be obtained. The purpose of the present invention is
It is an object of the present invention to provide a semiconductor integrated circuit which prevents such a current from an external terminal to a power supply and enables an interface between chips having different power supply voltages.

[0005]

According to the present invention, in a CMOS semiconductor integrated circuit, the potential of an N-type semiconductor layer serving as a base of a P-channel MOS transistor is set at V _DD 2 and the source of the P-channel MOS transistor is connected. Potential V
_DD 1, the voltage applied to the external terminal V _in, the P-channel
The forward voltage of the parasitic diode of the MOS transistor
Vf, threshold of the P-channel MOS transistor
The threshold voltage is Vt, and the P-channel MOS transistor
And a voltage source and the N-type semiconductor layers was V _sub
In order to satisfy both the following equations (1) and (3),
A semiconductor integrated circuit, wherein a potential of a semiconductor layer is set . _{V DD 2> V in -Vf ...} (1) V in <V DD 1 + f (V DD 2-V DD 1) ... (3) _{here, V sub = V DD 2-} V DD 1, Vt = f
(V _sub ): Vt is a function of V _sub

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is an input buffer circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. PMOS 10, NMOS 20,
And a CMOS gate 30, each having a source connected to a first power supply (hereinafter referred to as V _DD 1) 70 and the ground, and an N well constituting the PMOS 10 connected to a second power supply (hereinafter referred to as V _DD 2). , A P-type semiconductor substrate constituting the NMOS 20 is connected to the ground. Here, if V _in becomes voltage is applied to the external terminals 60,
In order to parasitic diode is not turned on, V _DD 2 may be V _DD 2> V _in -Vf ... in such a way that (1).

[0007] FIG. 2 is a characteristic diagram showing the voltage V _sub-source -N wells PMOS 10, the relationship between the threshold voltage Vt. V _sub is represented as _{V sub = V DD 2-V} DD 1 ... (2). As you increase the V _sub from the figure, it can be seen that the Vt also increases. Thus, Vt as a function f of the V _sub, can be expressed as Vt = f (V _sub). Here, PMOS against V _in becomes input voltage
For 10 is not turned _{on, V in <V DD 1 +} Vt = V DD 1 + f (V DD 2-V DD 1) ... (3) and may be set to be. Therefore, equation (1)
(3) by setting simultaneously V _DD 2 so as to satisfy the equation, the electric current does not flow even if applied power V _DD 1 of high input voltage V _in from the voltage.

FIG. 3 is a three-state output buffer circuit diagram of a semiconductor integrated circuit showing a second embodiment of the present invention . PMO
S10, NMOS 20, and 2-input NAND gate 3
1 and 2 input NOR gate 32 and inverter gate 3
3 as in the first embodiment.
The source of the NMOS 20 is connected to V _DD 1 and the ground, the N well forming the PMOS 10 is connected to V _DD 2, and the P-type semiconductor substrate forming the NMOS 20 is connected to the ground. Here, by setting the enable terminal 40 to a low level, both the PMOS 10 and the NMOS 20 are turned off, and the output becomes high impedance. At this time, the power supply V _DD 1 higher than the input voltage V _in to the external terminal 60
Is applied, in order for the current not to flow to V _DD 1,
As in the first embodiment, V _DD 2 may be set so as to simultaneously satisfy the expressions (1) and (3).

FIG. 4 shows a third embodiment of the present invention, in which a booster circuit 80 is connected to the input buffer of FIG. With this configuration, V _DD2 can be generated from V _DD1 by the booster circuit 80, and only a single power supply needs to be supplied. Similarly, a booster circuit 80 is provided in the fourth embodiment of the present invention shown in FIG.
It may be connected to, V by the booster circuit 80 from V _DD 1
Generates _DD 2 to enable configuration with a single power supply.

[0010]

As described above, according to the present invention, the potential of the N-type semiconductor layer serving as the base of the P-channel MOS transistor is increased.
V _DD 2, potential V _DD 1 to which the source of the P-channel MOS transistor is connected , voltage applied to an external terminal
V _in, the parasitic diode of the P-channel MOS transistor
Forward voltage Vf of the P-channel MOS transistor
Threshold voltage Vt of the P-channel MOS
The voltage between the source of the transistor and the N-type semiconductor layer is V
_{When sub} , V _DD 2> V _in -V f and V _in <V _DD 1
+ F (V _DD2 −V _DD 1), where (V _sub = V _DD 2−
V _DD 1, Vt = f (V _sub ): Vt is a function of V _sub )
Since it is configured to satisfy the relationship, the N-type semiconductor layer
The potential can be set to the minimum necessary potential,
Power consumption can be reduced, and even if a voltage higher than the power supply voltage is applied to the external terminal connected to the PMOS, current can be prevented from flowing from the external terminal to the power supply, and an interface between chips having different power supply voltages can be provided. There is an effect that can be taken.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input buffer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a substrate bias-threshold characteristic of a PMOS.

FIG. 3 is a circuit diagram of a three-state output buffer according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an input buffer according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a three-state output buffer according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of an example of an input buffer of a conventional semiconductor integrated circuit.

FIG. 7 is a circuit diagram of a conventional three-state output buffer.

[Explanation of symbols]

 Reference Signs List 10 PMOS 20 NMOS 30 CMOS gate 40 Enable terminal 50 Parasitic diode 60 External terminal 70 First power supply 71 Second power supply 80 Boost circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8234-21/8238 H01L 21/8249 H01L 27/06 H01L 27/08 331 H01L 27/088-27 / 092

Claims (1)

(57) [Claims] 1. A P-channel MOS transistor and an N-channel MOS transistor.
Complementary semiconductor integration composed of flannel MOS transistors
In the circuit, the base of the P-channel MOS transistor
The potential of the N-type semiconductor layerV _DD 2, saidP channel
The source of the MOS transistor is connectedPotential V
_DD 1. The voltage applied to the external terminal is V _in , The P channel
The forward voltage of the parasitic diode of the MOS transistor
Vf, threshold of the P-channel MOS transistor
The threshold voltage is Vt, and the P-channel MOS transistor
The voltage between the source and the N-type semiconductor layer is V _sub And
In order to satisfy both the following equations (1) and (3),
Potential of semiconductor layer was setSemiconductor collection characterized by the following:
Product circuit.V _DD 2> V _in −Vf (1) V _in <V _DD 1 + f (V _DD 2-V _DD 1)… (3) Where V _sub = V _DD 2-V _DD 1, Vt = f
(V _sub ): Vt is V _sub Function