JP2538986B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a Bi-CMOS circuit type logic circuit.

(Prior Art) A logic circuit based on a Bi-CMOS circuit system is a composite logic circuit composed of bipolar transistors and CMOS type transistors. This circuit is a highly advantageous logic circuit that combines the high speed of a bipolar transistor and the low power consumption of a CMOS transistor.

FIG. 8 is a circuit diagram showing the basic configuration of a conventional Bi-CMOS logic circuit. In the figure, 11 is a P-channel MOS transistor, 12 is an N-channel MOS transistor, 13 and 14 are NPN transistors, and 15 and 16 are impedance elements. The source of the transistor 11 is connected to the power supply potential Vcc, and the gate is connected to the input terminal In. The base of the NPN transistor 13 is connected to the drain of this transistor 11.
Power supply potential Vcc and output terminal Out between the collector and emitter of 13
Has been inserted between. The drain of the transistor 12 is connected to the output terminal Out, and the gate is connected to the input terminal In. The source of this transistor 12
The base of the NPN transistor 14 is connected, and the collector-emitter of the transistor 14 is inserted between the output terminal Out and the ground potential Vss. The impedance elements 15 and 16 are respectively formed by the transistor 13
Is inserted between the base and the emitter of the transistor, and between the base and the emitter of the transistor 14.

The above-mentioned conventional circuit is provided with a totem pole output stage composed of transistors 13 and 14, so that the MOS transistors 11 and 12 receive a change in potential supplied from the output terminal In.
The base current is supplied to the transistors 13 and 14, and the amplified signal is taken out to the output terminal Out.

For example, when the signal supplied to the input terminal In is switched from the “1” level to the “0” level, the MOS transistor 11 is turned on, and a current is supplied to the base of the NPN transistor 13 and the impedance element 15. As a result, the base-emitter voltage of the transistor 13 rises to its built-in potential voltage, and the transistor 13 is turned on. As a result, the load capacitance of the output terminal Out is rapidly charged by the emitter current of the transistor 13 and the output becomes "1" level. On the other hand, pre-biased by the impedance element 16,
Since the base accumulated charge of the transistor 14 that has been in the ON state is extracted by this impedance element 16,
Transistor 14 quickly turns off. This allows
Generation of a shoot-through current between the power supply potential Vcc and the ground potential Vss of the totem pole output stage due to the delay of the off operation of the transistor 14 is prevented.

On the other hand, when the signal supplied to the input terminal In is switched from the “0” level to the “1” level, the MOS transistor 12 is turned on and current is supplied to the base of the NPN transistor 14 and the impedance element 16. As a result, the voltage between the base and emitter of the transistor 14 rises to the built-in potential voltage, and the transistor 14 is turned on. As a result, the load current of the output terminal Out is rapidly discharged by the collector current of the transistor 14, and the output becomes "0" level. On the other hand, since the base accumulated charge of the transistor 13 which has been biased by the impedance element 15 and turned on in advance is extracted by this impedance element 15, the transistor 13 is rapidly turned off. This prevents the generation of a through current between the power supply potential Vcc and the ground potential Vss of the totem pole output stage due to the delay of the off operation of the transistor 13.

In the totem pole type Bi-CMOS logic circuit, resistors 17 and 18 are used as a concrete example of the impedance elements 15 and 16 for extracting the base accumulated charge of the bipolar transistor as shown in FIG. 9 ( JP 60-
165751), and a so-called Z method in which N-channel MOS transistors 19 and 20 are used as shown in FIG. 10 (JP-A-61-198817).

Further, in the past, as shown in FIG. 11, a transistor
An N-channel MOS transistor 21 is used as an impedance element for extracting the base accumulated charge of 13, and a resistor 22 is used as an impedance element for extracting the base accumulated charge of the transistor 14.
And a diode 23 connected between the emitter and the base of the transistor 13 so that the potential of the output terminal is used when discharging the output terminal Out. 27227).

The above conventional circuit can use about 5V as the power supply potential Vcc. In the submicron region where the channel length of the MOS transistor is slightly shorter than 1 μm, it is CM in terms of operating speed.
It is superior to the OS logic circuit. However, the channel length is 0.
When the size is reduced to about 5 μm, it is necessary to reduce the power supply potential Vcc to about 3 V, which causes the following problems.

If such a circuit is operated at a low power supply voltage Vcc of about 3 V, the collector-emitter voltage and collector-base voltage during operation of the transistors 13 and 14 are low, so that a sufficient current amplification factor cannot be obtained. . On the other hand, the source potential of the transistor 12 when it is turned on is the transistor
As it has 14 built-in potentials above the ground potential, the driving force is low due to the back gate effect and the reduction in the gate-source voltage and the source-drain voltage. Furthermore, the junction capacitance between the collector and the base of the transistor 14 becomes a mirror capacitance, which causes an increase in the rise and fall delay time. Therefore, when taking into consideration the decrease in the amplification factor of the transistor 14 and the decrease in the driving force of the transistor 12 due to the decrease of the power supply potential Vcc from 5V to 3V, the part related to the fall characteristic is to be included in the transistors 12, 14 and the impedance element Bi-CM like 16
There is not much advantage in using an OS configuration. Further, the device area of the bipolar transistor is large, and the use of two bipolar transistors in the totem pole stage hinders the improvement of the degree of integration.

Therefore, a circuit as shown in FIG. 12 was conceived as a device that operates at high speed and low power consumption and realizes an improvement in the degree of integration.
That is, it is a circuit configured to use only one bipolar transformer without forming a totem pole stage.

The configuration of the circuit shown in FIG. 12 is as follows. P channel
The source of the MOS transistor 31 is connected to the power supply potential Vcc, and the gate is connected to the input terminal In. The base of the NPN transistor 33 is connected to the drain of the transistor 31, and the collector-emitter of the transistor 33 is inserted between the power supply potential Vcc and the output terminal Out. The drain of the N-channel MOS transistor 34 is connected to the base of the transistor 33, the source is connected to the ground potential Vss, and the gate is connected to the input terminal In. The gate of the N-channel MOS transistor 35 is connected to the input terminal In, and the source / drain of the transistor 35 is inserted between the ground potential Vss and the output terminal Out.

The operation of the circuit shown in FIG. 12 will be described. First, input terminal In
When the signal supplied to is switched from the "1" level to the "0" level, the MOS transistor 31 is turned on and the MOS transistors 34 and 35 are turned off. As a result, all the drain current of the transistor 31 flows into the base of the NPN transistor 33, and the transistor 33 is rapidly turned on. As a result, the load capacitance of the output terminal Out is charged by the emitter current of the transistor 33, and the output terminal Out is set to "1".
The level signal is output.

On the other hand, when the signal supplied to the input terminal In is switched from the “0” level to the “1” level, the transistor 31 is turned off and the transistors 34 and 35 are turned on. As a result, the load capacitance of the output terminal Out is discharged via the transistor 35. At the same time, NP via transistor 34
The electric charge accumulated in the base of the N-transistor 33 is extracted, and the transistor 33 rapidly turns off. This prevents a shoot-through current between Vcc and Vss due to a delay in the off operation of the transistor 33.

With this configuration, the part related to the fall characteristic is not composed of Bi-CMOS, so
Compared to the totem pole type Bi-CMOS gate, the increase in delay time is suppressed.

However, in the configuration of this circuit, the CMOS logic gate circuit including the transistors 31 and 34 is connected to the base of the NPN transistor 33. Therefore, when a multi-input logic or a complicated logic is formed, the number of transistors 34 must be increased accordingly, which has a drawback that the degree of integration is reduced.

(Problems to be Solved by the Invention) As described above, conventionally, when a logic gate circuit driven by a low power supply voltage was manufactured, high-speed operation, low power consumption, and high integration could not be satisfied at the same time.

This invention was made in consideration of the above circumstances,
An object of the invention is to provide a highly integrated logic circuit which operates at high speed even at a low power supply voltage and with low power consumption.

[Structure of the Invention] (Means for Solving the Problems) A logic circuit of the present invention is a bipolar transistor having a collector connected to a first potential and an emitter connected to an output terminal, and an input signal supplied to a gate and a source. , A drain is provided between the first potential and the base of the bipolar transistor, and a first MOS transistor of the first conductivity type, the number of which corresponds to the input, and an input signal is supplied to the gate, and the source and the drain are the outputs. The second MOS of the second conductivity type, the number of which is according to the input provided between the terminal and the second potential.
It is composed of a transistor and an impedance element connected only between the base of the bipolar transistor and the output terminal.

(Function) The present invention makes the bipolar transistor only the one on the power supply side and operates the BiCMOS only at the time of rising,
Do not increase the delay time caused by the decrease in the power supply voltage. By forming an element for extracting the stored charge of the base of the bipolar transistor between the base and the emitter, a high-speed, low power consumption, highly integrated logic circuit can be obtained.

(Examples) Hereinafter, the present invention will be described by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration when the logic circuit of the present invention is applied to an inverter. The source of the P-channel MOS transistor 1 is connected to the power supply potential Vcc, and the gate of this transistor 1 is connected to the input terminal In. The gate of the N-channel MOS transistor 2 is connected to the input terminal In, and the source of the transistor 2 is ground potential.
It is connected to Vss. Further, the collector of the NPN transistor 3 is connected to the power supply potential Vcc.
The base of is connected to the drain of the MOS transistor 1. An impedance element 4 is inserted between the base and emitter of the NPN transistor 3. Then, the emitter of the NPN transistor 3 and the MOS transistor 2
The drains of are commonly connected, and the output terminal Out is connected.

The impedance element 4 is, for example, a resistor 5 as shown in FIG. 2, an N-channel MOS transistor 6 whose gate is connected to a power supply potential Vcc as shown in FIG.
As shown in the figure, P with its gate connected to the ground potential Vss
The channel MOS transistor 7 can be used.

Next, the operation of the circuit configured as described above will be described. When the signal supplied to the input terminal In is switched from the "1" level to the "0" level, the transistor 1 is turned on and the transistor 2 is turned off. As a result, a current is supplied to the impedance element 4 and the base of the NPN transistor 3. At this time, a potential difference is generated across the impedance element 4 and reaches the built-in potential voltage between the base and emitter of the transistor 3, so that the transistor 3 is turned on. As a result, the load current of the output terminal Out is rapidly charged by the emitter current of the transistor 3 and a "1" level signal is output to the output terminal Out.
On the other hand, when the signal supplied to the input terminal In is switched from the "0" level to the "1" level, the transistor 1 is turned off and the transistor 2 is turned on. This allows
The load capacitance of the output terminal Out is discharged via the transistor 2. At the same time, the base accumulated charge of the NPN transistor 3 is extracted via the resistor 5 and the transistor 2 in the ON state, so that the transistor 3 is turned off rapidly. This prevents shoot-through current between Vcc and Vss of the totem pole output stage.

With such a circuit configuration, high-speed operation can be realized with low power consumption even with a low-voltage power supply. Further, the logical circuit of the present invention can be easily expanded to a multi-input logical circuit by rational simplification of the circuit configuration.

FIG. 5 is a circuit diagram showing a configuration in which the logic circuit of the present invention is applied to a 2-input NAND gate circuit. Power supply potential Vc
P channel between c and the base potential of NPN transistor 3
The sources and drains of the MOS transistors 1-1 and 1-2 are inserted in parallel, and the transistors 1-1 and 1-
The two gates are connected to the input terminals In-1 and In-2, respectively. N-channel MOS transistor 2 is connected to input terminal In-1.
The gate of the N-channel MOS transistor 2-2 is connected to the gate of -1 and the input terminal In-2, and the output terminal Ou is connected between the sources and drains of the transistors 2-1 and 2-2.
It is connected in series between t and the ground potential Vss. An impedance element 4 is inserted between the base and emitter of the NPN transistor 3.

The operation of this circuit is such that when the input terminals In-1 and In-2 are both at the "1" level, both the transistors 1-1 and 1-2 are in the off state and the transistors 2-1 and 2-2 are both in the on state. Become. As a result, the load capacitance of the output terminal Out is discharged via the transistors 2-2 and 2-1 and the output terminal Out
A "0" level signal is output to. At this time as well, as described in the above circuit, the base element charge of the transistor 3 is extracted by the impedance element 4, and a through current between Vcc and Vss via the transistor 3 is prevented. On the other hand, when the transistors 1-1 and In-2 are both in a signal state other than the "1" level, one of the transistors 1-1 and 1-2 is always on, and one of the transistors 2-1 and 2-2 is always on. It is turned off. As a result, the transistor 3 is turned on, the load capacitance of the output terminal Out is rapidly charged, and the "1" level signal is output to the output terminal Out.

FIG. 6 is a circuit diagram showing the configuration when the present invention is applied to a 2-input NOR gate circuit. The sources and drains of the P-channel MOS transistors 1-1 and 1-2 are connected in series between the power supply potential Vcc and the base of the NPN transistor 3. The gates of the transistors 1-1 and 1-2 are connected to the input terminals In-1 and In-2, respectively. The input terminal In-1 has an N-channel MOS transistor 2-
The gate of N-channel MOS transistor 2-2 is connected to the input terminal In-2, and the source and drain of both transistors 2-1 and 2-2 are output terminals Out.
And ground potential Vss are connected in parallel. An impedance element 4 is connected between the base and emitter of the NPN transistor 3.

As described above, the logic circuit of the present invention can be easily expanded to a multi-input gate as shown in FIGS. 5 and 6, and the conventional problems of integration can be greatly reduced. In addition, such a configuration has an advantage that it can be applied to a complicated circuit such as a latch circuit. The impedance element 4 can also be a resistor, an N-channel MOS transistor, a P-channel MOS transistor or the like.

FIG. 7 shows the configuration of a modified example of the circuit of FIG. 1, in which an NPN transistor 8 with a Schottky barrier diode is used instead of the NPN transistor 3 in FIG. By using this transistor 8, it is possible to shorten the time for which the base accumulated charge is extracted, and it is possible to realize a higher speed operation.

With the circuit configuration of each of the above-described embodiments or modifications, for example, when operating with a low voltage power supply of around 3.3V, it operates at higher speed and lower power consumption than the conventional totem pole type BiCMOS logic circuit. Further, since the CMOS logic gate is not connected around the bipolar transistor on the power supply side, there is an advantage that the integration can be facilitated.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a logic circuit having a high degree of integration, which operates at a high speed even with a low voltage power supply and has a low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention, and FIGS. 2 to 4 are circuit diagrams of configurations specifically showing a part of the circuit of FIG. 1, FIGS. 5 and 6, respectively. Is a circuit diagram showing a configuration according to another embodiment of the present invention, FIG. 7 is a circuit diagram showing a configuration according to a modification of the embodiment circuit of FIG. 1,
8 to 12 are circuit diagrams each showing a configuration of a conventional Bi-CMOS logic circuit. 1 ... P-channel MOS transistor, 2 ... N-channel M
OS transistor, 3 ... NPN transistor, 4 ... Impedance element.

Claims (3)

(57) [Claims] 1. A logic circuit comprising at least one input, wherein a bipolar transistor having a collector connected to a first potential and an emitter connected to an output terminal, and an input signal supplied to a gate and a source and a drain connected to each other. First
First MOS of the first conductivity type, the number of which is according to the input provided between the potential of the bipolar transistor and the base of the bipolar transistor.
A transistor, a gate to which an input signal is supplied, and a source and a drain provided between the output terminal and the second potential, the second MOS transistors of the second conductivity type according to the input, and the bipolar transistor. A logic circuit comprising: only one impedance element connected between the base of the transistor and the output terminal. 2. The logic circuit according to claim 1, wherein the impedance element is composed of a resistor. 3. The logic circuit according to claim 1, wherein the impedance element is composed of a MOS transistor.