JPS62284523A - Ttl compatible amalgamater bipolar/cmos output buffer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. DETAILED DESCRIPTION OF THE INVENTION [Background of the Invention] The present invention generally relates to output buffer circuits. More specifically, high current drive capability and T.

The present invention relates to a composite bipolar/CMOS output buffer circuit with low propagation delay compatible with TL levels.

Conventional output buffer circuits using CMOS transistors are generally known in the prior art.

A major disadvantage of CMOS transistor technology is that they have low current drive capabilities that make them unsuitable for large capacitive loads. On the other hand, prior art CMO3 output buffer 8 circuits have been modified to use transistors with very large outputs to increase current drive for TTL level compatibility, thus causing substantial propagation delays at their outputs. Problems result.

Therefore, it would be desirable to provide a merged PIPO9F0MO8 output buffer circuit that offers the advantages of high current drive capacity and low propagation delay.

The invention is achieved by combining both bipolar transistor and CMOS transistor technologies. As a result, bipolar transistors and CMOS transistors are merged or placed on a common semiconductor substrate to form an integrated circuit output buffer arrangement.

SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a combined bibolar/CMOS output buffer circuit that is relatively simple and economical to manufacture and assemble, yet overcomes the disadvantages of conventional output buffer devices. The goal is to provide the following.

It is an object of this invention to provide a merged bipolar/CMOS output buffer circuit with current drive capacity and low propagation delay.

Another object of the invention is to provide an output buffer circuit formed of merged bipolar and CMOS transistors that provides two output states compatible with TTL levels.

Yet another object of the invention is to provide an output buffer circuit formed of merged bipolar and CMOS transistors that provides three distinct output states compatible with TTL levels.

In accordance with these aims and objectives, it is concerned with the provision of an output buffer circuit formed of merged bipolar and CMOS transistors to provide two output states compatible with TTL levels. The output buffer circuit includes a P-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply potential.

The first bipolar transistor has its collector connected to the power supply potential, its base connected to the drain of the P-channel transistor, and its emitter connected to the output terminal. The first N-channel MOS transistor has its gate connected to the input terminal and its drain connected to the power supply potential. The second bipolar transistor has its collector connected to the output terminal, its base connected via a resistor to the source of the first N-channel transistor, and its emitter connected to ground potential. The second N-channel MOS transistor has its gate connected to the drain of the P-channel transistor, its drain connected to the source of the first N-channel transistor, and its source connected to ground potential. The third N-channel MOS transistor has its gate connected to the input terminal, its drain connected to the drain of the P-channel transistor, and its source connected to ground potential. The third bipolar transistor has its base connected to the source of the first N-channel transistor, its collector connected to the base of the second bipolar transistor, and its emitter connected to the collector of the second bipolar transistor.

In another aspect of the invention, an output buffer circuit is provided that has three distinct output states and is formed from a plurality of CMOS transistors and a plurality of bipolar transistors.

These and other objects and advantages of the invention will become more fully apparent from the following detailed description, taken in conjunction with the accompanying drawings in which like reference numerals indicate corresponding parts throughout.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings in detail, a combined bipolar transistor/CMOS (complementary metal oxide semiconductor) output according to the present invention provides two output states compatible with TTL levels. A schematic circuit diagram of buffer device 10 is shown in FIG. Output buffer 10 has an input terminal 12 and an output terminal 14. The buffer device serves to convert the 0MO8 logic level received at the input terminal 1.2 to a TTL logic level at the output terminal 14 with increased current driving capacity and therefore shorter propagation delay.
Ru.

The buffer device 10 includes an N-channel MOS transistor Nl, a P-channel MOS transistor P3, and a first transistor Nl.
N-channel MOS transistor N2, second radiation ff1N
- Contains channel MOS transistor N4, pull-down bipolar transistor Q1 and pull-up bipolar transistor Q2.

The anti-saturation means for controlling the saturation effect of the pull-down bipolar transistor Q1 is
3 and a resistor R. It will be appreciated that, for convenience, P-channel transistors are designated by the letter P followed by specific reference numerals, and N-channel MOS transistors are designated by the letter N followed by specific reference numerals.

The N-channel MOS transistor N1 has its drain electrode connected to the power supply voltage or power supply potential VCC, its source electrode connected to the drain of the first discharge transistor N2, and its gate electrode connected to the input terminal 12. . Power supply potential vCC is typically +5.0 volts. Input terminal 12 receives an input logic symbol V, N that cycles between a low or rOJ logic state and a high or logic "1". At CMO3 input logic levels, a low state is approximately O volts and a high state is approximately power supply potential VCC, or +5.0 volts. The P-channel MOS transistor P3 has its source electrode connected to the power supply potential, and its drain connected to the second discharge transistor N.
4, and its gate is connected to the input terminal 12.

Pull-down bipolar transistor Q1 has its collector connected to the emitter of pull-up bipolar transistor Q2 and to output terminal 14. The emitter of the bipolar transistor Q1 is connected to the second discharge transistor N2.
source and ground potential. The base of transistor Q1 is connected to one end of resistor R and the collector of saturation control transistor Q3. The other end of resistor R is connected to the source of N-channel transistor N1, the drain of first discharge transistor N2 and the base of saturation control transistor Q3.

The emitter of transistor Q3 is connected to the collector of pulldown bipolar transistor Q1. The collector of pull-up bipolar transistor Q2 is connected to power supply potential vCC.

The base of transistor Q2 is connected to transistor P3°N4.
and the gate of transistor N2. The source of the second discharge transistor N4 is connected to the ground potential, and the base of the transistor N4 is connected to the input terminal 12.

Bipolar transistor Q1 defines a current sink transistor and operates as a pull-down element. Bipolar transistor Q2 defines a current source transistor and operates as a pull-up element. These transistors Q
1. Q2 is normally operated in what is known as a "bush/pull" mode. Bipolar transistor is CM
It has advantages over OS transistors, namely:
The former has the ability to provide higher current source/iti current sink capability used to drive capacitive output loads.

Anti-saturation means consisting of saturation control transistor Q3 and resistor R are used to control the saturation of pulldown bipolar transistor Q1, thereby eliminating the need for a Schottky diode. Therefore, the manufacturing complexity of the output buffer device 10 is minimized and
In this way costs are reduced. transistor Q
1 enters the saturation region, its collector-emitter voltage reduces the pull-down of the output voltage VO at the output terminal 14. The base-emitter voltage drop V, ε (Q3) on the transistor Q3 is calculated from the sum of the base-emitter voltage drop Va E (Q I) on the transistor Q1 and the voltage drop V on the resistor R, and the output voltage vo , i.e., VIIE(.,)+v,-V,
be equivalent to. The resistance value of resistor R and transistor Q3. Ql
Therefore, before transistor Q1 enters the tight saturation region, saturation control transistor Q3 conducts and transfers current from the base of transistor Q1 through transistor Q3 to transistor Q1.
, thereby preventing transistor Q1 from being forced further into the saturation region. As a result, excessive accumulated charge at the base of transistor Q1 is reduced to allow increased switching speed of operation.

N-channel transistor N2 provides a discharge path from the base of bipolar transistor Q1 to turn it off quickly, thereby facilitating and speeding up the low-to-high transition at output terminal 14. N-
Transistor N4 provides a discharge path from the base of bipolar transistor Q2 to turn it off quickly, thereby facilitating and speeding up the high-to-low transition at output terminal 14. Output buffer device 10 It should be understood by those skilled in the art that bipolar transistors Q1 . may be formed on a single silicon chip in a monolithic integrated circuit.
Even if Q2 and Q3 are all NPN type conductive,
It may be noted that these transistors may be replaced with PNP types.

Now, the operation of the output buffer device 10 of the present invention configured as described above will be explained. Assuming input logic signal VIN is in a low or "0" state, P-channel MOS transistor P3 will be conductive and N-channel MOS transistor N1 will be rendered non-conductive.

When the transistor P3 conducts, a drive current is applied to the base of the bipolar transistor Q2, turning it on and pulling up the output voltage.

As a result, output terminal 14 will begin charging quickly toward a high or "1" state. This output voltage VO in the high state is a voltage drop V(p,
) minus the sum of the base-emitter voltage V, ε(Ql) across bipolar transistor Q2. Generally, the voltage V (p a) is approximately +0.2
Volt, and the voltage VB E (Q 2) is approximately +0.8
It's a bolt. Therefore, the output voltage VO in the high state will be approximately +4.0 volts.

The input logic signal VIN at the input terminal 12 is switched from the low level state, and the sum of the threshold voltages of the transistors N1 and Ql, that is, V□(M,)+Va E(Q
I) When the transistor Nl increases by more than I).

Ql will begin to conduct to pull down the output voltage at output terminal 14. As a result, the output voltage VO will be pulled down to a low or rOJ state. This output voltage vo in the low state is equal to the collector-emitter voltage drop VCE (
Q+).

For a low-to-high transition at input terminal 12, it is necessary to turn off transistor Q2 as quickly as possible when transistor Q1 is turned on to reduce the delay in the high-to-low transition at output terminal 14. When the input signal is in a high state due to the fact that the gate of transistor N4 is pulled up, transistor N4 turns on quickly, so in order to discharge its excess base charge, the ground from the base of transistor Q2 is There will be a conductive discharge path to. A high to low transition at input terminal 12 requires transistor Q1 to be turned off as quickly as possible when transistor Q2 is turned on to reduce the delay of the low to high transition at output terminal 14. When the input signal is in a low state due to the fact that the gate of transistor N2 is pulled up through transistor P3, transistor N2 turns on quickly, so in order to discharge its excess base charge, the base of transistor Q1 There will be a conductive discharge path from ground to ground.

In FIG. 2, the present invention's merged bipolar/0
A schematic circuit diagram of an MO5 output buffer device 110 is shown. Output buffer device 110 of FIG. 2 includes all of the components of buffer device 10 of FIG. 1, and also includes two additional enabling P-channel MOS transistors P5, P6 and two additional discharge N-channel MOS
Transistor N7. Contains N8. All of the components in FIG. 2 are identical to those in FIG. 1 and are designated by the same reference numerals. The difference between FIG. 1 and FIG. 2 is that four MOS transistors P5. As there are connections in P6, N7 and N8, only these connections will be described.

In particular, the enabling P-channel transistor P5 has its source electrode connected to the power supply potential vCC, its drain electrode connected to the source electrode of the P-channel transistor P3, and its gate electrode connected to the second input terminal 13. ing. A second input terminal 13 receives an enabling signal VEN that alternates between a low state and a high state. The enabling P-channel transistor P6 has its source electrode also connected to the supply potential vCC, its drain electrode connected to the drain of the N-channel transistor N1, and its gate electrode connected to the second input terminal 13. . The discharge N-channel transistor N7 has its drain electrode connected to the base of the bipolar transistor Q2, its source electrode connected to ground potential, and its gate electrode connected to the second input terminal 13. The discharge N-channel transistor N8 has its drain electrode connected to the base of the bipolar transistor Q1 via the resistor R, its source electrode connected to ground potential, and its gate electrode connected to the second input terminal 13. There is.

Only the differences in operation of FIG. 2 from FIG. 1 will be discussed. When the enabling signal vEN is in the high state, both P-channel transistors P5°P6 are made non-conducting;
Both bipolar transistors Ql, Q2 will therefore be turned off regardless of the state of the input logic signal applied to the first input terminal 12. As a result, the output voltage v
o will be at the 3-state or ``floating'' state level. This three-state level is a voltage approximately at an intermediate level between the high state level and the low state level. Each transistor Q2. To remove any accumulated charge from the base of Ql, N
- channel transistor N7. N8 are both turned on, thereby ensuring that they will remain off. When the enable signal VEN is in a low state, the power supply potential VCC is connected to the P-channel transistor P3.
and the drain of N-channel transistor N1, both P-channel transistors P
5. P6 will become conductive. Accordingly, the operation of buffer device 110 will be the same as that just described with respect to FIG.

In FIG. 3, a second embodiment of the output buffer circuit of FIG. 1, designated by reference numeral 210, is shown. The output buffer circuit 10 of FIG. 1 has a disadvantage in that the output voltage in the low level state is controlled by the resistance value of resistor R.

Resistor values must be manufactured accurately, which increases manufacturing costs. Furthermore, buffer circuit 10 does not adequately compensate for changes in the resistance of resistor R at high operating temperatures. Buffer circuit 210 is an improved version of the circuit of FIG. 1, and includes all of the components of FIG. 1, and further includes bipolar transistors Q4. Q5 and resistor R1 are added.

Components that are the same or function similarly in FIG. 1 are given the same reference numerals and generally will not be described again.

Bipolar transistor Q4. Q5 forms a voltage source and resistors R1, R form a voltage divider. N-channel MOS transistor N2 has its drain connected to the base of bipolar transistor Q1 and functions as an active pull-down transistor to reduce the low-to-high transition time at output terminal 14. The gate and source electrodes of transistor N2 are connected in the same manner as in FIG. The collector and base of diode-connected transistor Q4 are connected together to the emitter of transistor Q5. The emitter of transistor Q4 is connected to ground potential. The collector and base of diode-connected transistor Q5 are coupled together and further connected to the source of first N-channel transistor N1 and one end of resistor R1.

The other end of resistor R1 is connected to the other end of resistor R.

In operation, the output voltage in the low level state may be controlled by the ratio of the resistor R1,H and the base-emitter (Vaε) voltage of the transistors Ql, Q4 and Q5, which can be more easily adjusted in the manufacturing process. Dew. In other words, when the human logic voltage VIN is in a high level state, the transistor Q2 is turned off, and
The voltage at the common collector base of transistor Q5 is VaE(Q*)+VaE(Qs). Therefore, the voltage drop across resistor R1,H is SVa E(Q a)+Va E(Q ri V
a E(Q +)i:: will be equal. Resistor R
1,R will act as a voltage divider to provide a controlled bias voltage across the collector-base junction of transistor Q3. As a result, the output voltage at output terminal 14 in the low level state will remain substantially constant. Since the circuit operation of FIG. 3 is the same as that described with respect to FIG. 1, a detailed discussion of its operation will not be repeated again.

In FIG. 4, a third embodiment of the output buffer circuit of FIG. 1, designated by the reference numeral 310, is illustrated. As can be seen, output buffer circuit 310 includes the circuit of FIG. 3 and an additional N-channel MOS transistor N9.

The gate and drain electrodes of transistor N9 are connected together to power supply potential vCC. transistor N9
The source of is connected to the collector of transistor Q4 and the emitter of transistor Q5. Transistor N9 connects the base of transistor Q4 and transistor Q5.
Q1 serves as a bleed resistor to keep the emitter of Q1 always charged, thereby reducing the amount of time it takes to turn on pulldown bipolar transistor Q1. Other than this difference, the component connections and circuit operation of FIG. 4 are identical to the circuit of FIG. 3. It should be understood by those skilled in the art that transistor N9 may be replaced by either a P-channel MOS transistor or a resistor.

In FIG. 5, a fourth embodiment of the output buffer circuit of FIG. 1, designated by reference numeral 410, is illustrated. As can be seen, the bipolar pull-down transistor Q1
Output buffer circuit 410 is substantially identical to the circuit of FIG. 4, except that it is formed with dual collectors. One collector of transistor Q1 is connected to output terminal 14, and the other collector of transistor Q1 is connected to the emitter of transistor Q3.

The circuit of FIG. 4 is such that during the time that the output voltage is in a low level state, a voltage drop is generated across its collector-emitter terminal by the sinking of current through the pull-down transistor Q1, whereby: The potential at the emitter of transistor Q3 is increased and the clamp current in transistor Q3 is decreased. This increases the base current in transistor Q1 which would cause saturation of transistor Q1. transistor Q
By supplying a double collector to output terminal 14
The effects of current sinking from transistor Q1 are reduced and a substantially constant low output voltage is maintained, yet transistor Q1
The current level in transistor Q3 is maintained to prevent saturation. Other than these differences, the component connections and circuit operation in FIG. 5 are identical to the circuit in FIG. 4.

In FIG. 6, another embodiment of the output buffer circuit of FIG. 2, designated by the reference numeral 510, is shown. It will be appreciated that buffer circuit 510 combines all of the circuit components of FIG. 2 with the additional improved features shown in FIG. In particular, the buffer circuit 510 is a voltage source (Q4
．． Q5), voltage divider (R1, R), bleed resistor (N
9) and the double collector transistor (Ql) of FIG. 5 are combined into the circuit of FIG. N-channel MOS transistor N8 has its drain connected to the base of bipolar transistor Q1 (rather than to the source of transistor N1 as in the second transistor).
, acts as an active pull-down transistor, reducing the conversion time to a high output impedance state at output terminal 14. Other than these differences, the component connections and circuit operation of FIG. 6 are identical to the circuit of FIG. 2.

From the foregoing detailed description, it will be seen that the present invention provides an output buffer circuit formed of merged bipolar and CMOS transistors to produce two output states or three output states. The combined bipolar/CMOS output buffer circuit of the present invention has high current drive capacity and low propagation delay.

While what is presently believed to be the preferred embodiment of this invention has been illustrated and described, various changes and modifications may be made and equivalents may be made without departing from the true scope of the invention. What can be replaced with that element is
It will be understood by those skilled in the art. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its central scope. Therefore, this invention is not limited to the particular embodiments disclosed as the best possible way to carry out the invention, but the invention encompasses all embodiments that come within the scope of the appended claims. intended to include.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram of a merged bipolar/CMO8 output buffer circuit with two output states formed in accordance with the principles of the present invention. FIG. 2 is a schematic circuit diagram of a merged bipolar/CMOS output buffer circuit of the present invention with three separate output states. FIG. 3 shows a second embodiment of the output buffer circuit of FIG. FIG. 4 shows a third embodiment of the output buffer circuit of FIG. FIG. 5 shows a fourth embodiment of the output buffer circuit of FIG. FIG. 6 shows another embodiment of the output buffer circuit of FIG. 2. In the figure, 10, 110, 210, 310°410'
, 510 is a bipolar/CMOS output buffer device, 1
2 is an input terminal, and 14 is an output terminal. Patent applicant: Advanced Micro Devices
Incorporated procedural amendment 1 February 19, 1988 Special rrWA No. 981 of 1988 2, Title of invention TTL compatible merged bipolar/CMO 8 output buffer circuit 3, Relationship with the person making the amendment Patent applicant address Thompson, Sunny Bay Pioneer Box 3453, California, United States.
Brace, 901 Name Advanced Micro Devices Incorporated Representative Thomas
Dabrid Armstrong 4, Agent address: 2-8-1 Hirano-cho, Higashi-ku, Osaka, Hirano-cho Yachiyo Building Voluntary amendment 6, Specification subject to amendment 1, Title of invention field 7, Invention of the statement of contents of the amendment In the name column, "rTTL compatible merged bipolar/CMO5 output buffer circuit" will be corrected to "rTTL compatible merged bipolar/CMO5 output buffer circuit."that's all

Claims (25)

[Claims] (1) A P-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply potential; whose collector is connected to the power supply potential and whose base is connected to the drain of the P-channel transistor; , a first bipolar transistor whose emitter is connected to the output terminal, a first N-channel MOS transistor whose gate is connected to the input terminal and whose drain is connected to the power supply potential, and whose collector is connected to the output terminal. , a second bipolar transistor whose base is connected via a resistor to the source of said first N-channel transistor and whose emitter is connected to ground potential, whose gate is connected to the drain of said P-channel transistor; a second N-channel MOS transistor, whose drain is connected to the source of said first N-channel transistor and whose source is connected to ground potential; and whose gate is connected to the input terminal and whose drain is connected to said P-channel transistor. a third N-channel MOS connected to the drain and whose source is connected to ground potential;
a transistor, its base connected to the source of said first N-channel transistor, its collector connected to the base of said second bipolar transistor, and its emitter connected to said second bipolar transistor;
and a third bipolar transistor connected to the collector of the bipolar transistor. (2) The output buffer circuit according to claim 1, wherein the first bipolar transistor is of NPN type conductivity. (3) The output buffer circuit according to claim 1, wherein the second bipolar transistor is of NPN type conductivity. (4) The output buffer circuit of claim 1, wherein the buffer circuit is formed on a single silicon chip of a monolithic integrated circuit. (5) A P-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply potential, and whose collector is connected to the power supply potential and whose base is connected to the drain of the P-channel transistor. a first bipolar transistor whose emitter is connected to the output terminal; an N-channel MOS transistor whose gate is connected to the input terminal and whose drain is connected to the power supply potential; and whose collector is connected to the output terminal. a second transistor, the base of which is connected to the source of the N-channel transistor through a resistor, and the emitter of which is connected to ground potential;
a bipolar transistor; first discharging means operatively connected to the base of the first bipolar transistor for quickly turning it off to speed up the low-to-high transition at the output terminal; a second discharge means operatively connected to the base for quickly turning it off to speed up the high-to-low transition at the output terminal; and connected between the base and collector of the second bipolar transistor; and anti-saturation means for preventing said second bipolar transistor from being forced further into the saturation region. (6) The output buffer circuit according to claim 5, wherein the first discharge means includes an N-channel MOS transistor. (7) The output buffer circuit according to claim 6, wherein the second discharge means includes an N-channel MOS transistor. (8) The output buffer circuit according to claim 7, wherein the anti-saturation means includes a third bipolar transistor. (9) The output buffer circuit according to claim 5, wherein the first bipolar transistor is of NPN type conductivity. (10) The output buffer circuit according to claim 5, wherein the second bipolar transistor is of NPN type conductivity. (11) The output buffer circuit according to claim 8, wherein the third bipolar transistor is of NPN type conductivity. (12) The output buffer circuit according to claim 5, wherein the buffer circuit is formed on a single silicon chip of a monolithic integrated circuit. (13) a first P-channel MOS transistor whose gate is connected to the first input terminal, whose collector is connected to the power supply potential, whose base is connected to the drain of the first P-channel transistor, and whose emitter is connected to the power supply potential; a first bipolar transistor connected to the output terminal, a first N-channel MOS transistor whose gate is connected to the first input terminal, whose collector is connected to the output terminal, and whose base is connected through a resistor. a second N-channel transistor connected to the source of the first N-channel transistor and having its emitter connected to ground potential;
a bipolar transistor whose gate is connected to the first P-
a second N-channel transistor connected to the drain of the first N-channel transistor, the drain of which is connected to the source of the first N-channel transistor, and the source of which is connected to ground potential;
- a third N-channel MOS transistor, whose gate is connected to the first input terminal, whose drain is connected to the drain of the first P-channel transistor and whose source is connected to ground potential; Its base is connected to the source of said first N-channel transistor, its collector is connected to the base of said second bipolar transistor, and its emitter is connected to said second bipolar transistor.
a third bipolar transistor connected to the collector of the bipolar transistor; its gate connected to the second input terminal; its source connected to the power supply potential; and its drain connected to the source of the first P-channel transistor. a second P-channel MOS transistor whose gate is connected to the second input terminal, whose source is connected to the power supply potential and whose drain is connected to the drain of the first N-channel transistor; a fourth N-channel MOS transistor, whose gate is connected to the second input terminal, whose drain is connected to the drain of the first P-channel transistor, and whose source is connected to ground potential; a fifth N-channel MOS transistor connected to the second input terminal, the drain of which is connected to the source of the first N-channel transistor, and the source of which is connected to ground potential; An output buffer circuit formed by a combined bipolar transistor and CMOS transistor that provides an output state. (14) The output buffer circuit according to claim 13, wherein the first bipolar transistor is of NPN type conductivity. (15) The output buffer circuit according to claim 13, wherein the second bipolar transistor is of NPN type conductivity. (16) The output buffer circuit of claim 13, wherein the buffer circuit is formed on a single silicon chip of a monolithic integrated circuit. (17) a P-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply potential; whose collector is connected to the power supply potential and whose base is connected to the drain of the P-channel transistor; a first bipolar transistor whose gate is connected to the input terminal and whose drain is connected to a power supply potential; and whose collector is connected to the output terminal. and its base is connected to the first
a second bipolar transistor connected to one end of the resistor and having its emitter connected to ground potential; its gate connected to the drain of said P-channel transistor and its drain connected to the base of said second bipolar transistor; a second N-channel MOS transistor, whose gate is connected to the input terminal, whose drain is connected to the drain of the P-channel transistor, and whose source is connected to ground potential; The third N-channel M
an OS transistor, and a third bipolar transistor whose base is connected to the other end of the first resistor, whose collector is connected to the base of the second bipolar transistor, and whose emitter is connected to the collector of the second bipolar transistor. a second resistor having one end connected to the source of the first N-channel transistor and the other end connected to the base of the third bipolar transistor; a second resistor connected to the source of the first N-channel transistor; An output buffer circuit formed of a merged bipolar transistor and a CMOS transistor to provide two output states compatible with TTL levels with a voltage source comprising: (18) The voltage source includes fourth and fifth bipolar transistors, the collector and base of the fourth transistor are connected together to the emitter of the fifth transistor, and the emitter of the fourth transistor is at ground potential. 18. The output buffer circuit of claim 17, wherein the collector and base of the fifth transistor are connected together to the source of the first N-channel transistor. (19) The claim further comprises a bleed resistor formed by a fourth N-channel MOS transistor whose drain and gate are connected together to a power supply potential and whose source is connected to the emitter of the fifth transistor. The output buffer circuit according to range 18. (20) a P-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply potential; whose collector is connected to the power supply potential and whose base is connected to the drain of the P-channel transistor; a first bipolar transistor whose emitter is connected to the output terminal; a first N-channel MOS transistor whose gate is connected to the input terminal and whose drain is connected to a power supply potential; a second bipolar transistor connected to the output terminal, the base of which is connected to one end of the first resistor, the emitter of which is connected to ground potential; the gate of which is connected to the drain of the P-channel transistor; a second N-channel MOS transistor whose drain is connected to the base of the second bipolar transistor and whose source is connected to ground potential; and whose gate is connected to the input terminal and whose drain is connected to the drain of the P-channel transistor. a third N-channel M, whose source is connected to ground potential;
a third OS transistor, the base of which is connected to the other end of the first transistor, the collector of which is connected to the base of the second bipolar transistor, and the emitter of which is connected to the second collector of the second bipolar transistor; a bipolar transistor; a second resistor having one end connected to the source of the first N-channel transistor and the other end connected to the base of the third bipolar transistor; and a second resistor connected to the source of the first N-channel transistor. An output buffer circuit formed of a merged bipolar transistor and a CMOS transistor to provide two output states compatible with TTL levels with a voltage source and a voltage source. (21) The voltage source includes fourth and fifth bipolar transistors, the collector and base of the fourth transistor are connected together to the emitter of the fifth transistor, and the emitter of the fourth transistor is connected to ground potential. 21. The output buffer circuit of claim 20, wherein the collector and base of the fifth transistor are connected together to the source of the first N-channel transistor. (22) The claim further comprises a bleed resistor formed by a fourth N-channel MOS transistor whose drain and gate are connected together to a power supply potential and whose source is connected to the emitter of the fifth transistor. The output buffer circuit according to range 21. (23) The first P whose gate is connected to the first input terminal
- a channel MOS transistor and a first bipolar transistor whose collector is connected to the power supply potential, whose base is connected to the drain of said first P-channel transistor and whose emitter is connected to the output terminal; a first N-channel MOS transistor connected to the first input terminal, its first collector connected to the output terminal, its base connected to one end of the first resistor, and its emitter connected to ground potential; a second bipolar transistor; and a second N-channel MOS, the gate of which is connected to the drain of the first P-channel transistor, the drain of which is connected to the base of the second bipolar transistor, and the source of which is connected to ground potential. a third N-channel MOS transistor, the gate of which is connected to the first input terminal, the drain of which is connected to the drain of the first P-channel transistor, and the source of which is connected to ground potential; a third bipolar transistor connected to the other end of the first resistor, whose collector is connected to the base of the second bipolar transistor, and whose emitter is connected to the second collector of the second bipolar transistor; a second resistor connected to the source of the first N-channel transistor and its other end connected to the base of the third bipolar transistor; its gate connected to the second input terminal and its source connected to the power supply potential; a second P-channel MOS transistor, whose drain is connected to the source of the first P-channel transistor; whose gate is connected to the second input terminal, whose source is connected to the power supply potential; a third P-channel MOS transistor whose gate is connected to the drain of the first N-channel transistor, whose gate is connected to the second input terminal, whose drain is connected to the drain of the first P-channel transistor, and whose source is connected to the drain of the first P-channel transistor; a fourth N-channel MOS transistor whose gate is connected to the second input terminal and whose drain is connected to the base of the second bipolar transistor;
a fifth N-channel MOS transistor whose source is connected to ground potential; and a voltage source connected to the source of the first N-channel transistor.
An output buffer circuit formed by a combined bipolar transistor and a CMOS transistor that provides three output states compatible with the L level. (24) the voltage source includes fourth and fifth bipolar transistors, the collector and base of the fourth transistor are coupled together and connected to the emitter of the fifth transistor, and the emitter of the fourth transistor is connected to ground potential; 24. The output buffer circuit of claim 23, wherein the collector and base of the fifth transistor are connected together to the source of the first N-channel transistor. (25) The claim further comprises a bleed resistor formed by a sixth N-channel MOS transistor whose drain and gate are connected together to a power supply potential and whose source is connected to the emitter of the fifth transistor. The output buffer circuit according to range 24.