KR940007954B1 - Bicmos driving circuit - Google Patents

Bicmos driving circuit Download PDF

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Publication number
KR940007954B1
KR940007954B1 KR1019920003728A KR920003728A KR940007954B1 KR 940007954 B1 KR940007954 B1 KR 940007954B1 KR 1019920003728 A KR1019920003728 A KR 1019920003728A KR 920003728 A KR920003728 A KR 920003728A KR 940007954 B1 KR940007954 B1 KR 940007954B1
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South Korea
Prior art keywords
logic means
driving circuit
bicmos
speed
cmos
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KR1019920003728A
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Korean (ko)
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KR930020845A (en
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정기호
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삼성전자 주식회사
김광호
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Priority to KR1019920003728A priority Critical patent/KR940007954B1/en
Priority to ITMI921070A priority patent/IT1255305B/en
Priority to JP4144799A priority patent/JPH09167956A/en
Priority to DE4215649A priority patent/DE4215649A1/en
Priority to FR9206228A priority patent/FR2688362A1/en
Priority to GB9210937A priority patent/GB2264832B/en
Publication of KR930020845A publication Critical patent/KR930020845A/en
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Publication of KR940007954B1 publication Critical patent/KR940007954B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Abstract

The circuit speeds up the operation spped by reduction of discharging time constant. The circuit includes a CMOS logical means (31) which converts input signal into logical level signal, a high current driving means (33) which drives a bipolar device, and a speed development logical means (32) which speeds up the discharging speed of driving means (31). The logical means (31) has two CMOS inverters. The speed development logical means (33) has a CMOS inverter, and has CMOS inverters (M1,M2),(M3,M4),(M6).

Description

BiCMOS 구동회로BiCMOS driving circuit

제 1 도는 일반적인 BiCMOS 구동회로의 블럭도이다.1 is a block diagram of a general BiCMOS driving circuit.

제 2 도는 상기 제 1 도의 블럭도 내부의 구체적인 BiCMOS 구동회로도이다.FIG. 2 is a specific BiCMOS driving circuit diagram in the block diagram of FIG.

제 3 도는 본 발명에 의한 BiCMOS 구동회로도의 블럭도이다.3 is a block diagram of a BiCMOS driving circuit diagram according to the present invention.

제4a도 및 제4b도는 상기 제 1 도의 블록도를 구체화한 본 발명에 의한 BiCMOS 구동회로의 바람직한 일 실시예들이다.4A and 4B are exemplary embodiments of a BiCMOS driving circuit according to the present invention incorporating the block diagram of FIG.

본 발명은 반도체장치의 구동회로에 관한 것으로, 특히 적은 전력소모 및 고속 동작이 실현되도록 BiCMOS를 사용하여 구성한 구동회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a semiconductor device, and more particularly to a driving circuit configured using BiCMOS to realize low power consumption and high speed operation.

일반적으로 아날로그(analog) 기능과 디지탈(digital) 기능으로 구성되는 대규모 집적회로에서는 상기 아날로그 기능과 디지탈 기능을 모두 구현하기 위해서는 I2L(Integrated Injection Logic) 공정이나 CMOS(Complementary Metal Oxide Semicondutor) 공정이 이용되고 있다. L2L 소자로 디지탈 기능을 구현할 경우에는 출력단의 출력 스윙 레벨에 한계가 있으며, CMOS 소자로 증폭단의 큰 이득을 얻기 위해서는 MOS 트랜지스터의 크기를 크게해야 하므로 칩(chip) 사이즈가 증가하는 등의 문제점이 있다.In general, in a large-scale integrated circuit composed of an analog function and a digital function, an I 2 L (Integrated Injection Logic) process or a Complementary Metal Oxide Semicondutor (CMOS) process is used to implement both the analog function and the digital function. It is used. When implementing digital functions with L 2 L devices, the output swing level of the output stage is limited, and in order to obtain large gains of the amplifier stage with CMOS devices, the size of the MOS transistor needs to be increased, resulting in an increase in chip size. There is this.

이와 같은 문제로 인해 대규모 집적회로는 아날로그 및 디지탈 기능이 혼재된 BiCMOS 회로로 발전되고 있다.Due to these problems, large-scale integrated circuits are being developed as BiCMOS circuits with mixed analog and digital functions.

일반적으로 구동회로는 CMOS 소자를 이용한 것과 바이폴라 소자를 이용한 것으로 크게 구분할 수 있으나, 아날로그 및 디지탈 기능을 모두 갖춘 집적회로에서는 종래 회로 구성의 방법을 적용하기에는 어려움이 있다.Generally, the driving circuit can be largely classified into using a CMOS device and using a bipolar device. However, in an integrated circuit having both analog and digital functions, it is difficult to apply a conventional circuit configuration method.

이하, 첨부 도면 제 1 도 및 제 2 도를 참조하여 일반적인 BiCMOS 구동회로를 살펴본다.Hereinafter, a general BiCMOS driving circuit will be described with reference to FIGS. 1 and 2.

제 1 도는 일반적인 BiCMOS 구동회로의 블럭도로서 3개의 기능을 수행하는 블럭과 상기 블럭들의 연결형태로 구성된다. 즉, 입력단자(a)에 연결된 논리수단(11), 반전전압 보상수단(12), 출력단자(e)에 연결된 구동수단(13)으로 구성되며, 상기 수단은 각각의 내부 경로(b, c, d)를 통해 연결되어 있다.FIG. 1 is a block diagram of a general BiCMOS driving circuit and includes a block performing three functions and a connection form of the blocks. That is, it consists of a logic means 11 connected to the input terminal (a), an inversion voltage compensation means (12), and a drive means (13) connected to the output terminal (e). , via d).

일반적인 상기한 BiCMOS 구동회로의 블럭도를 구체적인 회로도로 구현한 제 2 도를 참조하여 회로동작을 살펴보면, 입력단자(a)에 입력된 신호전압레벨이 "하이"레벨일 때, 경로(c)는 "로우"레벨이고, 경로(b)는 "하이"레벨이 된다. 따라서 트랜지스터 Q3과 Q2는 "온(on)"상태가 되어 출력단자(e)의 전압레벨은 VCC-(VBE1+VBE2)로서 "하이"레벨이 된다. 한편, 입력단자(a)에 입력된 신호가 "로우"레벨이면 경로(c)는 "하이"레벨이 되고 경로(b)는 "로우"가 되어 트랜지스터 Q1과 Q2는 "오프(off)"상태가 되고 Q3과 Q4는 "온"상태가 되어 출력단자(e)의 전압 레벨은 VBE4+VCE3sat.로서 "로우"레벨이 된다.Referring to FIG. 2, which is a block diagram of a general BiCMOS driving circuit, a circuit diagram is described with reference to FIG. 2. When the signal voltage level input to the input terminal a is at a "high" level, the path c is It is at the "low" level, and the path b is at the "high" level. Therefore, the transistors Q3 and Q2 are turned "on", and the voltage level of the output terminal e becomes "high" level as V CC- (V BE1 + V BE2 ). On the other hand, if the signal input to the input terminal a is at the "low" level, the path c is at the "high" level, the path b is at the "low", and the transistors Q1 and Q2 are in the "off" state. Q3 and Q4 are turned "on" and the voltage level of the output terminal (e) becomes "low" level as V BE4 + V CE3 sat.

이때, 저항 R1은 트랜지스터 Q3와 Q4의 VBE(VBE3, VBE4) 값에 의해 MOS 소자인 M3과 M4로 구성된 인버터가 동작불안을 일으키지 않도록 전류를 제한하는 반전전압 보상수단의 역할을 한다.At this time, the resistor R1 serves as an inversion voltage compensation means for limiting the current so that the inverter composed of the MOS devices M3 and M4 does not cause operation instability by the V BE (V BE3 , V BE4 ) values of the transistors Q3 and Q4.

이와 같이 일반적인 BiCMOS 구동회로에서는 논리수단(11)과 구동수단(13) 사이에 반전전압 보상수단(12)으로서 저항(R1)이 이용되고 있다. 그러나 반도체 제조공정을 통해 웨이퍼 상에 집적회로를 형성할 경우, 저항 R1은 웨이퍼의 단위당 면적을 많이 차지할 뿐 아니라, 트랜지스터 Q3의 베이스-에미터 간 방전패스(pass)가 저항 R1과 MOS 소자 M2로 구성되어 있어, 방전 시상수가 크므로 회로의 고속동작을 구현하는데 문제점이 있다.In this general BiCMOS driving circuit, a resistor R1 is used as the inverting voltage compensating means 12 between the logic means 11 and the driving means 13. However, when the integrated circuit is formed on the wafer through the semiconductor manufacturing process, the resistor R1 occupies a large area per unit of the wafer, and the discharge pass between the base-emitter of the transistor Q3 is transferred to the resistor R1 and the MOS device M2. Since the discharge time constant is large, there is a problem in implementing the high speed operation of the circuit.

따라서, 본 발명의 목적은 반전전압 보상수단으로 CMOS 인버터를 이용함으로써 동작 속도가 뛰어난 BiCMOS 구동회로를 제공하는데 있다.Accordingly, an object of the present invention is to provide a BiCMOS driving circuit having excellent operation speed by using a CMOS inverter as the inversion voltage compensation means.

또, 본 발명의 다른 목적은 반전전압 보상수단으로 저항보다 집적도가 작은 CMOS 인버터를 이용함으로써 칩 사이즈를 줄일 수 있는 BiCMOS 구동회로를 제공하는데 있다.Another object of the present invention is to provide a BiCMOS driving circuit which can reduce the chip size by using a CMOS inverter having a smaller degree of integration than a resistor as an inversion voltage compensating means.

이와 같은 목적을 달성하기 위하여 본 발명은 입력신호를 논리레벨로 변환시키는 논리수단 ; 상기의 논리레벨을 바이폴라 소자를 사용하여 고속으로 동작시키는 대전류 구동수단 ; 논리수단과 구동수단 사이에 개재되어 구동수단의 방전속도를 빠르게 하는 속도개선 논리수단을 구비하여 구성되는 것을 특징으로 하는 BiCMOS 구동회로를 제공한다.In order to achieve the above object, the present invention provides a logic means for converting an input signal into a logic level; High current driving means for operating the logic level at a high speed by using a bipolar element; Provided is a BiCMOS driving circuit comprising a speed improving logic means interposed between the logic means and the driving means to speed up the discharge speed of the driving means.

이하, 첨부한 도면 제 3 도 및 제 4 도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 3 and 4.

제 3 도는 본 발명의 BiCMOS 구동회로의 블럭도로서 3개의 기능을 수행하는 블럭과 상기 블럭들의 연결형태로 구성되어 있다. 즉 입력단자(a)에 연결되어 두개의 CMOS 인버터로 구성되는 논리수단(31), 한개의 CMOS 인버터로 구성한 속도개선 논리수단(32) 및 출력단자(d)에 연결되어 3개의 바이폴라 트랜지스터 및 3개의 부하소자로 구성된 구동수단(33)을 구비하고, 상기 각 수단은 내부경로(b, c)를 통해 내부적으로 상호 연결되어 있다. 즉, 신호처리를 거친 신호가 입력단자(a)로 입력되어 논리수단(31)을 거쳐 논리레벨의 신호로 바뀌어 경로(b)로 출력되며, 경로(b)로 출력된 논리레벨의 신호는 속도개선 논리수단(32)과 구동수단(33)에 각각 입력된다. 즉, 속도개선 논리수단(32)을 이루는 CMOS 소자(M5, M6)의 게이트 공통 전극선에 입력된 입력신호는 상기 CMOS 인버터를 통과하여 그 출력신호가 내부경로(c)를 통해 구동수단(33)에 입력된다. 여기서 상기 속도개선 논리수단(32)은 구동수단(33)의 방전을 빠르게 하여 구동수단(33)의 동작속도를 높이는 기능을 한다. 논리수단(31)과 속도개선 논리수단(32)에서 입력된 신호는 구동수단(33)을 통해 출력수단(d)에서 출력전압으로 나타난다.3 is a block diagram of a BiCMOS driving circuit of the present invention, which is composed of a block performing three functions and a connection form of the blocks. That is, the logic means 31 connected to the input terminal a and composed of two CMOS inverters, the speed improving logic means 32 composed of one CMOS inverter, and the output terminal d are connected to three bipolar transistors and three. Driving means 33 comprising four load elements, each of which is internally interconnected via internal paths b and c. That is, the signal processed through the signal is input to the input terminal (a) through the logic means 31 is converted into a signal of the logic level is output to the path (b), the signal of the logic level output to the path (b) is a speed It is input to the improvement logic means 32 and the drive means 33, respectively. That is, the input signal inputted to the gate common electrode line of the CMOS elements M5 and M6 constituting the speed improving logic means 32 passes through the CMOS inverter, and the output signal is driven through the internal path c. Is entered. The speed improving logic means 32 serves to increase the operating speed of the driving means 33 by speeding up the discharge of the driving means 33. The signals input from the logic means 31 and the speed improvement logic means 32 appear as output voltages from the output means d via the drive means 33.

상기한 본 발명을 구성하는 구체적인 BiCMOS 구동회로도인 제4a도를 참조하여 그 회로 동작을 살펴보면, 입력단자(a)에 입력된 신호 전압레벨이 "하이"레벨일 때 경로(b)는 "하이"레벨이고, 경로(c)는 "로우"레벨이 된다. 따라서 트랜지스터 Q1과 Q2은 "온"상태가 되고, Q3와 Q4은 "오프"상태가 되어 출력단자(d) 전압은 VCC-VBE1+VBE2)가 되어 "하이"레벨이 된다. 한편, 입력단자(a)에 입력된 신호전압 레벨이 "로우"레벨이면 경로(b)는 "로우"레벨이고, 경로(c)는 VBE3+VBE4가 되어 트랜지스터의 Q1과 Q2은 "오프"상태가 되고, Q3와 Q4는 "온"상태로 되어 출력단자(d)에는 VBE4+VBE3sat. 전압이 나타나 "로우"레벨이 된다.Referring to FIG. 4A, which is a specific BiCMOS driving circuit diagram constituting the present invention, the circuit operation is performed. When the signal voltage level input to the input terminal a is at the "high" level, the path b is "high". Level, path c is at the "low" level. Therefore, the transistors Q1 and Q2 are in the "on" state, the Q3 and Q4 are in the "off" state, and the output terminal (d) voltage is V CC -V BE1 + V BE2 ) to become the "high" level. On the other hand, if the signal voltage level input to the input terminal a is at the "low" level, the path b is at the "low" level, and the path c is at V BE3 + V BE4 so that the transistors Q1 and Q2 are "off". "Q" and Q4 are "on" and the output terminal (d) has V BE4 + V BE3 sat. The voltage appears and goes to the "low" level.

또한, 본 발명의 다른 실시예인 제4b도에서는 속도개선 논리수단(32)의 입력선을 M1과 M2로 구성된 CMOS 논리수단(31)의 입력단에 공통으로 접속하여도 제4a도의 실시예에서와 같은 동일한 논리레벨의 신호가 속도개선 논리수단(32)으로 입력되므로 동일한 회로동작 및 효과를 얻을 수 있다. 즉 입력단자(a)로 입력되는 신호는 동시에 속도개선 논리수단(31)인 CMOS 인버터(M5, M6)의 입력단에도 입력된다.In addition, in FIG. 4B, which is another embodiment of the present invention, the input line of the speed improving logic means 32 is commonly connected to the input terminal of the CMOS logic means 31 composed of M1 and M2, as in the embodiment of FIG. 4A. Since the signal of the same logic level is input to the speed improvement logic means 32, the same circuit operation and effect can be obtained. In other words, the signal input to the input terminal a is simultaneously input to the input terminals of the CMOS inverters M5 and M6, which are speed improvement logic means 31, respectively.

속도개선 논리수단(32)에 CMOS 인버터를 사용함으로써 칩 면적을 많이 차지하던 종래의 저항을 대신할 수 있어 반도체장치의 고집적도에 매우 유리한 장점이 있으며, 트랜지스터 Q3의 방전패스가 n-MOS 소자인 M6로 이루어지므로 방전시상수가 작아지고, 결과적으로 방전속도가 빨라지게 되어 회로 동작 속도를 훨씬 빠르게 개선시키는 효과를 얻을 수 있는 이점이 있다.By using a CMOS inverter in the speed improvement logic means 32, it is possible to replace the conventional resistor, which occupies a large area of the chip, which is very advantageous for the high integration of the semiconductor device. Since it is made of M6, the discharge time constant is small, and as a result, the discharge speed is increased, which has the advantage of improving the circuit operation speed much faster.

Claims (7)

입력신호는 논리레벨로 변환시키는 논리수단 ; 바이폴라 소자를 사용하여 고속으로 동작시키는 대전류 구동수단 ; 논리수단과 구동수단 사이에 개재되어 구동수단의 방전속도를 빠르게 하는 속도개선 논리수단을 구비하여 구성되는 것을 특징으로 하는 BiCMOS 구동회로.Logic means for converting the input signal to a logic level; High current driving means for operating at high speed by using a bipolar element; And a speed improving logic means interposed between the logic means and the driving means to speed up the discharge rate of the driving means. 제 1 항에 있어서, 상기 논리수단은 두 개의 CMOS 인버터를 직렬로 연결하여 구성된 것을 특징으로 하는 BiCMOS 구동회로.The BiCMOS driving circuit according to claim 1, wherein the logic means is formed by connecting two CMOS inverters in series. 제 1 항에 있어서, 상기 속도개선 논리수단은 논리적 반전기능을 갖는 회로로 구성된 것을 특징으로 하는 BiCMOS 구동회로.2. The BiCMOS driving circuit according to claim 1, wherein the speed improving logic means is composed of a circuit having a logical inversion function. 제 3 항에 있어서, 상기 속도개선 논리수단은 1개의 CMOS 인버터로 구성된 것을 특징으로 하는 BiCMOS 구동회로.4. The BiCMOS driving circuit according to claim 3, wherein the speed improving logic means comprises one CMOS inverter. 제 1 항, 제 2 항 및 제 4 항 중 어느 한 항에 있어서, 속도개선 논리수단의 CMOS 인버터 입력선이 논리수단의 전단 CMOS 인버터(M1, M2)의 입력단과 공통접속된 것을 특징으로 하는 BiCMOS 구동회로.A BiCMOS according to any one of claims 1, 2 and 4, characterized in that the CMOS inverter input line of the speed improving logic means is connected in common with the input terminals of the front end CMOS inverters M1 and M2 of the logic means. Driving circuit. 제 1 항, 제 2 항 및 제 4 항 중 어느 한 항에 있어서, 속도개선 논리수단의 CMOS 인버터 입력선이 논리수단의 후단 CMOS 인버터(M3, M4)의 출력단과 공통접속된 것을 특징으로 하는 BiCMOS 구동회로.A BiCMOS according to any one of claims 1, 2 and 4, characterized in that the CMOS inverter input line of the speed improving logic means is connected in common with the output terminals of the CMOS inverters M3 and M4 after the logic means. Driving circuit. 제 1 항 및 제 3 항 중 어느 한 항에 있어서, 상기 속도개선 논리수단의 CMOS 인버터에 구비된 n-MOS 소자(M6)를 구동수단을 구성하는 바이폴라 트랜지스터(Q3)의 방전패스로 이용하는 것을 특징으로 하는 BiCMOS 구동회로.4. The method according to any one of claims 1 and 3, wherein the n-MOS element M6 provided in the CMOS inverter of the speed improvement logic means is used as a discharge path of the bipolar transistor Q3 constituting the driving means. BiCMOS driving circuit.
KR1019920003728A 1992-03-06 1992-03-06 Bicmos driving circuit KR940007954B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019920003728A KR940007954B1 (en) 1992-03-06 1992-03-06 Bicmos driving circuit
ITMI921070A IT1255305B (en) 1992-03-06 1992-05-05 BICMOS CONTROL CIRCUIT
JP4144799A JPH09167956A (en) 1992-03-06 1992-05-11 Bi cmos driving circuit
DE4215649A DE4215649A1 (en) 1992-03-06 1992-05-13 BICMOS DRIVER CIRCUIT
FR9206228A FR2688362A1 (en) 1992-03-06 1992-05-21 BiCMOS drive circuit
GB9210937A GB2264832B (en) 1992-03-06 1992-05-22 Bicmos driving circuit

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KR940007954B1 true KR940007954B1 (en) 1994-08-29

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KR900000830B1 (en) * 1984-06-25 1990-02-17 후지쑤 가부시끼가이샤 Complementary bi-mis gate circuit
JPS61224519A (en) * 1985-03-28 1986-10-06 Toshiba Corp Logic circuit
US4678940A (en) * 1986-01-08 1987-07-07 Advanced Micro Devices, Inc. TTL compatible merged bipolar/CMOS output buffer circuits
JP2696991B2 (en) * 1988-09-26 1998-01-14 日本電気株式会社 BiCMOS logic circuit
JPH02182022A (en) * 1989-01-09 1990-07-16 Fujitsu Ltd Output buffer circuit
JPH02237220A (en) * 1989-03-09 1990-09-19 Fujitsu Ltd Output circuit
JPH02243015A (en) * 1989-03-15 1990-09-27 Nec Corp Control circuit
JPH03156967A (en) * 1989-11-15 1991-07-04 Toshiba Micro Electron Kk Output circuit
US5038058A (en) * 1990-11-06 1991-08-06 Motorola, Inc. BiCMOS TTL output driver

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DE4215649A1 (en) 1993-09-09
GB2264832A (en) 1993-09-08
GB9210937D0 (en) 1992-07-08
FR2688362A1 (en) 1993-09-10
KR930020845A (en) 1993-10-20
ITMI921070A1 (en) 1993-11-05
ITMI921070A0 (en) 1992-05-05
GB2264832B (en) 1995-10-18
IT1255305B (en) 1995-10-31
JPH09167956A (en) 1997-06-24

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