JPH02182022A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To quicken the change in a logic level of an output signal with respect to a change in a logic level of an input signal by increasing the quantity of a base current of a bipolar transistor(TR) being an output stage TR in the dynamic state more than that in a static state. CONSTITUTION:A base current control circuit 12 is provided with an output buffer circuit having an output stage TR 11. The base current control circuit 12 detects the level of the input signal of the output stage TR 11 and the level of the output signal and a base current of a bipolar. TR X1 is increased only when the logic level of the output signal is changed in response to the change in the logic level of the input signal. Thus, the logic level of the output signal of the output stage TR 11 is rapidly changed. On the other hand, when the logic level of the input signal of the output stage TR 11 is not changed, the base current control circuit 12 reduce the steady-state base current without increasing the base current of the bipolar TR X1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an output back 7 circuit, and in particular to a T
The present invention relates to an output puff 7 circuit that outputs a TL level.

As integrated circuits (ICs) have become faster and more highly integrated in recent years,
There is a demand for faster internal circuits of tC. On the other hand, the output stage transistor of the internal gate is B t −0M
By switching to O3, we aim to increase the speed. On the other hand, Dekabatatsuno? If an attempt is made to increase the speed, the steady current increases and the power consumption increases, so low-cost power from the output buffer 7 is required.

[Conventional technology]

FIG. 5 shows a circuit diagram of an example of a conventional output battery 1 circuit. In the figure, 15 is an input terminal, for example 0MO8 (Ll
A binary signal at the MOS level is input. On the other hand, 16 is an output terminal which outputs a binary signal of TT level.

Pl and N1 are a P-channel MO8 field effect transistor and an N-channel MO8 field effect transistor whose gates and drains are connected, respectively, and constitute a first CMOS inverter. Similarly, P channel MO8! S! The W field effect transistor P2 and the N channel MOS field effect transistor N2 form the second CMO.
A P-channel MO8 field effect transistor P3 and an N-channel MOS field effect transistor N3 constitute a third CMOS inverter.

The first to third CMOS inverters described above are connected in cascade, and the output terminal of the second CMOS inverter is connected to the base of the Schottky clamped NPN transistor Q1 and the cathode of the Schottky barrier diode SBD+, respectively. , the output end of the third CMOS inverter is a Schottky clamped NPl'1 transistor Q3.
connected to the base of.

The emitter of transistor Q1 and the anode of diode SBD+ are each connected to the base of NPN transistor Q2. Transistors QI and Q2 are Darlington connected, and a resistor R provided on their collector side
1 is a current limiting resistor that defines the high level of the output signal. Further, the diode SBD+ is used to extract the base charge of the transistor Q2. The emitter of transistor Q2 and the collector of transistor Q3 are each connected to output terminal 16.

Since the input signal waveform input to the input terminal 15 is normally distorted, the output buffer 7 circuit having such a configuration shapes the waveform and reduces the load of a large amount external to the IC to T.
It is provided for driving at TL level.

The CMOS level input to the input terminal 15 (i.e.
The input signal (high level is +5V, low level is OV) is supplied to the base of the transistor QI through the first and second CMOS inverters described above.Meanwhile, the phase is inverted by the third CMOS inverter described above. and is supplied to the base of transistor Q3.

Therefore, when the input signal is at a high level, the base potential of the transistor Q1 becomes a high level, so the Darlington-connected transistors Q1 and Q2 are turned on, and -7'l, the base potential of the transistor Q3 becomes a low level. Therefore, transistor Q3 is turned off. As a result, a high-level signal of 1.3 V or higher at the TrL level is outputted to the output terminal 16.

On the other hand, when the input signal is at the [1- level, the base potential of the transistor Q+ is at the low level, so the transistors Q+ and Q2 are respectively turned off. At this time, the base ff1f'il of the transistor Q2 is connected to the diode SBD+
is instantly discharged through the Further, since the base potential of the transistor Q3 becomes high level, the transistor Q3 is turned on. 5. Therefore, when the input signal is at a low level, a signal at a low level (approximately OV here) at a TrL level, which is less than 1.3V, is taken out from the output 1''F16.

In such an output variation circuit, a Darlington connection configuration of bipolar transistors Q+ and Q2 is used to speed up the rise of the output signal from a low level to a high level, and a Darlington connection configuration of bipolar transistors Q+ and Q2 is used to speed up the rise of the output signal from a low level to a high level. In order to speed up the fall of , a B i-0MO3 configuration is used in which the base of transistor Q3, which is a bipolar transistor, is connected to the output terminal of a third CMOS inverter made up of transistors P3 and N3, and
The size of transistor P3 is increased to increase the base current of transistor Q3.

[Problem to be solved by the invention]

However, in the above-mentioned conventional output buffing circuit, the base current of transistor Q3 is constant, so while the fall of the above-mentioned output signal is fast, even in a steady state where the output signal remains at a low level, A large base current continues to flow through the - transistor Q3, resulting in a problem of large power consumption.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an output buffer circuit that reduces steady power consumption and also achieves high speed.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 11 is an output stage transistor, and the base of a bipolar transistor x 1 is connected to the output terminal of the field effect transistor.
It has a t-crv+os configuration. In the output buffer circuit forming such an output stage transistor 11, a base current control circuit 12 is provided in the present invention.

The base current control circuit 12 detects the levels of the input signal and output signal of the output stage transistor 11, and the base current of the bipolar transistor 1゜[Operation] The base current tlJ It1 circuit 12 only when the logic level of the input signal of the output stage transistor 11 changes,
Since the control is performed to increase the base N current of the bipolar transistor X1, the logic level of the output signal of the output stage transistor 11 changes rapidly.

On the other hand, when the logic level of the input signal to the output stage transistor 11 does not change, the base current control circuit 12 reduces the steady base current without increasing the base current of the bipolar transistor x1.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention, in which:
Components that are the same as those in FIGS. 1 and 5 are designated by the same reference numerals.
9. In FIG. 2, the explanation thereof will be omitted. In FIG. 2, the Schottky clamped NPN transistor Q3 corresponds to the bipolar transistor X1. Further, N4 and N5 are N-channel MO8 type field effect transistors, and the source of the transistor N4 and the drain of the transistor N5 are respectively connected. Furthermore, the gate of the transistor N4 is connected to the common connection point of the gates of the transistors P2 and N2, and the drain is connected to the +5V power supply terminal. On the other hand, the gate of the transistor Ns is connected to the common connection point (0 point) of the emitter of the transistor Q2, the collector of the transistor Q3, and the output terminal 16 via the resistor R2.

If the 0 point of the above resistor R2 is connected directly to the gate of the transistor Ns, there is a risk that the transistor N5 will be destroyed by static electricity.
Although it is a resistance, it is not necessarily necessary in principle.

Further, Q4 is an NPN transistor whose base is connected to the source of the transistor N5, and the transistor P
Its emitters are connected to both the drains of I' and N3 and the base of the transistor Q3, respectively, and its collector is connected to the +5■ power supply terminal.

The transistors N4, Ns and Q4 and the resistor R2 constitute the base current control circuit 12 described above.

The output buffing circuit of this embodiment operates as shown in the following table.

In the above table, "ON" in the operation of the base current control circuit 12 indicates that the operation to increase the base current is performed, and "OFF 1" indicates that the operation to increase the base current is not performed. Also, is it the output buffer that causes the output signal to lag behind the input signal? This is because there is a delay in itself. Further, states (1) to 6) mean that the input signal and the output signal are in each state as shown in FIG.

Next, the operation of this embodiment will be explained according to the above-mentioned operation clothes.

Width state In this state, both the input signal and the output signal are at low level, as shown in FIG.

In this case, since the input signal is at low level, the potential at the point becomes high level, and transistor N4 is turned on. On the other hand, since the output signal is at a low level, the transistor N5 is turned off. Therefore, a current is supplied to the transistor Q4, and the transistor Q4 is turned off, so that the base current i11 control circuit 121 is turned off. Therefore, the base current of transistor Q3 is:
It is supplied only from transistor P3'.

State (2) In this state, the input signal changes from low level to high level as shown in Figure 6, but the output buffer? Due to its own delay, the output signal level has not yet changed and remains at a low level. In this case, since the input signal changes from low level to high level, the potential at the 0 point changes from high level to O- level. Therefore, transistor N4 is turned off. Further, since the transistor N5 is in the same state as in (1), it is turned off, and the base current control circuit 12 is also turned off.

State a In this state, as shown in FIG. 6, the output signal changes with a delay with respect to the change in the input signal. In this case, since the input signal is at a high level, the potential at the point becomes 0-level, and the transistor N4 is turned off.

On the other hand, since the output signal changes from low level to high level, transistor N5 is turned on. Therefore, the base current of the transistor Q4 is not supplied, and the base current control circuit 12 is turned off.

State (4) In this state, both the input and output signals are as shown in Figure 6.
This is when the condition (■) becomes stable while the condition is at a high level. In this case, the base current control circuit 12 is also turned off as in the state (2).

Condition (2) In this state, as shown in Figure 6, the input signal has changed from high level to low level, but due to the delay of the output buffer itself, the output signal level has not changed yet and remains at high level. It's time. In this case, since the input signal changes from high level to low level, the potential at the 0 point also changes from low level to high level. Therefore, transistor N4 is turned on. On the other hand, since the output signal remains at a high level, the l transistor N5 is also turned on, the base current of the transistor Q4 is supplied, and the transistor 04 is turned on. That is, base current 1
The operation of the iIJtl11 circuit 12 becomes A-on1. As a result, a current is supplied to the base of the transistor Q3 through the emitter of the transistor Q4, and a current larger than the steady base current is supplied by the amount of current, and the transistor Q3 becomes , turns on rapidly.

6) State This state is a continuation of state ① as shown in Fig. 6, and is a state in which the output (n) changes after a delay in response to changes in the input signal.In this case, the input signal changes. Since the signal is low level, the potential at the point becomes high level, and the transistor N
4 is turned on. On the other hand, since the output signal changes from high level to low level, the output signal changes from transistor N4
Until the threshold level of
4 is on, and anything below that is off. Therefore, until the output signal reaches the threshold level of the transistor N4, the base current control circuit 12 is in the same state as in (2) and is turned on. When the output signal becomes below the threshold level of the transistor N4, the base current control circuit 12 1
2 becomes the same state as (1) and turns off.

As described above, according to the present embodiment, only when the input signal changes from high level to low level and the output signal remains high level, the base current of transistor Q3 is increased to rapidly turn on the transistor Q3. Therefore, the time from the time when the logic level of the input signal changes to the time when the output signal changes from high level to low level can be made shorter than before. Moreover, in the steady state when the transistor Q3 is on, the base current control circuit 12 is off, so the current flowing through the transistor Q3 can be reduced compared to when the output signal falls. Therefore, power consumption can be reduced.

FIG. 3 shows actual measured values of input signals and output signals of the embodiment circuit shown in FIG. 2. Figure 3 (A) shows the change in the output signal when the input signal changes from high level to low level, and Figure 3 (B) shows the output signal when the input signal changes from a-level to high level. Indicates changes in the signal. However, Fig. 3(A).

The input shown in (B) is at the rTL level, and after receiving an input signal input from outside the IC and converting this input signal to a CMOS level by an inverter in the IC, the input signal is sent to the input terminal 15.
is being entered. Note that the load capacity connected to the output terminal 16 is 50 pF, the load resistance is 1Ω, and the power supply voltage is 5V.

In FIG. 3(A), the solid line ■ represents the change in the output signal of the circuit of this embodiment, and the broken line represents the change in the output signal of the conventional circuit shown in FIG. As can be seen from FIG. 3(A), the rise of the output signal is almost the same as that of the conventional circuit.

On the other hand, as shown by the solid line ■ in FIG. 3(B), the fall of the output signal of the circuit of this embodiment is indicated by the broken line ■ in FIG. 3(B).
It can be seen that the fall of the output signal of the conventional circuit shown in 3° is considerably faster.
In this embodiment, the base current required when the transistor P3' is turned on is extracted from the base current control circuit 1 through the source and drain of the transistor P3'.
Since the second current from 2 is added, the 5th current
Compared to the size of transistor P3 in the figure, transistor P
The gate width of 3- can be reduced to 1/2. .

Therefore, when the output signal is at low level, the transistor Q
The base current to 3 is 1/2 that of the conventional one, and the power consumption at that time is also 1/2 because the power supply voltage is constant.

Note that the present invention is not limited to the above-described embodiment, and similarly, the base ff1l of the transistor Q1 is increased only when the output signal changes from low level to high level to speed up To LH. You can also do that.

FIG. 4 shows a circuit diagram of another embodiment of the present invention in this case, and in the same figure, the same components as in FIGS. .

In FIG. 4, the base current control circuit 12 includes P-channel MO3 type field effect transistors P4 and P5 and NP
It consists of an NI-transistor Q4 and a resistor R2.

Transistor P4 has its gate connected to the gate of transistor P2, and its drain connected to the source of transistor P5. Further, the gate of the transistor P5 is connected to the connection point (2) via the resistor R2, and the drain thereof is connected to the base of the transistor Q4.

This base current! 1) The control circuit 12 operates when the input signal at the input terminal 15 changes from a low level to a high level and the point (2) is at a low level that has not yet changed to a high level. At this time, the input of transistor P4 becomes low level, and P4 is turned on. In addition, the input of transistor P5 becomes low level, and P5 is also turned on.
, therefore, transistor Q4 is turned on and current is supplied through Q4 to the base of transistor Q1. As a result, the base current of the transistor Q1 increases compared to the steady state, and the output signal changes from low level to high level in a shorter time than before from the time when the input signal changes to high level.

FIG. 6 is a diagram showing the phase relationship between the input signal and the output signal.

C Effect of invention f! ] As described above, according to the present invention, when the input signal logic level dynamically changes the amount of base current of the bipolar transistor constituting the output stage transistor, it changes when the input signal logic level changes statically (when the input signal logic level changes). (when the logic level does not change), the logic level of the output signal can change quickly in response to changes in the logic level of the input signal, and the power consumption in steady state can be reduced compared to the conventional method. It has features such as the ability to

In the figure, 11 is an output stage transistor, 12 is a base current υ) control circuit, Xl is a bipolar transistor, Q+ and Q3 are Schottky clamped transistors, and Q2 and Q4 are NPN transistors.

Patent applicant: Tomitsu Co., Ltd. ・NPN

[Brief explanation of the drawing]

Fig. 1 is a principle configuration diagram of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a waveform diagram of an embodiment of the invention, and Fig. 4 is another embodiment of the invention. Figure 5 is a circuit diagram of an example of the conventional circuit. Figure 1 Figure 6

Claims (1)

[Claims] In an output buffer circuit in which the output stage transistor (11) has a Bi-CMOS configuration in which the output end of a field effect transistor is connected to the base of a bipolar transistor (X_1), the output stage transistor (11) A base current that detects the level of each of the input signal and the output signal, and increases the base current of the bipolar transistor (X_1) only when the logic level of the output signal changes in accordance with the change in the logic level of the input signal. An output buffer circuit comprising a control circuit (12).