JPH0529847A - Active load circuit and differential amplifier circuit using the same - Google Patents

Abstract

PURPOSE:To make the rising or falling of an output logical signal faster while suppressing power consumption by enhancing the drawing efficiency of a gate electric load. CONSTITUTION:An active load circuit is provided with a first MOS transistor inserted in the first circuit and the second MOS transistor inserted in the second circuit, connects the gates of the first and second MOS transistors so as to be constituted and connects a constant current source with the gates of the first and second MOS transistors in a mirror circuit which permits same quantity current or n-fold current when compared with current flowing in the first circuit to flow in the second circuit. A differential amplifier is provided with the two sets, at least, of active load circuits, uses the first MOS transistors of the respective sets as the respective active load elements of a pair of differential transistors and also uses the second MOS transistors of the respective sets as output switching elements or the driving elements of the switching element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active load circuit and a differential amplifier using the same, and more particularly to an active load circuit composed of MOS transistors. In recent years, a bipolar transistor / C having both high speed and low power consumption
MOS transistor mixed type IC, so-called Bi-CM
OS type ICs are often used, but in such ICs,
It is required to convert an analog signal of arbitrary amplitude into a CMOS logic signal.

[0002]

2. Description of the Related Art FIG. 6 is a diagram of a conventional level conversion circuit applied to this type of signal conversion, which is an example of a level conversion circuit using a differential amplifier including an active load circuit. In FIG. 6, Q ₁ and Q ₂ are differential transistors, C ₁ is a constant current source,
INV ₁ is inverted _{circuit, T 1a, T 1b, T} 2a, T 2b, T3a and T _3b are MOS transistors, PMO at T _{1 a} and T _1b
A first mirror circuit M ₁ having an S configuration is configured, and a second mirror circuit M ₂ having a PMOS configuration is configured by T _2a and T _2b .
T _3a and T _3b form a third mirror circuit M ₃ having an NMOS configuration.

The mirror ratio of M ₁ is 1, and the mirror ratios of M ₂ and M ₃ are both n times (n> 1). Due to these mirror ratios, the current I ₁ flowing through T _1a is 1 time. I ₄ flows to T _1b, and a current I ₅ n times as large as the current I ₂ flowing to T _2a is T _2b.
Current, which is n times the current I ₄ flowing through T _3a ,
That is, since I ₄ = I ₁ , the current I ₆ n times as large as I ₁ is T _{3 b}
Flow into.

Now, when the magnitude relationship between the _two input signals V ₁ and V ₂ is V ₁ > V ₂ , Q ₁ is on and Q ₂ is off,
Since I ₁ = I ₃ and I ₂ = 0, T _3b has a current I ₆ n times as large as I _1.
As a result, the potential at point A is lowered to a low potential level equivalent to V _SS . On the other hand, when V ₁ <V ₂ , contrary to the above, Q ₁ is off and Q ₂ is on, and I ₁ = 0, I ₂ = I ₃
As a result, a current I ₅ n times as large as I ₂ flows through T _2b, and the potential at the point A is raised to a high potential level equivalent to V _CC .

That is, the levels of the input signals V ₁ and V ₂ are V
_It is converted into a binary logic of H logic corresponding to _CC and L logic corresponding to V _SS , and this logic signal is inverted by INV ₁ and then output as V _o .

[0006]

However, in the above circuit, the gates of the MOS transistors T _1a and T _2a of the first and second mirror circuits M ₁ and M ₂ are respectively connected to the differential transistor Q. _Since it was configured to connect to the collectors of ₁ and Q ₂ , immediately after the differential transistor was turned off, T
The gate charge of _1a or T _2a is not smoothly extracted, and T _1a
And T _2a off transition is delayed.

Therefore, these MOS transistors T
The transition time from ON to OFF of the other MOS transistors T _1b and T _2b , which are in a mirror relationship with _1a and T _2a , becomes long, and the load current continues to flow through T _1b and T _2b during that time, resulting in a large power consumption. Problems and output logic signal V
There is a problem that the rising tp _LH or the falling tp _{HL of o} is delayed (see FIG. 7).

The present invention has been made in view of the above problems, and it is an object of the present invention to accelerate the rise and fall of the output logic signal while suppressing the power consumption by increasing the efficiency of extracting the gate charge. To do.

[0009]

An active load circuit according to the present invention has a first MOS transistor inserted in a first circuit and a second MOS circuit inserted in a second circuit as shown in the principle diagram of FIG. And a second MOS transistor formed by connecting the gates of the first and second MOS transistors to each other. In the active load circuit that flows into the second circuit, a constant current source is connected to the gates of the first MOS transistor and the second MOS transistor.

Further, the differential amplifier according to the present invention comprises at least two sets of the active load circuits, each set of the first MOSs.
The transistor is used as each active load element of the pair of differential transistors, and the second MOS transistor of each set is used as an output switching element or a switching element driving element. More preferably, the current value of the constant current source (C ₁₁ ) is set to the first M
5% of the maximum current flowing in the drain of the OS transistor
It is characterized by being 20%.

[0011]

In the present invention, the off-transition speed of the first MOS transistor and the second MOS transistor is accelerated by supplying the gate current from the constant current source. Therefore, can block unwanted load current supplied to the early, it is possible to suppress power consumption, it is possible to accelerate the rise fall of the output logic signal V _o.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 are diagrams showing an embodiment of an active load circuit according to the present invention and a differential amplifier using the same, which is an example applied to a level conversion circuit as in FIG. Note that FIG.
The same parts as those in FIG.

The difference between FIG. 2 and FIG. 6 is that two constant current sources are added. That is, the constant current source C ₁₁ is connected between the gates of the MOS transistors T _1a and T _1b of the first mirror circuit M ₁ and V _CC , and the M of the _second mirror circuit M ₂ is further connected.
A feature of this embodiment is that a constant current source C ₁₂ is connected between the gates of the OS transistors T _2a and T _2b and V _CC . Here, in the first mirror circuit M ₁ , one MOS transistor (first MOS transistor) T _1a is inserted into the circuit on the differential transistor Q ₁ side as the first circuit, and the other MOS transistor ( Second MOS transistor) T _1b
Is inserted in the second circuit including T _3a . A current (sink current) I _{4 that} is 1 times the current I ₁ flowing in the first circuit
Is poured into the second circuit.

The second mirror circuit M ₂ has one M
OS transistor (first MOS transistor) T
_2a is inserted in the circuit on the side of the differential transistor Q ₂ as the first circuit, and the other MOS transistor (second MOS
Transistor) T _2b is inserted in the second circuit including T _3b . A current (sinking current) I ₆ which is n times the current I ₂ flowing in the first circuit is flown into the second circuit.

Further, a pair of differential transistors Q₁, Q₂
Is the first to third mirror circuits M₁~ M₃Differential with
An amplifier is configured, and this differential amplifier is a MOS transistor.
T _1a, T_2a(First MOS transistor)
Register Q₁, Q₂MOS transistor as an active load of
T_2bIs a switching element on the H logic side, and
Dista T_3bIs a switching element on the L logic side, and a MOS
Transistor T_2bThe switching element T_3bDrive element of
To use.

In the above configuration, the input signal is (1)
When changing from the state of V ₁ > V _{2 to} the state of V ₁ <V ₂ ,
(2) On the contrary, consider the case where the state of V ₁ <V ₂ changes to the state of V ₁ > V ₂ . In the case of (1), “Q ₁ ” changes from on to off, and in the case of (2), “Q ₂ ” changes from on to off. In any case, the MOS transistor "T" connected to the off-transition side transistor
The drain-source voltage of " _1a " or " _T2a " becomes equal to or lower than the pinch-off voltage and also changes from on to off.
Here, a constant current source C ₁₁ is connected to the gate of T _1a , and a constant current source C ₁₂ is connected to the gate of T _2a , and these constant current sources both function as a constant current source of the source.

Therefore, at the time of off-transition of T _1a and T _2a , current can be supplied from the constant current sources C ₁₁ and C ₁₂ to quickly extract the gate charge, and the off-transition time can be shortened. As a result, T _2b or T _1b (T _3a ,
T _3b ) can be turned off immediately, the load current can be cut off immediately to reduce power consumption, and
As shown in FIG. 3, the fall and fall of the logic signal V _o can be shortened.

Here, the current values of the constant current sources C ₁₁ and C ₁₂ are
When the ratio with the current value of the constant current source C ₁ (maximum value of I ₁ and I ₂ ) is set within a certain range (5% to 20%),
You can get the maximum effect. Although the constant current source is connected to the mirror circuits other than the third mirror circuit M ₃ in the above embodiment, the present invention is not limited to this, and, for example,
As shown in FIG. 4, 2 which constitutes the _third mirror circuit M _3.
One of the MOS transistors T _3a, may be connected to sink a constant current source C ₁₃ between the gate and V _{S S} of T _3b.

In this way, the off transition time of T _3a can be further shortened, and T _3b can be turned off quickly. Accordingly, as shown in FIG. 5, it can be further shorten the rise of V _o.

[0020]

According to the present invention, the gate charge extraction efficiency can be increased, and the rise and fall of the output logic signal can be accelerated while suppressing the power consumption.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a waveform diagram of an example.

FIG. 4 is another configuration diagram of the embodiment.

FIG. 5 is another waveform diagram of the example.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is a waveform diagram of a conventional example.

[Explanation of symbols]

T _1a : MOS transistor (first MOS transistor) T _2a : MOS transistor (first MOS transistor) T _1b : MOS transistor (second MOS transistor, drive element) T _2b : MOS transistor (second MOS transistor) , Output switching element) M _{1 to} M ₄ : mirror circuits C ₁₁ , C ₁₂ : constant current sources Q ₁ , Q ₂ : differential transistors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0175

Claims (3)

[Claims] 1. A first MOS transistor inserted in a first circuit, and a second MOS transistor inserted in a second circuit. The first and second M-transistors are provided.
The gates of the OS transistors are connected to each other to form a first
In the active load circuit for flowing the same amount of current or n times as much current into the second circuit into the second circuit, a constant current source is connected to the gates of the first MOS transistor and the second MOS transistor. Characteristic active load circuit. 2. An active load circuit according to claim 1, comprising at least two sets, wherein each set of first MOS transistors is used as an active load element of a pair of differential transistors, and each set of second load transistors is used. A differential amplifier characterized in that a MOS transistor is used as an output switching element or a switching element driving element. 3. The active load circuit according to claim 1, wherein the current value of the constant current source (C ₁₁ ) is 5% to 20% of the maximum current flowing through the drain of the first MOS transistor.