JPS63300623A - Semiconductor buffer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention is directed to integrated semiconductor circuits, and more particularly to receiving human input signals from circuits having low voltage level signals, i.e. signals with small swings. Complementary Metal Oxide Semiconductor (CMO3), or Complementary Field Effect Transistor (F
ET) relating to circuits.

B. Prior Art Semiconductor receivers (passive circuits), ie, buffer circuits, having low voltage level signals, ie, small swing signals, such as the output from bipolar circuits, are known.

U.S. Pat. No. 4,438,352 discloses a CMO 8-channel buffered circuit compatible with transistor-transistor logic circuits (TTL), and the device includes gate electrodes of a series circuit with first and second P-channel transistors. a second N-channel transistor connected in parallel with the second P-channel transistor; and a common input between the first N-channel transistor and the second P-channel transistor; and an output connected to a point.

Other examples of TTL to CMO8 input buffers or level shifting circuits are disclosed in US Pat. No. 4,258,272 and US Pat. No. 4,475,050. Also,
U.S. Pat. No. 4,031,490 discloses a circuit for converting binary signals from bipolar transistor logic circuits to the level of the analog signals required by insulated gate field effect transistor circuits.

CMOS circuits compatible with emitter-coupled logic circuits
It is disclosed in US Pat. No. 4,437,171.

Problems that the C8 invention seeks to solve: Since the signal level changes, or signal swings, in bipolar devices are much smaller than the signal level changes required for normal CMO5 circuit operation, CMO8 circuits for bipolar technology The interface of 9C which has a normal 5 volt power supply has some problems.
MO3 circuits are typically optimized to switch transistor elements at around 2.5 volts. However, conventional bipolar technology circuits have positive potential rising levels of, for example, at least 1.5 volts and negative potential falling levels of at least 0.6 volts. Other bipolar circuits, such as TTL circuits, have voltage levels of 2 ports and 0.8 volts as corresponding voltage levels.

The output voltage from these bipolar circuits is the normal CM
It can be appreciated that it is difficult to use the O5 circuit as a signal for switching. However, the N-channel devices and P
Although it is possible to change the center of the switching point by modifying the size of the channel device, variations in supply voltage and process parameters may limit tolerance limits. It becomes bigger than that.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new CMOS receiver of simple construction for use with low input voltage levels, which provides high efficiency, high density and low power consumption (in some conditions The aim is to achieve a semiconductor device with zero consumption.

Means for solving the D0 problem According to the invention, a CMOS receiver or buffer circuit of simple construction is provided, which comprises a first inverter having an output terminal connected to an input terminal of the second inverter. , means connected in parallel to the first inverter for causing the first inverter to initiate faster switching operations at a lower voltage switching input.

A CMOS receiver or buffer circuit of an embodiment of the invention includes first and second P-channel devices and a first
a first series circuit having an input terminal connected to a control electrode of each of said devices and connected in parallel to a first P-channel device and a first N-channel device; a second series circuit including a first P-channel device and a first N-channel device;
The device includes an output terminal located at the common point of darkness.

E. Embodiment Referring to FIG. 1, there is shown a CMOS receiver or buffer circuit according to the present invention, which comprises a first series transistor having first and second P-channel transistors 12 and 14. It includes a circuit 10 and a second series circuit having a second N-channel transistor 20 and a third N-channel transistor 22 connected as a diode. A first series circuit 10 having an output node, ie terminal N1, is connected between the power supply terminal VH and a reference potential, such as ground potential, and a second series circuit 18 has an and a common node N2 between the second P-channel transistors 12 and 14;
Connected between ground potential. First series circuit 10
Transistors 12 and 14 operate as inverters. The input terminal IN is connected to the first and second P channels.
It is connected to the control electrodes of transistors 12 and 14 and to the control electrode of a second N-channel transistor 20.

Furthermore, the circuit of FIG. 1 includes a first inverter 24 having a third P-channel transistor 26 and a fourth N inverter 24 having an output node, i.e., output terminal N3, at its drain electrode.
channel transistor 28. The gate electrodes of the third P-channel transistor 26 and the fourth N-channel transistor 28 are connected to the output terminal N1 of the first series circuit 10. The second inverter 30 includes a fourth P-channel transistor 32 and a fifth N-channel transistor 34 having input terminals connected to the output terminal N3 of the first inverter 24.
and an output terminal N4. Third inverter 3
6 includes a fifth P-channel transistor 38 and a sixth N-channel transistor 40 having input terminals connected to the output terminal N4 of the second inverter 30, and an output terminal N5. The antilog output signal from the circuit of FIG. 1 is provided at an output terminal OUT connected to the output terminal N5 of the third inverter 36, and the complement output signal from the circuit of FIG. The output terminal 1 is connected to the output terminal N4 of the inverter 30.

The P-channel transistor 14 of the first series circuit is a current source whose current value is a function of the input terminal IN, the supply voltage VH and the voltage at node N2. Transistor 22 connected as a diode is an N-channel transistor.
Provides a process dependent voltage offset from the drain of transistor 20. P-channel transistor 12 is a current source whose current value is a number between the input voltage IN and the conduction state of transistors 14, 20 and 22. Transistor 12 controls the amount of current that must be switched by N-channel transistor 16, thereby controlling the switching of the receiver circuit when terminal N1 changes from a high potential to a low potential or from a low potential to a high potential. Set a point. 1st N channel
Transistor 16 is P-channel transistor 12
A switching device having a current magnitude and a current generated by the receiver circuit determines the value of the input voltage IN that causes switching in the receiver circuit. N-channel transistor 20 is a current source whose current value depends on the input terminal. transistor 20
turns off completely near low input voltages. Along with transistors 14 and 22, transistor 20:
Determine the supply voltage of transistor 12, which in turn is
The current flowing through transistor 12 is influenced to change the switching point of the receiver circuit. For increasing levels of input voltage, transistor 12 is completely turned off.

P-channel transistor 2 of first inverter 24
6 and N-channel transistors 28 are sized to accommodate subsequent inverter, buffer, or amplifier stages 30 and 3.
6, the switching points of the input stage of the receiver circuit are selected to transform them to optimal values. transistor 2
Correctly choosing the sizes of 6 and 28 will produce symmetrical delay characteristics in the circuit. The operation of the receiver or buffer circuit of the present invention of FIG. 1 is better understood by reference to the voltage versus time graph at the nodes, terminals IN, N1, N2 and N3, shown in FIG. I can do it.

When voltage supply terminal VH is at +5 volts and at time 0, the input terminal at terminal IN is at +0.4 volts, P-channel transistors 12 and 14 are on and transistors 16 and 20 are on. , is off, so the voltage at terminals N1 and N2 is at +5 volts,
At this point, power consumption is zero. If the voltage at terminal N1 is +5 volts, transistor 28 is on and transistor 26 is off, so the output voltage at terminal N3 is 0 volts. 10 nanoseconds (ns)
At a time of , the input voltage at terminal IN is approximately +2
As it begins to increase to +4 volts, the voltage at terminal N2 rapidly decreases to about +1.8 volts due to transistor 20 turning on. During the transient period, when the voltage at IN increases and the voltage at terminal N2 decreases to the point where P-channel transistor 12 is completely off, N-channel transistor 16 switches to terminal N1. discharge freely.

The decrease in voltage at terminal N1 causes the output of first inverter 24 to rapidly switch from 0 volts to the full supply voltage of +5 volts within a few nanoseconds.

At a time of 20 nanoseconds, the input voltage IN is at its maximum voltage of +2.4 volts, terminal N1 is at 0 ports, and terminal N
2 is at +1.8 volts and terminal N3 is at +5 volts. An input voltage IN of magnitude between +0.4 volts and +2.4 volts can be considered as a full swing of voltage from a TTL bipolar circuit.

As shown in the graph of FIG. 2, the terminal IN.

The voltages on N1, N2, and N3 are held constant between 20 and 50 nanoseconds, and at a time of 50 nanoseconds, the input voltage is decreased toward +0.4 volts and terminal N
The voltage at terminal N2 increases rapidly toward +5 volts, and the voltage at terminal N1 increases even faster toward +5 volts, while the voltage at terminal N3 decreases to 0 volts.

At a time of 60 nanoseconds, the voltage at terminals IN, Nl, N2, and N3 is the same voltage value that those terminals had at a time from 0 nanoseconds to 10 nanoseconds.

Although not shown in the graph of FIG. 2, the voltage at the output terminal N4 of the second inverter 30 is the complement of the voltage at the output terminal N3 of the first inverter 24. In other words,
If the voltage at output terminal N3 is a high potential representing, for example, one binary digit of information, the voltage at output terminal N4 is a low potential representing a zero binary digit. 8th
The voltage at the terminal N5 of the second inverter 36 corresponds to the voltage at the terminal N3 representing the antilog output, or to the voltage at the terminal OUT of the receiver circuit of FIG.
The voltage at terminal N4 represents the complement output signal or the voltage at terminal ■π of the receiver circuit of FIG.

It should be noted that the receiver circuit of the present invention shown in FIG. 1 can be operated without malfunction even with input voltage swings much smaller than the swings shown by the graph in FIG. 2. There is. For example, as shown in FIG. 3, without causing any malfunction in this circuit,
The input voltage swing of the input terminal IN is approximately +1.1 to +
It can be narrowed to between 1.7 volts. Supply voltage VH
With +5 volts and an input voltage of +1.1 volts at terminal IN, N-channel transistors 16 and 20 will be slightly conductive and P-channel transistors 12 and 14 will be fully conductive. . Therefore,
The voltage drop across P-channel transistors 12 and 14 causes the voltage at terminal N1 to be approximately 3.7 volts;
The voltage at terminal N2 is then approximately 4.2 volts, and the N-channel transistor 28 of the first inverter 24 is
Since it conducts more strongly than P-channel transistor 26 conducts, the voltage at terminal N3 will be near 0 volts. At a time of 10 nanoseconds, the input voltage IN increases by +1.
As it begins to increase toward 7 volts, the voltage at terminal N2 begins to drop to approximately +2.6 volts, and the N-channel
As transistors 16 and 20 conduct more strongly and P-channel transistor 12 turns completely off,
The voltage at terminal N2 drops more rapidly towards 0 ports.

Therefore, the voltage at terminal N3 of inverter 24 causes transistor 28 to turn off and transistor 26 to
As it turns on, the voltage rapidly rises from 0 volts to +5 volts. In a time of 50 nanoseconds, the input voltage 1N is +1.7
volts to +1° 1 volts, reducing the conduction of N-channel transistor 16 and reducing terminals N1 and N1.
2 are returned to +3.7 volts and +4.2 volts, respectively, and the voltage at terminal N3 is also returned to 0 ports.

For a given range of supply voltage variations and process parameters, the circuit of P-channel transistors 12 and 14 and N-channel transistors 16 and 20 can be configured such that the small input voltage swing IN shown in FIG. It should be noted that in order to be properly controlled, the device parameters of the circuit, ie the parameters of the transistors, must be suitably adjusted in a known manner.

In FIG. 4, a graph of the combined switching characteristics of the receiver circuit of FIG. 1 is shown for a given supply voltage variation, temperature variation, and process parameter variation.

When the voltage at the input terminal IN increases to approximately +1°3 volts,
The output terminal OUT always increases to VH, and the input terminal IN
When the voltage decreases below 100°9 volts, the output terminal OUT always decreases to 0 volts.

It should be noted that those skilled in the art can make changes and modifications to the circuit of FIG. 1 as necessary.

For example, N-channel transistor 22 can be formed by a plain and simple PN junction or by a resistive impedance. Additionally, if desired, the control electrode of the N-channel transistor 20 of the second series circuit 18 can be connected to any suitable point at a constant reference potential ranging from 0 volts to ■H ports. , such a fixed reference potential may be made variable under external changes such as operating temperature but process conditions.

Also, various modifications can be made to this circuit by utilizing appropriate known feedback techniques.

Another embodiment of the invention for detecting small signal swings with respect to the reference voltage VH is to invert the polarity of the transistors and to connect the VH connection of the first series circuit 10 and the ground connection of the second series circuit. It can be created by reversing the .

Although the invention has been described with respect to relatively low input voltages in connection with the operation of the example receiver circuit, input voltage swings from the VH voltage to ground may also be used if desired. It goes without saying that it can be done.

As detailed in the F9 invention, the present invention provides an 0M05 circuit that can operate with small swing signals, thereby providing high efficiency, high density integration, and low power consumption. A CMOS receiver or buffer circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram of an embodiment of the receiver or buffer circuit of the present invention, and FIG. 2 shows the voltage versus time at selected points of the circuit of FIG. 1 when a full input swing is applied to the input terminals. The graph, Figure 3, shows that when a smaller voltage input swing is received than the expected full human power swing, the first
A graph of voltage versus time at selected points of the circuit in Figure,
FIG. 4 is a graph showing the switching characteristics of the receiver of FIG. 1, that is, the buffer circuit. 12...first P-channel transistor, 14
...Second P-channel transistor, 16...
...First N-channel transistor, 2°...
second N-channel transistor, 22...third
N-channel transistor, 26...third P
channel transistor, 28... fourth N-channel transistor, 32... fourth P-channel transistor, 34... fifth N-channel transistor;
Transistors, 38...Fifth P-channel transistor, 40...Sixth N-channel transistor.

Claims (1)

[Claims] First and second transistors (12, 14) of the same conductivity type, either P-channel or N-channel, and a third transistor of the opposite conductivity type to the first and second transistors. (16), a first series circuit (10) formed by interconnecting adjacent electrodes other than the control electrode at connection points (N2) and (N1), respectively; A series circuit in which mutually adjacent electrodes other than the control electrode of a fourth transistor (20) of the same conductivity type as the third transistor are interconnected, and the connection point (N2) and the third transistor are interconnected. a second series circuit (18) connected in parallel between the electrodes not connected to each other; and an input terminal (IN) connected to the first, second, third, and fourth transistors; A semiconductor buffer circuit whose output terminal is N1).