JPS58108820A - Schmitt circuit - Google Patents

Abstract

PURPOSE:To obtain a Schmitt circuit which consists of less elements and has excellent characteristics by a C-MOS process. CONSTITUTION:In a figure, Q1, Q2, and Q3 are P channel MOS.FET elements, and Q4 is an N channel MOS.FET element. When an input level is higher than the earth level, the elements Q1 and Q2 are turned on and the Q3 and Q4 are turned off. When the input level rises above a threshold voltage VTH, a voltage i1.RON=VDS (RON: source-drain resistance value in on state) is developed between the drain and source of the Q2. When it further rises, the voltage VDS exceeds the threshold voltage VTH of the Q3 and a current i2 starts flowing. In this case, the current i1 decreases. Then, the potential at a connection point P2 drops and the channel of the Q3 becomes wider to further increase the current i2, so that the current i1 is further decreased. This positive feedback inverts the level at an output terminal OUT abruptly. If the input level drops below a level VCC, the current i1 starts flowing similarly and the current i2 decreases, inverting the level at the output terminal OUT abruptly through this positive feedback.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schmitt circuit, and particularly to one realized in a C-MOS process.

Waveforms handled by logic circuits are often required to have steep rises and falls. □A Schmitt circuit (or Schmitt-Trial circuit) is used to correct the shape of a slow waveform such as a sine wave, or a waveform that has become dull or distorted during transmission.

In other words, a Schmitt circuit is a circuit used as an interface between the analog domain and the digital domain.
The basic purpose is to convert analog inputs with very slow transition times or noisy voltages to logic levels with a sharp single transition when the required Threnjord voltage is reached. It also has hysteresis characteristics to suppress noise and parasitic oscillation.

A conventional Schmitt circuit constructed of discrete components is shown in FIGS. 1 and 2. Figure 1 shows inverter c1
, c2 are connected in two stages and positive feedback is applied.

However, it is necessary to use a feedback resistor 2 with a high resistance value, which poses many problems when integrated into an IC. On the other hand, the circuit in FIG. 2 includes inverters G3, G4, NAND circuit G5. G6
It is a commonly used circuit that is realized by a C-MOS process. (It is used by setting it to V-)
.

However, 12 basic MOS elements are required,
There are many problems. A device with a small number of elements (and good characteristics) is desired.

This invention was made in view of the above problems, and C-M
The purpose of this invention is to provide a new Schmitt circuit with a small number of elements and good characteristics using an OS process.

The configuration of the present invention includes a first MOS of the first conductivity type for the power supply.
, the source of the first MOS-FET is connected to the drain of the first MOS-FET, and the sources of the second MOS-FET and the third MOS-FET of the first conductivity type are respectively connected, and the second MOS-FET is connected to the source of the second MOS-FET, The third MOS is connected to the drain of the FET.
, the gate of the FET is connected, and the fourth MOS of the second conductivity type is connected to the drain of the FET, and the fourth MO
The source of the S-FET and the drains of the third MOS and FET are commonly grounded, and the gates of the first MOS-FET and the second MOS, FET and the third MOS and FET are commonly grounded. It is characterized in that the input signal is inputted to the second MOS-FET while the output is derived from the drain of the second MOS-FET.

The present invention will be explained below with reference to illustrated embodiments.

FIG. 3 shows a Schmitt circuit with four elements manufactured using a C-MOS process. Ql, G2. G3 is a P-channel MOS, FET element, and G4 is an N-channel MOS
, is an FET element (hereinafter, MOS and FET elements are simply referred to as "elements").

In connection of the elements, the source of the element Q1 is connected to the power source Wee, and the source of the element Q2°G3 is connected to the drain of the element Q1. The gate of element q3 is connected to the drain of element Q2, and the conductivity type of element q3 is connected to the drain of element Q2.

Connect the drains of different elements q4. The source of element Q4 and the drain of element Q3 are grounded. Element Q1. element q
2 and the gates of element Q4 are connected in common, and an input terminal IN is derived from this. The output terminal OUT is connected to the element q
2 (or the gate of element Q3 or the drain of element q4).

In the circuit configured as described above, the operation when the input level rises above the ground level will be described.

Initially, element q1 and element Q2 are in the ON state (conducting state), and element Q3 and element q4 are in the OFF state (non-conducting state). When the input level rises and exceeds the threshold voltage ■TH of element q4, current i□ begins to flow. Then, il・RO is connected between the drain and source of element q2.
A voltage VDs is generated at N=■DS (note that RON is the resistance value between the drain and source when conductive). When the input level further increases, the voltage VDS increases to the element Q
3 threshold voltage VTH is exceeded, and element q3 becomes ONL.
,, current 12 begins to flow. However, at this time, element Q
Since the current flowing through l does not change, the current i
□ decreases. Then, the potential at the connection point P2 decreases, the channel of the element Q3 becomes wider, and the current i2 further increases. On the other hand, the current i□ further decreases. Due to such positive feedback.

As shown in the input/output characteristic diagram of FIG. 4 (corresponding to the input value V0), the output terminal OUT is rapidly reversed.

Next is the case where the input level falls below the VQC level. Initially, element Q1. Q2. Q3 is in the OFF state (3), and element Q4 is in the ON state. When the input level begins to fall, element Q1 is first turned on. At this time, element Q2
are not turned on at the same time.

This is because the source of element Q2 is floating above the level Vcc, so it is back biased and the threshold voltage ■T
This is because H increases. When element Ql turns on, element Q3 turns on. The input further decreases, and the input voltage becomes lower than the potential of the connection point P1 to the threshold voltage 71 of the element Q2.
When the temperature drops by the amount of the mouth, element q2 turns ON. Current 11 begins to flow and current i2 decreases. As current 10 begins to flow, the potential at connection point P2 increases, the voltage between the gate and source of element Q3 decreases, and current 12 decreases. Due to such positive feedback, as shown in the input/output characteristic diagram of FIG. 4 (corresponding to the input value V-), the output terminal OUT is rapidly reversed.

In this way, since the conditions required for the output to rapidly invert are different, a Schmitt circuit having hysteresis characteristics as shown in FIG. 4 can be constructed. By the way, P channel/I/M
O5, element Ql as FET.

Q2. Threshold voltage i at Q3 ■Tl(P
=-0,6, conduction factor; βp=8.2
゜BKP=0.33, while N channel M
O3, threshold for element q4 which is FET)
Designed as follows: voltage i VTHN = 0.6, conduction factor; βN = 15.9, BKN = 2.6, and in all devices, the ratio of channel width W to channel length W/ If L is designed to be 1, V+=2.4
0 (V), V = 1.55 (V).

Such a Schmitt circuit has the following characteristics: ■ The amplitude of the output voltage swings to the maximum between the ground level and the power supply VCC level;
Low power consumption, ■Inversion voltage is β (conduction
(2) It has the advantage that it is determined by the factor (2), so it is relatively stable, and (2) it can be constructed entirely of MOS transistor elements of the minimum size, depending on the case.

In the above embodiment, there are three P channel elements and one N channel element.
Although an example using channel elements has been shown, the present invention is not limited to this, and may be configured with three N-channel elements and one P-channel element.

As described above, according to the present invention, it is possible to obtain a Schmitt circuit with a very small number of elements (4) and good characteristics using a C-MOS process.

[Brief explanation of the drawing]

FIG. 1 is an illustrative diagram of a conventional Schmitt circuit shown in a discrete configuration, FIG. 2 is an illustrative diagram of another Schmitt circuit,
FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is an input/output characteristic diagram of the circuit q in FIG. 3.
...P channel MO5, FET element, Q4...
...N-channel MO8, FET element patent applicant Ricoh Co., Ltd.

Claims (1)

[Claims] (1) A first MO5, FET of the first conductivity type is connected to the power supply (
7) 7-swo connection L, the i-th (y) MOS, F E
A second MO5-FET of the first conductivity type and a source of a third MO5, pET are respectively connected to the drain of the T,
The second MO5 and the third MO5 are connected to the drain of the FET.
8. Connect the gate of the FET and connect the drain of the fourth MO5, FET of the second conductivity type, and connect the source of the fourth MO8, FET and the drain of the third MO5, FET in common. grounded to the first MO5, FET
and the second MO8, FET, and the fourth MO5, FE.
The respective gates of T are connected in common, and the fourth
While inputting the input signal to the gate of MO5 and FET,
A Schmitt circuit characterized in that the output is derived from the drain of the second MO5 and FET.