CN114744995A - Level conversion circuit and chip comprising same - Google Patents

Abstract

The utility model provides a level shift circuit reaches chip including level shift circuit relates to integrated circuit technical field. The level shift circuit includes: the level conversion module is provided with an input end, an output end and a bias current control end and is used for carrying out level conversion on an input signal received by the input end under the control of bias current input by the bias current control end and outputting a signal after the level conversion through the output end; and the current bias module is connected between a first power supply and a bias current control end of the level conversion module and is used for providing bias current for the level conversion module so as to accelerate the level conversion output of the level conversion module. According to the level conversion circuit and the level conversion chip, the level conversion output can be accelerated through the introduction of the current bias module, and the input signal with smaller voltage is processed.

Description

Level conversion circuit and chip comprising same

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a level shifter and a chip including the level shifter.

Background

In deep sub-micron chips, device feature sizes such as gate oxide thickness and channel length are greatly reduced, along with the power supply voltage that must be lowered to match the decreasing device, otherwise the gate oxide may be broken down or the transistor channel may be penetrated. For example, for 90nm technology, the supply voltage is 1.0V. However, the power supply voltage of a chip is 3V or 2.5V, so a level conversion circuit is required to convert an external high voltage signal into a corresponding internal low voltage signal, convert an internal low voltage signal into a corresponding external high voltage signal, or convert the operating voltage between different modules (different voltage domains) inside the chip. In addition, the signal transmission between different modules also needs to switch the working voltage through a level conversion circuit.

However, the conventional level shift circuit has low conversion efficiency, and when the level shift circuit is used for level shifting between circuit modules with large input voltage changes, the level shift circuit has poor adaptability and cannot process input signals with low voltage.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a level shifter and a chip including the same, which at least to some extent overcome the problem that the level shifter provided in the related art cannot handle input signals with lower voltages.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a level conversion circuit including:

the level conversion module is provided with an input end, an output end and a bias current control end and is used for carrying out level conversion on an input signal received by the input end under the control of the bias current input by the bias current control end and outputting a signal after the level conversion through the output end;

and the current bias module is connected between a first power supply and the bias current control end of the level conversion module and used for providing the bias current for the level conversion module so as to accelerate the level conversion output of the level conversion module.

In one embodiment of the present disclosure, the current bias module includes:

the bias voltage generating module is used for outputting bias voltage;

and the bias current control module is connected with the bias voltage generation module and used for generating the bias current under the control of the bias voltage and providing the bias current to the level conversion module through the bias current control end.

In an embodiment of the disclosure, the bias voltage generating module is connected to the first power supply and provides the bias voltage to the bias current control module through a first node, and the bias current control module is connected to the first power supply and a bias current control terminal of the level shift module.

In one embodiment of the present disclosure, the bias voltage generating module includes:

a first PMOS transistor, wherein the source electrode of the first PMOS transistor is connected with the first power supply, and the grid electrode and the drain electrode of the first PMOS transistor are both connected with the first node;

the drain electrode of the first NMOS transistor is connected with the first node, the grid electrode of the first NMOS transistor is used for receiving reference voltage, the source electrode of the first NMOS transistor is connected with a second power supply, and the voltage of the second power supply is lower than that of the first power supply.

In one embodiment of the present disclosure, the reference voltage is lower than a voltage of the first power supply, the reference voltage is higher than a voltage of the second power supply, and the reference voltage is the same as a high level voltage of the input signal.

In one embodiment of the present disclosure, the bias voltage generating module includes:

a first PMOS transistor, wherein the source electrode of the first PMOS transistor is connected with the first power supply, and the grid electrode and the drain electrode of the first PMOS transistor are both connected with the first node;

and the source electrode of the second PMOS transistor is connected with the first node, the grid electrode and the drain electrode of the second PMOS transistor are connected with a second node, the second node is electrically connected with a second power supply, and the voltage of the second power supply is lower than that of the first power supply.

In one embodiment of the present disclosure, the bias voltage generation module further includes a first resistance unit connected in series between the drain of the first PMOS transistor and the source of the second PMOS transistor, or connected in series between the second node and the second power supply.

In an embodiment of the disclosure, the bias current control module includes a third PMOS transistor, a source of the third PMOS transistor is connected to the first power supply, a gate of the third PMOS transistor is connected to the bias voltage generation module through the first node, and a drain of the third PMOS transistor is connected to the bias current control terminal of the level shift module.

In an embodiment of the present disclosure, the level shift circuit includes a plurality of level shift modules, the current bias module includes a bias voltage generation module and a plurality of bias current control modules, the plurality of bias current control modules are all connected to the same bias voltage generation module, and each bias current control module is respectively connected to a bias current control terminal of one level shift module.

In one embodiment of the present disclosure, the current bias module is implemented by a current source or a bandgap reference circuit.

In one embodiment of the present disclosure, the level conversion module includes:

the pull-up unit is connected with the current bias module through the bias current control end and is connected with the output end;

the inverting unit is connected with the input end, the second power supply and a third power supply and is used for generating and outputting an inverted signal of the input signal, and the voltage of the third power supply is the same as the high-level voltage of the input signal;

and the pull-down unit is connected with the pull-up unit, the second power supply, the input end, the phase inversion unit and the output end and is used for receiving the input signal and the phase inversion signal of the input signal output by the phase inversion unit.

In one embodiment of the present disclosure, a voltage of the third power supply is lower than a voltage of the first power supply, the voltage of the third power supply is higher than a voltage of the second power supply, and the voltage of the third power supply is the same as a high-level voltage of the input signal.

In one embodiment of the present disclosure, when the input signal is at a low level, the level shift module responds to an inverted signal of the input signal, and the pull-down unit pulls the output terminal voltage to a low level;

when the input signal is at a high level, the level conversion module responds to the input signal, and the pull-up unit pulls the voltage of the output end to a high level.

In one embodiment of the present disclosure, the pull-up unit includes:

a source electrode of the fourth PMOS transistor is connected with the bias current control end, a grid electrode of the fourth PMOS transistor is connected with the output end, and a drain electrode of the fourth PMOS transistor is connected with a third node;

and the source electrode of the fifth PMOS transistor is connected with the bias current control end, the grid electrode of the fifth PMOS transistor is connected with the third node, and the drain electrode of the fifth PMOS transistor is connected with the output end.

In one embodiment of the present disclosure, the pull-down unit includes:

a second NMOS transistor, wherein the drain electrode of the second NMOS transistor is connected with the third node, the grid electrode of the second NMOS transistor is connected with the input end, and the source electrode of the second NMOS transistor is electrically connected with the second power supply;

and the drain electrode of the third NMOS transistor is connected with the output end, the grid electrode of the third NMOS transistor is connected with the output port of the phase inversion unit, and the source electrode of the third NMOS transistor is electrically connected with the second power supply.

According to another aspect of the present disclosure, there is provided a chip including: such as the level shift circuit described above.

Embodiments of the present disclosure may/have at least the following advantages: compared with the existing level conversion circuit which directly connects the level conversion module to the first power supply, the constant bias current bias module can limit the pull-up current of the level conversion module under the influence of the constant bias current, so that the influence of the pull-up current of the level conversion module on the pull-down rate is reduced, the requirement on the pull-down voltage of the level conversion module is reduced, namely the requirement on the voltage value of an input signal of the level conversion circuit is reduced, the level conversion circuit can process the input signal with smaller voltage, the voltage application range of the input signal of the level conversion circuit is enlarged, and the effect of accelerating the output of level conversion is achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 illustrates a schematic diagram of a level shift circuit provided by an embodiment of the present disclosure;

fig. 2 is a schematic diagram of another level shift circuit provided in the embodiments of the present disclosure;

fig. 3 illustrates a circuit diagram of a current bias module provided by an embodiment of the present disclosure;

fig. 4A illustrates a circuit diagram of another current bias module provided by an embodiment of the present disclosure;

fig. 4B illustrates a circuit diagram of another current bias module provided by the embodiments of the present disclosure;

FIG. 5 is a schematic diagram of another level shift circuit provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another level shift circuit provided by an embodiment of the present disclosure;

fig. 7 illustrates a schematic diagram of a level shift module provided by an embodiment of the present disclosure;

fig. 8 illustrates a circuit diagram of a level shift module provided by an embodiment of the present disclosure;

fig. 9 is a timing diagram of the circuit shown in fig. 8.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The present exemplary embodiment will be described in detail below with reference to the drawings and examples.

Fig. 1 shows a schematic diagram of a level shift circuit provided in an embodiment of the present disclosure, and as shown in fig. 1, a level shift circuit 10 provided in an embodiment of the present disclosure includes:

the level conversion module 11 has an input terminal Vin, an output terminal Vout, and a bias current control terminal P0, and is configured to perform level conversion on an input signal received by the input terminal Vin under the control of the bias current Ic input by the bias current control terminal P0, and output the level-converted signal through the output terminal Vout;

the current bias module 12 is connected between the first power supply VDD1 and the bias current control terminal P0 of the level shift module 11, and is configured to provide the bias current Ic to the level shift module 11 to speed up the level shift output of the level shift module 11.

In this embodiment, the input terminal Vin may be connected to the output terminal of the first voltage domain, and is configured to receive an input signal different from the voltage of the first power VDD1, and the level conversion module 11 performs level conversion on the input signal received by the input terminal Vin, and outputs a signal with a high level equal to the voltage of the first power VDD1 after the level conversion through the output terminal Vout, so as to achieve the purpose of signal level conversion. For example, when the high level voltage of the first voltage domain of the input signal is lower than the voltage of the first power supply VDD1, level conversion of the lower voltage domain into the higher voltage domain may be achieved; alternatively, when the high level voltage of the first voltage domain of the input signal is higher than the voltage of the first power supply VDD1, level conversion of the higher voltage domain into the lower voltage domain may be achieved.

It should be noted that the input signal received by the input terminal Vin may include a high level portion and/or a low level portion as required, that is, the output terminal of the first voltage domain may input a signal with only a high level to the input terminal Vin, may also input a signal with only a low level to the input terminal Vin, may also input a signal with a high level to the input terminal Vin in a partial period, and may input a signal with a low level to the input terminal Vin in another partial period. As shown in fig. 9, the input signal may be a pulse signal having a high level and a low level, the high level of the pulse signal having a voltage different from that of the first power supply VDD 1.

The current bias module 12 is connected between the first power supply VDD1 and the level shift module 11, and can input the bias current Ic to the level shift module 11 through the current bias module 12 to limit the pull-up current of the level shift module 11, thereby reducing the influence of the pull-up current of the level shift module 11 on the pull-down rate, reducing the requirement on the pull-down voltage of the level shift module 11, and increasing the signal output speed of the level shift module 11.

The following describes a specific implementation of the current bias module 12.

Fig. 2 shows a schematic diagram of another level shift circuit provided in the embodiment of the present disclosure. As shown in fig. 2, in one embodiment, the current bias module 12 includes a bias voltage generating module 121 and a bias current control module 122, where the bias voltage generating module 121 is configured to output a bias voltage; the bias current control module 122 is connected to the bias voltage generating module 121, and is configured to generate the bias current Ic under the control of the bias voltage, and provide the bias current Ic to the level shifter module 11 through the bias current control terminal P0.

Fig. 3 shows a circuit diagram of a current bias module provided in an embodiment of the present disclosure.

As shown in fig. 3, in one embodiment, the bias voltage generating module 121 is connected to a first power VDD1 and provides a bias voltage V0 to the bias current control module 122 via a first node N1, and the bias current control module 122 is connected to the first power VDD1 and a bias current control terminal P0 of the level shift module 11.

In one embodiment, as shown in fig. 3, the bias voltage generating module 121 includes a first PMOS transistor MP1 and a first NMOS transistor MN1, the source of the first PMOS transistor MP1 is connected to the first power VDD1, and the gate and the drain are both connected to the first node N1; the first NMOS transistor MN1 has a drain connected to the first node N1, a gate for receiving the reference voltage VDDL, and a source connected to the second power supply GND, which may be a common negative voltage supply or a zero potential terminal, and has a voltage lower than the voltage of the first power supply VDD 1. The reference voltage VDDL may be provided by a reference voltage circuit or by a low-voltage domain voltage supply. In one embodiment, the reference voltage VDDL is lower than the voltage of the first power supply VDD1, the reference voltage VDDL is higher than the voltage of the second power supply GND, and the reference voltage VDDL is the same as the high-level voltage of the input signal to implement level conversion from the low-voltage domain to the high-voltage domain. For example, the reference voltage circuit providing the reference voltage VDDL may be a bandgap reference circuit providing a bandgap reference voltage.

In the embodiment shown in fig. 3, the first NMOS transistor MN1 is turned on under the control of the reference voltage VDDL, and the drain of the first NMOS transistor MN1 generates the reference current I0. Can be changed by adjusting the reference voltage VDDLThe magnitude of the reference current I0 is varied. When the reference voltage VDDL is constant, the reference current I0 is constant. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the drain current of the first PMOS transistor MP1 is the reference current I0 and is constant. The drain current of the first PMOS transistor MP1 is controlled by the gate-source voltage V of the first PMOS transistor MP1_gsp1It is determined that when the reference current I0 is constant, the gate-source voltage V of the first PMOS transistor MP1_gsp1The voltage difference between the first power supply VDD1 and the first node N1 is constant, and the voltage of the first node N1 is constant when the voltage of the first power supply VDD1 is not changed, and at this time, the voltage of the first node N1 is equal to the voltage of the first power supply VDD1 minus the gate-source voltage V of the first PMOS transistor MP1 operating at the drain current I0_gsp1Thereby causing the bias voltage generation module 121 to generate the constant bias voltage V0.

Fig. 4A illustrates a circuit diagram of another current bias module provided in an embodiment of the present disclosure.

As shown in fig. 4A, in another embodiment of the bias voltage generating module 121, the bias voltage generating module 121 includes a first PMOS transistor MP1 and a second PMOS transistor MP2, wherein a source of the first PMOS transistor MP1 is connected to a first power VDD1, and a gate and a drain of the first PMOS transistor MP1 are both connected to a first node N1; the source of the second PMOS transistor MP2 is connected to the first node N1, the gate and the drain are connected to the second node N2, the second node N2 is electrically connected to the second power source GND, and the voltage of the second power source GND is lower than the voltage of the first power source VDD 1.

The gate and drain of the second PMOS transistor MP2 of this embodiment are connected, i.e. the gate-source voltage V_gsp2Equal to gate-drain voltage V_dsp2Inevitably has V_dsp2＞V_gsp2-V_thp2When the second PMOS transistor MP2 is operated in the saturation region, the drain current of the second PMOS transistor MP2 is constant, i.e., the constant reference current I0 is generated. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, so the drain current of the first PMOS transistor MP1 is the reference current I0 and is constant. The drain current of the first PMOS transistor MP1 is controlled by the gate-source voltage V of the first PMOS transistor MP1_gsp1Determining that the first PMO is constant when the reference current I0 is constantGate-source voltage V of S transistor MP1_gsp1The voltage difference between the first power supply VDD1 and the first node N1 is constant, and the voltage of the first node N1 is constant when the voltage of the first power supply VDD1 is not changed, and at this time, the voltage of the first node N1 is equal to the voltage of the first power supply VDD1 minus the gate-source voltage V of the first PMOS transistor MP1 operating at the drain current of I0_gsp1Thereby causing the bias voltage generation module 121 to generate the constant bias voltage V0.

Fig. 4B illustrates a circuit diagram of another current bias module provided by the embodiment of the present disclosure.

It should be noted that, as shown in fig. 4B, in order to further adjust the magnitude of the reference current, the bias voltage generating module 121 further includes a first resistor unit R1. In one embodiment, the first resistance unit R1 may be connected in series between the second node N2 and the second power source GND or between the drain of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 to adjust the magnitude of the reference current I0.

The first resistor unit R1 may be implemented by a plurality of resistors connected in series or in parallel, or may be implemented by a plurality of self-biased transistors connected in series or in parallel, and the number of the resistors or the self-biased transistors may be determined according to the magnitude of the reference current I0 generated according to actual needs, which is not limited in this application.

For the implementation of the current mirror module 122, in an embodiment, as shown in fig. 3, 4A and 4B, the bias current control module 122 may include a third PMOS transistor MP3, a source of the third PMOS transistor MP3 is connected to the first power VDD1, a gate of the third PMOS transistor MP3 is connected to the bias voltage generation module 121 through the first node N1, and a drain of the third PMOS transistor MP3 is connected to the bias current control terminal P0, so as to generate a constant bias current Ic according to the bias voltage V0 and input the constant bias current Ic to the level conversion module 11.

In the embodiments shown in fig. 3, 4A and 4B, the gate-source voltage V of the third PMOS transistor MP3_gsp3And the gate-source voltage V of the first PMOS transistor MP1_gsp1Similarly, when the third PMOS transistor MP3 and the first PMOS transistor MP1 have the same parameters (e.g., the same device size, the same width-to-length ratio W/L), the third PMOS transistor MP3 and the first PMOS transistor MP1 have the same parametersThe drain current of the MP3 is the same as the reference current I0, so as to generate the bias current Ic according to the bias voltage V0; in addition, when the device size of the third PMOS transistor MP3 is proportional to the device size of the first PMOS transistor MP1, the drain current of the third PMOS transistor MP3 is also proportional to the reference current I0, so as to generate the fixed bias current Ic according to the bias voltage V0.

In an embodiment of the present disclosure, one or more resistor units may be connected in series to the drain of the third PMOS transistor MP3 to adjust the magnitude of the bias current, further stabilize or reduce the bias current (e.g., input a smaller bias current than the reference current I0 to the level shifter module 11). The resistor unit connected in series at the drain of the third PMOS transistor MP3 may be implemented by a plurality of resistors connected in series or in parallel, or implemented by a plurality of self-biased PMOS transistors connected in series or in parallel, and the number of the resistors or the self-biased PMOS transistors may be determined according to the magnitude of the bias current, which is not specifically limited in this application.

Fig. 5 is a schematic diagram of another level shift circuit provided in the embodiments of the present disclosure.

As shown in fig. 5, in some embodiments, the level shift circuit 50 may include a plurality of level shift modules 11, the current bias module 12 includes a bias voltage generation module 121 and a plurality of bias current control modules 122, the number of the level shift modules 11 is the same as the number of the bias current control modules 122, the plurality of bias current control modules 122 are all connected to the same bias voltage generation module 121, and each bias current control module 122 is respectively connected to the bias current control terminal P0 of one level shift module 11, so that the level shift speed of the plurality of level shift modules 11 is increased by one current bias module 12, so as to greatly reduce the circuit area of the level shift circuit 50. Meanwhile, the size of the bias current Ic generated by each bias current control module 122 can be correspondingly adjusted by adjusting the device size of the third PMOS transistor MP3 in each bias current control module 122 to meet the requirement of the level shift module 11, and the manner of adjusting each bias current control module 122 refers to the above embodiments, which is not described herein again.

In one embodiment, the embodiment shown in fig. 5 may be implemented by, on the basis of the embodiments shown in fig. 3 or fig. 4A or fig. 4B, connecting the gate of the third PMOS transistor MP3 of each bias current control module 122 to the first node N1, connecting the source of the third PMOS transistor MP3 of each bias current control module 122 to the first power VDD1, and connecting the drain of the third PMOS transistor MP3 of each bias current control module 122 to the bias current control terminal P0 of one level shift module 11, respectively.

It should be noted that, in addition to using the circuit composed of the bias voltage generating module 121 and the bias current control module 122 to generate the bias current, the current bias module 12 may also be implemented by other circuits that can achieve the same function, such as a current source or a bandgap reference circuit. For example, the current source may employ a mirror current source, a proportional current source, a micro current source, a current source of an emitter follower, a wilson current source, or the like to generate the bias current; the bandgap reference circuit may provide a bandgap reference current that is not affected by temperature, as implemented by a PTAT reference current source circuit.

In various current sources, a transistor in a circuit can be replaced by a triode (BJT), and a constant bias current Ic can also be generated. Taking a mirror current source as an example for explanation, in addition to generating the bias current by using the PMOS transistor in the embodiments of fig. 3 to 5, the PMOS transistor may be replaced by an element that can realize the function of generating the bias current, such as a PNP triode, and details are not repeated here.

Fig. 6 shows a schematic diagram of a level shift circuit in other embodiments of the present disclosure.

In other embodiments, as shown in fig. 6, the current bias module 12 may also be implemented by a second resistor unit R2 connected in series between the first power supply VDD1 and the bias current control terminal of the level shift module 11 to reduce the pull-up current of the level shift module 11. Specifically, the second resistance unit R2 may be implemented by a plurality of resistors connected in series or in parallel, or may be implemented by a plurality of self-biased PMOS transistors connected in series or in parallel, and for the number of resistors or self-biased PMOS transistors, the bias current is generated according to actual needs, which is not specifically limited in the present application.

An exemplary embodiment of the level shifting module 11 shown in fig. 1 is described below.

Fig. 7 is a schematic diagram of a level shift module according to an embodiment of the disclosure. Referring to fig. 7, in an exemplary embodiment of the present disclosure, the level shift module 11 includes a pull-up unit 111, an inverting unit 112, and a pull-down unit 113, wherein the pull-up unit 111 is connected to the current bias module 12 through a bias current control terminal P0, and is connected to the output terminal Vout; the inverting unit 112 is connected to the input terminal Vin, the second power GND and the third power VDD2, and is configured to generate and output an inverted signal of the input signal, and the voltage of the third power VDD2 is the same as the high level voltage of the input signal; the pull-down unit 113 is connected to the pull-up unit 111, the second power GND, the input terminal Vin, and the output terminal Vout, and receives an input signal of the input terminal Vin and an inverted signal of the input signal output by the inverting unit 112.

In this embodiment, the voltage of the third power supply VDD2 is lower than the voltage of the first power supply VDD1, the voltage of the third power supply VDD2 is higher than the voltage of the second power supply GND, and the voltage of the third power supply VDD2 is the same as the high-level voltage of the input signal. When the input signal is at a low level, the level shift module 11 responds to the inverted signal of the input signal, and the pull-down unit 113 pulls down the voltage of the output terminal Vout to a low level; when the input signal is at a high level, the level shift module 11 responds to the input signal, and the pull-up unit 111 pulls up the voltage at the output terminal Vout to a high level.

The pull-up unit 111 is connected to the first power supply VDD1 through the current bias module 12, and is configured to pull up the high level of the output signal to a voltage of the first power supply VDD1, for example, 2.8V to 5.0V. When the voltage of the first power supply VDD1 is high, the pull-up unit 111 may adopt a device with a high operating voltage, that is, it is ensured that the pull-up unit 111 can operate in the second voltage domain of [ GND, VDD1], so as to quickly pull up the high level of the output signal of the third node N3 or the output terminal Vout in the circuit to the voltage of the first power supply VDD 1.

Fig. 8 shows a circuit diagram of a level conversion module provided in an embodiment of the present disclosure.

As shown in fig. 8, in one embodiment, the pull-up unit 111 may include: a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5, wherein the source of the fourth PMOS transistor MP4 is connected to the bias current control terminal P0, the gate thereof is connected to the output terminal Vout, and the drain thereof is connected to the third node N3; the source of the fifth PMOS transistor MP5 is connected to the bias current control terminal P0, the gate is connected to the third node N3, and the drain is connected to the output terminal Vout.

The pull-down unit 113 is connected between the second power GND and the input terminal Vin, and the pull-down unit 113 is configured to pull down the low level of the output signal of the output terminal Vout to the voltage of the second power GND. In one embodiment, the high level voltage of the input signal of the input terminal Vin connected to the pull-down unit 113 may be less than the voltage of the first power supply VDD1, for example, the high level voltage of the input signal is 1.2V to 1.5V. When the high level voltage of the input signal at the input terminal Vin is smaller than the voltage of the first power supply VDD1, the pull-down unit 113 operates in the first voltage domain of [ GND, VDDL ], which is the same as the voltage domain of the input signal, so that the pull-down unit 113 may employ a device having a low operating voltage, thereby quickly pulling down the low level of the output signal at the output terminal Vout or the third node N3 in the circuit to the voltage of the second power supply GND.

With continued reference to fig. 8, in one embodiment, the pull-down unit 113 may include a second NMOS transistor MN2 and a third NMOS transistor MN3, wherein the drain of the second NMOS transistor MN2 is connected to the third node N3, the gate is connected to the input terminal Vin, and the source is electrically connected to the second power GND; the third NMOS transistor MN3 has a drain connected to the output terminal Vout, a gate connected to the output port of the inverting unit 112 to receive the inverted signal of the input signal, and a source electrically connected to the second power source GND. That is, the second NMOS transistor MN2 is controlled by the input signal of the input terminal Vin, and the third NMOS transistor MN3 is controlled by the inverted signal of the input terminal Vin, so that the output terminal Vout performs the conversion of two output levels.

As shown in fig. 8, the inverting unit 112 includes an odd number of inverters INV0, an input port of the first inverter INV0 is connected to the input terminal Vin, an output port of the last inverter INV0 is connected to the output terminal Vout, an input port of the middle inverter INV0 is connected to an output port of the previous inverter INV0, and an output port of the middle inverter INV0 is connected to an input port of the next inverter INV 0. In fig. 8, the inverting unit 112 is provided with an inverter INV0, an input port of the inverter INV0 is connected to the input terminal Vin, an output port of the inverter INV0 is connected to the gate of the third NMOS transistor MN3, and the inverter INV0 is connected between the third power supply VDD2 and the second power supply GND.

It should be noted that the output end of the first voltage domain inputs a high level signal to the gates of the two NMOS transistors of the pull-down unit 113 and a low level signal obtained by inverting the high level signal through the inverting unit 112, respectively, or inputs a low level signal to the gates of the two NMOS transistors of the pull-down unit 113 and a high level signal obtained by inverting the low level signal through the inverting unit 112, respectively, in a certain period of time, so as to control the two NMOS transistors of the pull-down unit 113 in the level shifter module 11.

Fig. 9 is a timing diagram of the circuit shown in fig. 8.

In this embodiment, an example in which the input signal is a pulse signal having a high level and a low level is described. As shown in fig. 9, when the input signal at the input terminal Vin is at a low level, the second NMOS transistor MN2 is turned off, the third NMOS transistor MN3 is turned on under the control of the inverted signal of the input signal, at this time, the output signal at the output terminal Vout is pulled down to the second power GND, the output terminal Vout outputs a low level, the fourth PMOS transistor MP4 is turned on, the third node N3 is pulled to a high level, and the fifth PMOS transistor MP5 is turned off.

When the input signal at the input terminal Vin changes from low level to high level, the second NMOS transistor MN2 turns on gradually from off, the potential of the third node N3 drops, and the fifth PMOS transistor MP5 turns on gradually. Since the third NMOS transistor MN3 is gradually turned off, the potential of the output terminal Vout is gradually pulled up to a high level by the fifth PMOS transistor MP 5. In this process, the current I1 in the fourth PMOS transistor MP4 gradually decreases from Ic to 0, and the current I2 in the fifth PMOS transistor MP5 gradually increases from 0 and then gradually decreases to 0. When the input signal at the input terminal Vin is greater than the turn-on voltage of the second NMOS transistor MN2, the second NMOS transistor MN2 is turned from off to on, so that the third node N3 is pulled down to a low level, the fifth PMOS transistor MP5 is turned on, the third NMOS transistor MN3 is turned from on to off, and the output signal at the output terminal Vout is pulled up to a high level. The second NMOS transistor MN2 and the fourth PMOS transistor MP4 are connected in series, and the current in the second NMOS transistor MN2 gradually increases and then gradually decreases to 0; the third NMOS transistor MN3 and the fifth PMOS transistor MP5 are connected in series, and the current in the third NMOS transistor MN3 gradually decreases from Ic to 0. Due to the small bias current Ic, the second NMOS transistor MN2 can be pulled to a lower voltage lower than the first power supply VDD1 by the bias current control terminal P0 under the condition of a small gate-on voltage (i.e., a small input signal high-level voltage), so as to quickly pull the third node N3 to a low level, and further quickly pull the output terminal Vout voltage to a high level by the fifth PMOS transistor MP5, thereby increasing the high-level output speed of the output signal.

When the input signal at the input terminal Vin changes from high level to low level again, the current I1 in the fourth PMOS transistor MP4 gradually increases, the current I2 in the fifth PMOS transistor MP5 gradually decreases from Ic to 0, and since the bias current Ic is small, when the inverted signal of the input signal at the input terminal Vin is greater than the turn-on voltage of the third NMOS transistor MN3, the third NMOS transistor MN3 changes from off to on under the control of the inverted signal of the input signal, and the third NMOS transistor MN3 can pull the bias current control terminal P0 to a lower voltage lower than the first power supply VDD1 under the condition of a small gate turn-on voltage (i.e., the high level voltage of the input signal is small), so as to quickly pull the voltage at the output terminal Vout to low level, thereby improving the low level output speed of the output signal.

It can be seen that by reducing the highest current when the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are turned on, and reducing the influence of a larger pull-up current on the pull-down rate, the requirements on the pull-down capability of the second NMOS transistor MN2 and the third NMOS transistor MN3 can be reduced, that is, the requirements on the gate turn-on voltages of the second NMOS transistor MN2 and the third NMOS transistor MN3 are reduced, so that the level shifter circuit can process a smaller input signal, the effect of fast voltage transition can be achieved for controlling an input signal in a wider range, the voltage application range of the input signal of the level shifter circuit is increased, and the effect of level shift output is accelerated.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

The embodiment of the disclosure also provides a chip, which includes the level conversion circuit. Compared with the existing level conversion circuit which directly connects the level conversion module to the first power supply, the level conversion circuit can limit the pull-up current of the level conversion module under the influence of the constant bias current, so that the influence of the pull-up current of the level conversion module on the pull-down rate is reduced, the requirement on the pull-down voltage of the level conversion module is reduced, namely the requirement on the voltage value of an input signal of the level conversion circuit is reduced, the level conversion circuit can process the input signal with smaller voltage, the voltage application range of the input signal of the level conversion circuit is enlarged, and the effect of accelerating the output of level conversion is achieved.

For the chip embodiment, since it includes the level shift circuit, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the level shift circuit embodiment. Compared with the existing level conversion circuit which directly connects the level conversion module to the first power supply, the chip disclosed by the invention can limit the pull-up current of the level conversion module under the influence of the constant bias current, further reduce the influence of larger pull-up current of the level conversion module on the pull-down rate, reduce the requirement on the pull-down voltage of the level conversion module, namely reduce the requirement on the voltage value of an input signal of the level conversion circuit, enable the level conversion circuit to process the input signal with smaller voltage, enlarge the voltage application range of the input signal of the level conversion circuit and achieve the effect of accelerating the output of level conversion.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The above detailed description is made on the level shift circuit and the chip provided by the present invention, and the principle and the implementation of the present invention are explained by applying a specific example, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (16)

1. A level shift circuit, comprising:

the level conversion module is provided with an input end, an output end and a bias current control end and is used for carrying out level conversion on an input signal received by the input end under the control of the bias current input by the bias current control end and outputting a signal after the level conversion through the output end;

and the current bias module is connected between a first power supply and the bias current control end of the level conversion module and used for providing the bias current for the level conversion module so as to accelerate the level conversion output of the level conversion module.

2. The level shift circuit of claim 1, wherein the current bias module comprises:

the bias voltage generating module is used for outputting bias voltage;

and the bias current control module is connected with the bias voltage generation module and used for generating the bias current under the control of the bias voltage and providing the bias current to the level conversion module through the bias current control end.

3. The circuit of claim 2, wherein the bias voltage generating module is coupled to the first power supply and provides the bias voltage to the bias current control module via a first node, and the bias current control module is coupled to the first power supply and a bias current control terminal of the level shifter module.

4. The circuit of claim 3, wherein the bias voltage generating module comprises:

a first PMOS transistor, wherein the source electrode of the first PMOS transistor is connected with the first power supply, and the grid electrode and the drain electrode of the first PMOS transistor are both connected with the first node;

the drain electrode of the first NMOS transistor is connected with the first node, the grid electrode of the first NMOS transistor is used for receiving reference voltage, the source electrode of the first NMOS transistor is connected with a second power supply, and the voltage of the second power supply is lower than that of the first power supply.

5. The circuit of claim 4, wherein the reference voltage is lower than a voltage of the first power supply, wherein the reference voltage is higher than a voltage of the second power supply, and wherein the reference voltage is the same as a high level voltage of the input signal.

6. The circuit of claim 3, wherein the bias voltage generating module comprises:

a first PMOS transistor, wherein the source electrode of the first PMOS transistor is connected with the first power supply, and the grid electrode and the drain electrode of the first PMOS transistor are both connected with the first node;

and the source electrode of the second PMOS transistor is connected with the first node, the grid electrode and the drain electrode of the second PMOS transistor are connected with a second node, the second node is electrically connected with a second power supply, and the voltage of the second power supply is lower than that of the first power supply.

7. The circuit of claim 6, wherein the bias voltage generating module further comprises a first resistor unit connected in series between the drain of the first PMOS transistor and the source of the second PMOS transistor, or connected in series between the second node and the second power supply.

8. The circuit of claim 3, wherein the bias current control module comprises a third PMOS transistor, a source of the third PMOS transistor is connected to the first power supply, a gate of the third PMOS transistor is connected to the bias voltage generation module through the first node, and a drain of the third PMOS transistor is connected to the bias current control terminal of the level shift module.

9. The circuit according to claim 2, wherein the level shift circuit comprises a plurality of level shift modules, the current bias module comprises a bias voltage generation module and a plurality of bias current control modules, the plurality of bias current control modules are connected to the same bias voltage generation module, and each bias current control module is connected to a bias current control terminal of one of the level shift modules.

10. The circuit of claim 1, wherein the current bias module is implemented by a current source or a bandgap reference circuit.

11. The level shift circuit of claim 1, wherein the level shift module comprises:

the pull-up unit is connected with the current bias module through the bias current control end and is connected with the output end;

the inverting unit is connected with the input end, the second power supply and a third power supply and used for generating and outputting an inverted signal of the input signal, and the voltage of the third power supply is the same as the high-level voltage of the input signal;

and the pull-down unit is connected with the pull-up unit, the second power supply, the input end, the phase inversion unit and the output end and is used for receiving the input signal and the phase inversion signal of the input signal output by the phase inversion unit.

12. The level shift circuit of claim 11,

the voltage of the third power supply is lower than the voltage of the first power supply, the voltage of the third power supply is higher than the voltage of the second power supply, and the voltage of the third power supply is the same as the high-level voltage of the input signal.

13. The level shift circuit of claim 12,

when the input signal is at a low level, the level conversion module responds to an inverted signal of the input signal, and the pull-down unit pulls the voltage of an output end to the low level;

when the input signal is at a high level, the level conversion module responds to the input signal, and the pull-up unit pulls the voltage at the output end to the high level.

14. The circuit of claim 11, wherein the pull-up unit comprises:

a fourth PMOS transistor, wherein a source electrode of the fourth PMOS transistor is connected with the bias current control end, a grid electrode of the fourth PMOS transistor is connected with the output end, and a drain electrode of the fourth PMOS transistor is connected with a third node;

and the source electrode of the fifth PMOS transistor is connected with the bias current control end, the grid electrode of the fifth PMOS transistor is connected with the third node, and the drain electrode of the fifth PMOS transistor is connected with the output end.

15. The level shift circuit of claim 14, wherein the pull-down unit comprises:

a second NMOS transistor, wherein the drain electrode of the second NMOS transistor is connected with the third node, the grid electrode of the second NMOS transistor is connected with the input end, and the source electrode of the second NMOS transistor is electrically connected with the second power supply;

and the drain electrode of the third NMOS transistor is connected with the output end, the grid electrode of the third NMOS transistor is connected with the output port of the phase inversion unit, and the source electrode of the third NMOS transistor is electrically connected with the second power supply.

16. A chip comprising a level shifting circuit as claimed in any one of claims 1 to 15.

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