TWM643260U - High performance level shifting circuit - Google Patents

Abstract

This creation proposes a high-efficiency potential converter circuit, which is composed of an input circuit (1), a latch circuit (2), an output control transistor (3) and an output control transistor (4), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store the converted output potential; the output control transistor (3) is used to pull down the potential of the first node ( N1 ); the output control transistor ( 4 ) is used to pull down the potential of the second node ( N2 ) .

The high-efficiency potential converter circuit proposed in this invention can not only quickly convert the first signal into a second signal, but also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

Description

High-efficiency potential shifter circuit

This creation proposes a high-efficiency potential converter circuit, which is composed of an input circuit (1), a latch circuit (2), an output control transistor (3) and an output control transistor (4), in order to quickly obtain accurate voltage level conversion and effectively reduce the power consumption of the electronic circuit.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC for short). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor, P channel metal oxide semiconductor) transistor (MP1), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN 2) and an inverter (INV) to form a potential converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the level shifter is in a stable state, no static current is generated in the latch type level shifter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down (pull down) and the first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up (pull up) to turn off the second PMOS transistor (MP2); moreover, when the first NMOS transistor (MN 1) When the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up and the first PMOS transistor (MP1) is turned off. Therefore, there will not be a current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-mentioned conventional level converter has a negative effect on the pull-up and pull-up of the potential on the output terminal (OUT) when the second PMOS transistor (MP2) tends to be turned on (or turned off) and when the second NMOS transistor (MN2) is tended to be turned off (or turned on). There is a phenomenon of contention between the voltages and voltages, so the second signal (V(OUT)) is slower when it transitions to a low voltage level. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that the second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V(IN)) during the conversion period may not make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1) and the second NMOS transistor (MN2) fully turned on or completely turned off, which will cause a static current between the first high potential voltage (VDDH) and the ground (GND). increased power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high potential voltage (VDDH), because the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are the first high potential voltage (VDDH), while the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type level shifter can operate normally is limited.

Figure 2 shows another prior art mirror-type potential shifter circuit. The potential shifter connects the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) together and to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The first PMOS transistor (MP1) is in a saturation region. And its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror-type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the performance of the potential converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of the fact that the potentials of the latch-type potential converters compete with each other on their output terminals, the main purpose of this invention is to propose a high-performance potential converter circuit, which can not only convert the first signal into a second signal accurately and quickly, but also effectively reduce power consumption.

This creation proposes a high-efficiency potential converter circuit, which is composed of an input circuit (1), a latch circuit (2), an output control transistor (3) and an output control transistor (4), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store the converted output potential; the output control transistor (3) is used to pull down the potential of the first node (N1); the output control transistor (4) is used to The potential of the second node (N2) is pulled down.

The simulation results prove that the high-efficiency potential converter circuit proposed by this invention can not only convert the first signal into a second signal accurately and quickly, but also has multiple functions such as simple circuit structure and favorable device miniaturization. At the same time, it can also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

1: Input circuit

2: Latch circuit

3: Output control transistor

4: Output control transistor

N1: the first node

N2: second node

N3: the third node

N4: the fourth node

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

I1: the first inverter

MN1: the first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

MN4: The fourth NMOS transistor

GND: ground

IN: the first input terminal

V(IN): the first signal

OUT: output terminal

V(OUT): the second signal

OUTB: Inverted output terminal

INB: the second input terminal

VDDH: the first high power supply voltage

VDDL: The second highest power supply voltage

Fig. 1 shows the circuit diagram of the potential converter in the first prior art; Fig. 2 shows the circuit diagram of the potential converter in the second prior art; Fig. 3 shows the circuit diagram of the high-efficiency potential converter circuit of the preferred embodiment of the present invention;

According to the above-mentioned purpose, this creation proposes a high-efficiency potential converter circuit, as shown in Figure 3, which is composed of an input circuit (1), a latch circuit (2), an output control transistor (3) and an output control transistor (4), wherein the input circuit (1) is used to provide differential input signals; the latch circuit (2) is used to store the converted output potential; the output control transistor (3) is used to pull down the potential of the first node (N1); the output control transistor (4) is Used to pull down the potential of the second node (N2); the input circuit (1) is coupled to the first input terminal (IN) to provide a differential input signal; it is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to The third node (N3); the source connection of the second NMOS transistor (MN2) to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)) and provide an inverted signal of the first signal (V(IN)); the latch circuit (2) is coupled to the first high power supply voltage (VDDH) and an input circuit (1), used as a storage switch Output potential; it is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the source of the fourth PMOS transistor (MP4) is connected to the second node (N2), and its gate is connected to The second input terminal (INB), and its drain is connected to the fourth node (N4); the output control transistor (3) is composed of a third NMOS transistor (MN3), its source is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the output control transistor (4) is composed of a fourth NMOS transistor (MN4), and its source is connected to the ground (G ND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first high power supply voltage (VDDH) is used to provide the first high power required by the high-performance potential converter circuit Voltage, the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the high-performance potential converter circuit, the level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH), the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the The second high power supply voltage (VDDL) is 1.2V, the first signal (V(IN)) is a rectangular wave between 0V and 1.2V, and the second signal (V(OUT)) is a corresponding waveform between 0V and 1.8V.

Please refer to FIG. 3 again, and now consider the steady-state operation of the high-efficiency potential shifter circuit when the first signal (V(IN)) is at a logic low level (0 volts): the logic low level on the first input terminal (IN) is simultaneously transmitted to the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), the gate of the third PMOS transistor (MP3) and the input terminal of a first inverter (I1), so that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both off (OFF), the third PMOS transistor (MP3) is turned on (ON), and the first inverter (I1) transmits a logic high level (VDDL) to the gate of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4) and the gate of the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) and the fourth All NMOS transistors (MN4) are turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). At this time, because the fourth NMOS transistor (MN4) is turned on, the fourth PMOS transistor (MP4) is turned off (OFF), and the potential of the second node (N2) will be pulled down to a logic low level (0 volts) and output from the output terminal (OUT). Since the fourth PMOS transistor (MP4) is turned off, the second NMOS transistor (MN2) conduction (ON), the potential of the fourth node (N4) will be pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) makes the first PMOS transistor (MP1) conduction (ON), at this time due to the first PMOS transistor (MP1) Turning on (ON), the potential of the first node (N1) will be pulled up to a logic high level and output by the inverting output terminal (OUTB). Since the third PMOS transistor (MP3) is also turned on, and the first NMOS transistor (MN1) is turned off (OFF), therefore, the potential of the third node (N3) will be pulled up to a logic high level. The logic high level of the third node (N3) makes the second PMOS transistor ( MP2) off, because the second Both the PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned off, and the fourth NMOS transistor (MN4) is turned on. Therefore, the potential of the second node (N2) will be maintained at a logic low level (0 volts), that is, the potential of the output terminal (OUT) will be maintained at a steady state value of a logic low level (0 volts). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by a high-efficiency potential shifter circuit, and output from the output terminal (OUT).

Considering again when the first signal (V(IN)) is a logic high level (VDDL), the steady-state operation situation of the high-efficiency potential shifter circuit: the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (M N1) and the third NMOS transistor (MN3) are both turned on (ON), and the third PMOS transistor (MP3) is turned off (OFF). At this time, because the third NMOS transistor (MN3) is turned on, the potential of the first node (N1) will be pulled down to a logic low level (0 volts) and output from the inverting output terminal (OUTB). Low level (0 volts), the logic low level on the third node (N3) makes the second PMOS transistor (MP2) conduction, and the first inverter (I1) transmits logic low level to the gate of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4) and the gate of the fourth PMOS transistor (MP4), so that the second NMOS transistor Both the crystal (MN2) and the fourth NMOS transistor (MN4) are turned off (OFF), and the fourth PMOS transistor (MP4) is turned on (ON). At this time, since the second PMOS transistor (MP2) is turned on (ON), and the fourth NMOS transistor (MN4) is turned off (OFF), the potential of the second node (N2) will be pulled up to a logic high level and output from the output terminal (OUT), because the fourth PMOS transistor (MP4) is also turned on (ON), therefore, the potential of the fourth node (N4) will be pulled up to a logic high level, and the logic high level of the fourth node (N4) will cause the first PMOS transistor (MP1) to be turned off. At this time, because the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned off, and the first NMOS transistor (MN1) is turned on, the potential of the third node (N3) will be maintained at a logic low level (0 volts). Both the OS transistor ( MP2 ) and the fourth PMOS transistor ( MP4 ) are turned on, and the second NMOS transistor ( MN2 ) is turned off. Therefore, the potential of the output terminal ( OUT ) will maintain a steady state value of a logic high level. In other words, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by a high-efficiency potential shifter circuit, and is output from the output terminal (OUT).

In summary, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and when the first signal (V(IN)) is at a logic high level (VDDL), the second signal (V(OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The high-efficiency potential shifter circuit proposed in this creation can be verified by the Spice transient analysis simulation results. It can not only quickly and accurately convert the first signal to a second signal, but also effectively reduce the competition between the pull-up path and the pull-down path of the output terminal (OUT), thereby reducing power loss.

While this creation specifically discloses and describes selected best practice For example, those who are familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of the creation. Therefore, all changes in the relevant technical categories are included in the patent application scope of this creation.

1: Input circuit

2: Latch circuit

3: Output control transistor

4: Output control transistor

N1: the first node

N2: second node

N3: the third node

N4: the fourth node

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

I1: the first inverter

MN1: the first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

MN4: The fourth NMOS transistor

GND: ground

IN: the first input terminal

V(IN): the first signal

OUT: output terminal

V(OUT): the second signal

OUTB: Inverted output terminal

INB: the second input terminal

VDDH: the first high power supply voltage

VDDL: The second highest power supply voltage

Claims (8)

A high-efficiency potential converter circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for connecting a drain of a first PMOS transistor (MP1), a source of a third PMOS transistor (MP3) and a drain of a third NMOS transistor (MN3); a second node (N2) for connecting a drain of a second PMOS transistor (MP2) to a fourth PMOS transistor The source of the crystal (MP4) and the drain of a fourth NMOS transistor (MN4) are connected together; a third node (N3) is used to connect the gate of the second PMOS transistor (MP2), the drain of the third PMOS transistor (MP3) and the drain of a first NMOS transistor (MN1); a fourth node (N4) is used for connecting the gate of the first PMOS transistor (MP1), the drain of the fourth PMOS transistor (MP4) and a second The drains of the NMOS transistors (MN2) are connected together; a first input terminal (IN), coupled to the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), the gate of the third PMOS transistor (MP3) and an input terminal of a first inverter (I1), for providing a first signal (V(IN)); a second input terminal (INB), coupled to the second NMOS transistor (MN2) The gate of the fourth NMOS transistor (MN4), the gate of the fourth PMOS transistor (MP4) and the output terminal of the first inverter (I1) are used to provide an inversion signal (V(INB)) of the first signal (V(IN)); An output terminal (OUT), coupled to the second node (N2), for outputting the second signal (V(OUT)); an inverting output terminal (OUTB), coupled to the first node (N1), for outputting an inverse signal of the second signal (V(OUT)); a first high power supply voltage (VDDH), coupled to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), for providing the first high power required by the potential converter circuit Voltage; a second high power supply voltage (VDDL), coupled to the source of the first inverter (I1), in order to provide the second high power supply voltage required by the potential converter circuit, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH); an input circuit (1), coupled to the first input terminal (IN), for providing differential input signals; a latch circuit (2), coupled to the first high power supply voltage (VDDH) and an input The circuit (1) is used to store the converted output potential; an output control transistor (3) is coupled to the first input terminal (IN) to pull down the potential of the first node (N1); and an output control transistor (4) is coupled to the second input terminal (INB) to pull down the potential of the second node (N2). As the high-efficiency potential converter circuit described in item 1 of the scope of patent application, wherein the input circuit (1) includes: a first NMOS transistor (MN1), its source is connected to the ground (GND), and its gate is connected to connected to the first input terminal (IN), and its drain is connected to the third node (N3); a second NMOS transistor (MN2), its source connected to the ground (GND), its gate connected to the second input terminal (INB), and its drain connected to the fourth node (N4); and a first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal ( V(IN)) Inverted signal. As the high-efficiency potential converter circuit described in item 2 of the scope of patent application, wherein the latch circuit (2) includes: a first PMOS transistor (MP1), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the fourth node (N4), and whose drain is connected to the first node (N1); a second PMOS transistor (MP2), whose source is connected to the first high power supply voltage (VDDH), and whose gate is connected to the third node (N3) , and its drain is connected to the second node (N2); a third PMOS transistor (MP3), its source is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); and a fourth PMOS transistor (MP4), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4) connect. As the high-efficiency potential converter circuit described in item 3 of the scope of patent application, wherein the output control transistor (3) is composed of a third NMOS transistor (MN3), its source is connected to Ground (GND), the gate of which is connected to the first input terminal (IN), and the drain of which is connected to the first node (N1). The high-efficiency potential shifter circuit described in item 4 of the scope of the patent application, wherein the output control transistor (4) is composed of a fourth NMOS transistor (MN4), its source is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2). The high-efficiency potential shifter circuit as described in claim 1 of the patent application, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The high-efficiency potential shifter circuit as described in claim 6 of the patent application, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The high-efficiency potential shifter circuit as described in claim 2 of the patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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