TWM628475U - Low power and high performance voltage level converting circuit - Google Patents

Abstract

The present invention proposes a low power consumption high performance potential conversion circuit, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), wherein the latch circuit (1) is used to save the converted output potential and control leakage current; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the potential conversion circuit Differential input signal.

The low power consumption and high performance potential conversion circuit proposed in this work can not only accurately convert the first signal into a second signal, but also can effectively reduce leakage current, thereby reducing power consumption.

Description

Low-power high-performance potential conversion circuit

The present invention relates to a low-power-consumption high-performance potential conversion circuit, especially a latch circuit (1), an output control circuit (2) and an input circuit (3), in order to obtain accurate voltage level conversion And effectively reduce the power consumption of electronic circuits.

A potential conversion circuit is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential conversion circuit is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a prior art latch-type potential conversion circuit, which uses a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1), a A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) ) to form a potential conversion circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the first signal (V(IN)) is also at the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, in the same During the time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential conversion circuit is in a stable state, the latch type There is no static current generated in the potential conversion circuit. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential conversion circuit, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the output terminal The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention with each other, so the second signal (V(OUT)) is slower when it transitions to a logic low level. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a logic low level, The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS electrical The crystal ( MN1 ) and the second NMOS transistor ( MN2 ) are completely turned on or turned off, which will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND). Current increases power loss.

Furthermore, the performance of the latch-type potential conversion circuit is affected by the first high potential voltage (VDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type potential conversion circuit can operate normally is limited.

FIG. 2 shows another prior art mirror-type potential conversion circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and to The drain of the first PMOS transistor (MP1) makes the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in the saturation region, and its The gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential conversion circuit is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the potential conversion The performance of the circuit will not change much either. Therefore, the mirror-type potential conversion circuit can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a voltage is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1). a quiescent current path.

In view of this, the main purpose of this creation is to propose a low-power high-performance potential conversion circuit, which can not only accurately and quickly convert a first signal into a second signal, but also can effectively reduce leakage current, thereby reducing power consume.

The present invention proposes a low power consumption high performance potential conversion circuit, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), wherein the latch circuit (1) is used to save the converted output potential and control leakage current; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the potential conversion circuit Differential input signal.

It is confirmed by the simulation results that the low power consumption and high performance potential conversion circuit proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is conducive to the miniaturization of the device, etc. Multiple functions, while also effectively reducing power consumption.

1: Latch circuit

2: Output control circuit

3: Input circuit

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

I1: first inverter

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: sixth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

OUT: output terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Figure 1 shows the circuit diagram of the potential conversion circuit in the first prior art; Figure 2 shows the circuit diagram of the potential conversion circuit in the second prior art; Figure 3 shows the low power consumption and high performance potential of the preferred embodiment of the present invention The circuit diagram of the conversion circuit; Fig. 4 shows the timing diagram of transient analysis of the first signal and the second signal in the preferred embodiment of the present invention.

According to the above purpose, the present invention proposes a low-power high-performance potential conversion circuit, as shown in FIG. 3, which consists of a latch circuit (1), an output control circuit (2) and an input circuit (3) The latch circuit (1) is used to save the converted output potential and control the leakage current; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the differential input signal of the potential conversion circuit; the latch circuit (1) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor transistor (MN1), a second NMOS transistor (MN2), a fifth PMOS transistor (MP5) and a sixth PMOS transistor (MP6), wherein the first PMOS transistor (MP1) The source is connected to the first high power supply voltage (VDDH), the gate is connected to the fourth node (N4), and the drain is connected to the first node (N1); the second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the The source of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), the gate is connected to the fourth node (N4), and the drain is connected to the third node ( N3) is connected; the source of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4), its gate is connected to the third node (N3), and its drain is is connected to the fourth node (N4); the source of the fifth PMOS transistor (MP5) is connected to the first node (N1), the gate is connected to the first input terminal (IN), and the drain is The pole is connected to the third node (N3); the source of the sixth PMOS transistor (MP6) is connected to the second node (N2), the gate is connected to the second input terminal (INB), and Its drain is connected to the fourth node (N4); the output The control circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the third PMOS transistor (MP3) is connected to the first high power supply Supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to The gate of the first high power supply voltage (VDDH) is connected to the second input terminal (INB), and the drain is connected to the second node (N2); the input circuit (3) is composed of a A third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1) are formed, wherein the source of the third NMOS transistor (MN3) is connected to the ground (GND). ), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); the source of the fourth NMOS transistor (MN4) is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); the first inverter (I1) coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal inverse to the first signal (V(IN)); the first high power supply The supply voltage (VDDH) is used to provide the first high potential voltage required by the potential conversion circuit; and the second high power supply voltage (VDDL) is used to provide the second high potential voltage required by the potential conversion circuit, The potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage ( VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is between 0 volts and 1.8 volts corresponding waveform.

Please refer to Figure 3 again to explain the working principle of Figure 3 as follows: Now consider the steady state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic low level (0 volts): the logic low level on the first input terminal (IN) is simultaneously transmitted to the first inverter the input terminal of the device (I1), the third NMOS transistor (MN3), the fifth PMOS transistor (MP5) and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3 ) is turned off (OFF), and the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned on (ON), at this time, the potential of the third node (N3) is pulled up to a level close to the first The high potential of a high potential voltage (VDDH), the high potential of the third node (N3) makes the second PMOS transistor (MP2) off and the second NMOS transistor (MN2) on; and the first inversion The device (I1) transmits a second high potential voltage (VDDL) to the gates of the fourth NMOS transistor (MN4), the sixth PMOS transistor (MP6) and the fourth PMOS transistor (MP4), so that the first The four NMOS transistors (MN4) are turned on (ON), and the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned off (OFF). At this time, due to the second NMOS transistor (MN2) ) and the fourth NMOS transistor (MN4) are all turned on, the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are all turned off (OFF), so , the potential of the fourth node (N4) will be pulled down to a logic low level (0 volts), and the low potential of the fourth node (N4) makes the first PMOS transistor (MP1) turn on (ON), The first NMOS transistor (MN1) is turned off (OFF). At this time, since the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are all turned on ( ON), and the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off (OFF), therefore, the potential of the third node (N3) is maintained at a logic high level, and the The potential of the fourth node (N4) maintains a steady state value of a logic low level (0 volt). Qualitatively speaking, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through the potential conversion circuit, and is sent from the output terminal. (OUT) output.

Then consider the steady-state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic high level (1.2 volts): the logic high level on the first input terminal (IN) is simultaneously transmitted to the first inverter the input terminal of the device (I1), the third NMOS transistor (MN3), the fifth PMOS transistor (MP5) and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3 ) is turned on (ON), and the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned off (OFF); and the first inverter (I1) transmits a low level (0 volts) to the gates of the fourth NMOS transistor (MN4), the sixth PMOS transistor (MP6), and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4) is turned OFF, and The fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned on (ON). At this time, since the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned on (ON), and the fourth NMOS transistor (MN4) is turned off (OFF), therefore, the potential of the fourth node (N4) will be pulled to a logic high level, and furthermore, the fourth node (N4) The high potential is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first PMOS transistor (MP1) is turned off (OFF), the first NMOS transistor ( MN1) is turned on (ON), at this time, since the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on (ON), the first PMOS transistor (MP1), the third Both the PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are turned off (OFF), therefore, the potential of the third node (N3) will be pulled down to a logic low level (0 volt), and further, The low potential of the third node (N3) is transmitted to the second PMOS transistor (MP2) and the gate of the second NMOS transistor (MN2), so that the second PMOS transistor (MP2) is turned on (ON), The second NMOS transistor (MN2) is turned off (OFF). At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, the second PMOS transistor (MP2), the Both the four PMOS transistors ( MP4 ) and the sixth PMOS transistor ( MP6 ) are turned on (ON), therefore, the potential of the fourth node ( N4 ) is maintained at a steady state value of a logic high level. In short, when the first signal (V(IN)) is at a logic high level (1.2 volts), it is converted into a second signal with a high level (VDDH) through a potential conversion circuit, and is output from the output terminal (OUT).

To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal (V( When IN)) is the second high potential voltage (1.2 volts), the second signal (V(OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

The simulation results of Spice transient analysis of the low-power high-performance potential conversion circuit proposed in this work are shown in Figure 4. The simulation results can confirm that the low-power high-performance potential conversion circuit proposed in this work has Not only can the first signal be converted into a second signal quickly and accurately, but also the power consumption can be effectively reduced.

Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included within the scope of the patent application of this creation.

1: Latch circuit

2: Output control circuit

3: Input circuit

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

I1: first inverter

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: sixth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

OUT: output terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A low power consumption high performance potential conversion circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for converting a first signal (V(IN)) into a second signal (V(OUT)) The drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the source of a fifth PMOS transistor (MP5) are connected together; a second node (N2), For connecting the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the source of a sixth PMOS transistor (MP6) together; a third node ( N3), used for the drain of the fifth PMOS transistor (MP5), the drain of a first NMOS transistor (MN1), the gate of the second PMOS transistor (MP2) and a second NMOS transistor The gates of the crystals (MN2) are connected together; a fourth node (N4) is used for the drain of the sixth PMOS transistor (MP6), the drain of a second NMOS transistor (MN2), and the drain of the sixth PMOS transistor (MP6). The gate of a PMOS transistor (MP1) and the gate of the first NMOS transistor (MN1) are connected together; a first input terminal (IN) is coupled to the third PMOS transistor (MP3), the A fifth PMOS transistor (MP5) and a gate of a third NMOS transistor (MN3) are used to provide a first signal (V(IN)); a second input terminal (INB) is coupled to the first signal The gates of four PMOS transistors (MP4), the sixth PMOS transistor (MP6) and a fourth NMOS transistor (MN4) are used to provide the inverted signal of the first signal (V(IN)); An output terminal (OUT) is coupled to the fourth node (N4) for outputting the second signal (V(OUT)); a first high power supply voltage (VDDH) is coupled to the first PMOS The source electrodes of the transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are used to provide the first voltage required by the potential conversion circuit a high potential voltage; a second high power supply voltage (VDDL) for providing the second high potential voltage required by the potential conversion circuit, the potential of the second high power supply voltage (VDDL) is lower than the first high potential The potential of the power supply voltage (VDDH); a latch circuit (1), coupled to the first high power supply voltage (VDDH), for storing the converted output potential and controlling the leakage current; an output control circuit (2) , for controlling the potential of the output signal of the potential conversion circuit; and an input circuit (3), coupled to the first input end (IN), for providing a differential input signal. The low-power-consumption high-performance potential conversion circuit as claimed in claim 1, wherein the latch circuit (1) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high power supply a voltage (VDDH), the gate of which is connected to the fourth node (N4), and the drain of which is connected to the first node (N1); A second PMOS transistor (MP2) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the third node (N3), and whose drain is connected to the second node ( N2) is connected; a fifth PMOS transistor (MP5), its source is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1) Three nodes (N3) are connected; a sixth PMOS transistor (MP6), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); a first NMOS transistor (MN1), the source of which is connected to the drain of the third NMOS transistor (MN3), and the gate of which is connected to the fourth node (N4) ), and its drain is connected to the third node (N3); and a second NMOS transistor (MN2), its source is connected to the drain of the fourth NMOS transistor (MN4), and its gate is is connected to the third node (N3), and its drain is connected to the fourth node (N4). The low-power-consumption high-performance potential conversion circuit as described in claim 2, wherein the output control circuit (2) comprises: a third PMOS transistor (MP3), the source of which is connected to the first high power supply a voltage (VDDH), the gate of which is connected to the first input terminal (IN) and the drain of which is connected to the first node (N1); and A fourth PMOS transistor (MP4), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the second input terminal (INB), and whose drain is connected to the second node (N2) is connected. The low-power-consumption high-performance potential conversion circuit according to claim 3, wherein the input circuit (3) comprises: a third NMOS transistor (MN3), the source of which is connected to the ground (GND), and the gate of which is connected to the ground (GND). The electrode is connected to the first input terminal (IN), and the drain electrode is connected to the source electrode of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), whose source electrode is connected to the ground ( GND), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1), coupled to Connected to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal inverse to the first signal (V(IN)). The low power consumption high performance level conversion circuit as claimed in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The low power consumption and high performance potential conversion circuit as claimed in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The low power consumption and high performance level conversion circuit as claimed in claim 4, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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