TWM625119U - Voltage level converting circuit with reduced power consumption - Google Patents

Abstract

The present invention proposes a potential conversion circuit for reducing power consumption, which is composed of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), wherein the input circuit (1) is a Used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and suppress the competition of the output potential; the power saving control switch circuit (3) is used to prevent the flow of current in a standby state , to reduce power loss.

The potential conversion circuit for reducing power consumption proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and the miniaturization of the device, and can also effectively The competition between the pull-up path and the pull-down path is suppressed, thereby reducing power consumption.

Description

Potential conversion circuit for reducing power consumption

This creation proposes a potential conversion circuit for reducing power consumption, especially a circuit composed of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), in order to obtain accurate voltage level conversion , At the same time, it can also effectively reduce the power loss of electronic circuits.

A potential conversion circuit is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential conversion circuit is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a mirror-type potential conversion circuit of another prior art. The potential conversion circuit is formed by connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to the together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential conversion circuit is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the conversion circuit will not There are too many changes. Therefore, the mirror-type potential conversion circuit can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is created between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

FIG. 2 shows a prior art latch-type potential conversion circuit, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), A second NMOS transistor (MN2) and an inverter (INV), wherein the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and the ground (GND), and the first The potential of a signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential conversion circuit is in a stable state, the latch type There is no static current generated in the potential conversion circuit. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; (MN1) When the second NMOS transistor (MN2) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP1). ) to turn off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential conversion circuit, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the output terminal The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention, so the speed of the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) are fully turned on or turned off, which will cause a static current between the first high power supply voltage (VDDH) and the ground (GND) ), this quiescent current will increase the power loss.

Furthermore, the performance of the latch-type potential conversion circuit is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the first high power supply that can make the latch-type potential conversion circuit operate normally is limited Supply voltage (VDDH) range. During the process when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the pull-up of the potential on the output terminal (OUT) There is contention between rising and falling, so the speed of the second signal (V(OUT)) is slower when it transitions to a low level.

In view of this, the main purpose of this creation is to provide a potential conversion circuit with reduced power consumption, which can not only accurately and quickly convert a first signal into a second signal, but also can effectively reduce the pull-up path and pull-down path. Compete with each other, thereby reducing power loss.

The present invention proposes a potential conversion circuit for reducing power consumption, which is composed of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), wherein the input circuit (1) is a Used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and suppress the competition of the output potential; the power saving control switch circuit (3) is used to prevent the flow of current in a standby state , to reduce power loss.

The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has the advantages of simple circuit structure and the advantages of miniaturization of the device. efficiency, while also effectively reducing power loss.

1: Input circuit

2: Latch circuit

3: Power saving control switch

GND: ground

I1: first inverter

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

N5: Fifth node

N6: sixth node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

OUT: output terminal

V(OUT): Second signal

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

EN: Enable control terminal

ENB: Inverting enable control terminal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

FIG. 1 is a circuit diagram showing a potential conversion circuit in the first prior art;

FIG. 2 is a circuit diagram showing a potential conversion circuit in the second prior art;

FIG. 3 is a circuit diagram of a potential conversion circuit for reducing power consumption according to a preferred embodiment of the present invention;

FIG. 4 is a timing chart of transient analysis of the first signal and the second signal according to the preferred embodiment of the present invention;

According to the above purpose, the present invention proposes a potential conversion circuit for reducing power consumption, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3) The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and suppress the competition of the output potential; the power saving control switch circuit (3) It is used to prevent the flow of current in the standby state to reduce power loss; the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter A phase device (I1) is formed, wherein the source of the first NMOS transistor (MN1) is connected to the fifth node (N5), the gate is connected to the first input terminal (IN), and the drain is is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)), and provide a signal inverse to the first signal (V(IN)); the latch circuit (2) consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first PMOS transistor (MP2), and a It consists of three PMOS transistors (MP3), a fourth PMOS transistor (MP4), a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4), wherein the first PMOS transistor (MP1) ) source is connected to the sixth node (N6), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the second PMOS transistor ( The source of MP2) is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the third PMOS transistor The source of (MP3) is connected to the sixth node (N6), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the fourth PMOS The source of the transistor (MP4) is connected to the sixth node (N6), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first The source of the three NMOS transistors (MN3) is connected to the third node (N3), the gate is connected to the second input terminal (INB), and the drain is connected to the first node (N1); The source of the fourth NMOS transistor (MN4) is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2) connection; the power saving control switch circuit (3) consists of a fifth PMOS transistor (MP5), a fifth NMOS transistor (MN5), an enable control terminal (EN) and an inversion enable control terminal (ENB) formed, wherein the source of the fifth PMOS transistor (MP5) is connected to the first high power supply voltage (VDDH), the gate is connected to the enable control terminal (EN), and the drain is connected to the The sixth node (N6) is connected; the source of the fifth NMOS transistor (MN5) is connected to the ground (GND), the gate is connected to the inverting enable control terminal (ENB), and the drain is is connected to the fifth node (N5); the enabling control terminal (EN) is coupled to the gate of the fifth PMOS transistor (MP5) for providing an enabling signal; the inverting enabling control terminal (ENB) is coupled to the gate of the fifth NMOS transistor (MN5) for providing an inversion enable signal; the first high power supply voltage (VDDH) is used for providing the potential for reducing power consumption The first high power supply voltage required by the conversion circuit; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the potential conversion circuit for reducing power consumption; the second high power supply voltage ( The level of VDDL) is lower than the level of the first high power supply voltage (VDDH); the first signal is a square wave between 0 volts and 1.2 volts, and the second signal is between 0 volts and 1.2 volts Corresponding waveforms between 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, the second signal ( V(OUT)) is the corresponding waveform between 0 volts and 1.8 volts.

Please refer to FIG. 3 again, when the signal of the enable control terminal (EN) is at a logic low level and the signal at the inverting enable control terminal (ENB) is at a logic high level, the fifth PMOS transistor (MP5) and the The fifth NMOS transistors (MN5) are all turned on (ON), and the potential conversion circuit is in an active (active) state; now consider that when the first signal (V(IN)) is a logic low level (0 volts), the potential conversion circuit Steady-state operation situation: the logic low level on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the third PMOS transistor (MP3), the fourth NMOS transistor ( MN4) and the gate of the first NMOS transistor (MN1), so that both the fourth NMOS transistor (MN4) and the first NMOS transistor (MN1) are turned off (OFF), and the third PMOS transistor (MP3) ) is turned on (ON); and the first inverter (I1) transmits a logic high level (VDDL) to the fourth PMOS transistor (MP4), the third NMOS transistor (MN3) and the second NMOS transistor (MN2) gate, so that the third NMOS transistor (MN3) and the second NMOS transistor (MN2) are both turned on (ON), the fourth PMOS transistor (MP4) is turned off (OFF), at this time, Since the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4) are both turned off (OFF), the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are both turned on (ON). ), at this time, the potential of the fourth node (N4) will be pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) is transmitted to the first PMOS transistor (MP1) ) gate, so that the first PMOS transistor (MP1) is turned on (ON). At this time, because the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the third NMOS transistor ( MN3) are all turned on (ON), and the first NMOS transistor (MN1) is turned off (OFF), therefore, the potential of the third node (N3) will be pulled up to a logic high level, the logic high level of the third node (N3) makes the second PMOS transistor (MP2) cut off (OFF). At this time, the second PMOS transistor (MP2), the fourth PMOS transistor (MP4 ) and the fourth NMOS transistor (MN4) are both turned off (OFF), and the second NMOS transistor (MN2) is turned on (ON), therefore, the potential of the fourth node (N4) will maintain a logic low level (0 volts) steady-state value, a logic low level (0 volts) potential is output at the output terminal (OUT). Qualitatively speaking, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through a potential conversion circuit that reduces power consumption, and the output terminal ( OUT) output.

Then consider the steady state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic high level (VDDL): the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the first The input terminal of the inverter (I1), the third PMOS transistor (MP3), the fourth NMOS transistor (MN4), and the gate of the first NMOS transistor (MN1), so that the fourth NMOS transistor (MN1) (MN4) and the first NMOS transistor (MN1) are both turned on (ON), the third PMOS transistor (MP3) is turned off (OFF); and the first inverter (I1) transmits a logic low level to the first Four PMOS transistors (MP4), the third NMOS transistor (MN3) and the gates of the second NMOS transistor (MN2), such that the third NMOS transistor (MN3) and the second NMOS transistor (MN2) ) are all turned off (OFF), the fourth PMOS transistor (MP4) is turned on (ON), at this time, since the second PMOS transistor (MP2) and the fourth NMOS transistor (MN4) are both turned on (ON), And the second NMOS transistor (MN2) is turned off (OFF), therefore, the potential of the fourth node (N4) is pulled to a logic high level, and the logic high level of the fourth node (N4) makes the fourth node (N4) high. A PMOS transistor (MP1) is turned off (OFF). At this time, since the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the third NMOS transistor (MN3) are all turned off (OFF), And the first NMOS transistor (MN1) is turned on (ON), the potential of the third node (N3) will be pulled down to a logic low level, the third node (N3) The logic low level on is transmitted to the gate of the second PMOS transistor (MP2), so that the second PMOS transistor (MP2) is turned on (ON). At this time, due to the second PMOS transistor (MP2), the The fourth PMOS transistor (MP4) and the fourth NMOS transistor (MN4) are both turned on (ON), and the second NMOS transistor (MN2) is turned off (OFF), therefore, the potential of the fourth node (N4) It will maintain a steady state value of a logic high level, and output a logic high level potential at the output terminal (OUT). In other words, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) through a potential conversion circuit that reduces power consumption, and is output by terminal (OUT) output.

To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal When (V(IN)) is a logic high level (VDDL), the second signal (V(OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of potential conversion is achieved.

Figure 4 shows the simulation results of Spice transient analysis of the potential conversion circuit for reducing power consumption proposed in this work. The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work not only still remains The first signal can be quickly and accurately converted into a second signal, and the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power consumption.

Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included within the scope of the patent application of this creation.

1: Input circuit

2: Latch circuit

3: Power saving control switch

GND: ground

I1: first inverter

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

N5: Fifth node

N6: sixth node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

OUT: output terminal

V(OUT): Second signal

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

EN: Enable control terminal

ENB: Inverting enable control terminal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A potential conversion circuit for reducing power consumption for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the drain of a third NMOS transistor (MN3) together; A second node (N2) for connecting the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the drain of a fourth NMOS transistor (MN4) together; A third node (N3) for connecting the gate of the second PMOS transistor (MP2), the source of the third NMOS transistor (MN3) and the drain of a first NMOS transistor (MN1) together; A fourth node (N4) for connecting the gate of the first PMOS transistor (MP1), the source of the fourth NMOS transistor (MN4) and the drain of a second NMOS transistor (MN2) together; a fifth node (N5) for connecting the first NMOS transistor (MN1), the source of the second NMOS transistor (MN2) and the drain of a fifth NMOS transistor (MN5) together; A sixth node (N6) for the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) The source and the drain of a fifth PMOS transistor (MP5) are connected together; A first input terminal (IN) coupled to the fourth NMOS transistor (MN4), the first NMOS transistor (MN1), the gate of the third PMOS transistor (MP3) and a first inverting the input end of the device (I1) for providing the first signal (V(IN)); A second input terminal (INB), coupled to the third NMOS transistor (MN3), the second NMOS transistor (MN2), the gate of the fourth PMOS transistor (MP4) and the first inverting The output terminal of the device (I1) is used to provide the inverted signal of the first signal (V(IN)); an output terminal (OUT) coupled to the fourth node (N4) for outputting the second signal (V(OUT)); a first high power supply voltage (VDDH) coupled to the source of the fifth PMOS transistor (MP5) for providing the first high power supply voltage required by the potential conversion circuit; A second high power supply voltage (VDDL) for providing the second high power supply voltage required by the potential conversion circuit, the potential of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage (VDDH) ) of the potential; an input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; a latch circuit (2), coupled to the sixth node (N6) and the input circuit (1), for preserving and suppressing the competition phenomenon of the output potential; and A power-saving control switch circuit (3) is used to prevent the flow of current in a standby state, so as to reduce power consumption. The potential conversion circuit for reducing power consumption as described in claim 1, wherein the input circuit (1) comprises: A first NMOS transistor (MN1) whose source is connected to the fifth node (N5), whose gate is connected to the first input terminal (IN), and whose drain is connected to the third node (N3) connected; A second NMOS transistor (MN2) whose source is connected to the fifth node (N5), whose gate is connected to the second input terminal (INB), and whose drain is connected to the fourth node (N4) connected; and A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) inverted signal. The potential conversion circuit for reducing power consumption as described in claim 2, wherein the latch circuit (2) comprises: A first PMOS transistor (MP1), its source is connected to the sixth node (N6), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1) connect; A second PMOS transistor (MP2), its source is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the second node (N2) connect; A third PMOS transistor (MP3), whose source is connected to the sixth node (N6), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1) connected; A fourth PMOS transistor (MP4), whose source is connected to the sixth node (N6), whose gate is connected to the second input terminal (INB), and whose drain is connected to the second node (N2) connected; A third NMOS transistor (MN3) whose source is connected to the third node (N3), whose gate is connected to the second input terminal (INB), and whose drain is connected to the first node (N1) connected; and A fourth NMOS transistor (MN4) whose source is connected to the fourth node (N4), whose gate is connected to the first input terminal (IN), and whose drain is connected to the second node (N2) connected. The potential conversion circuit for reducing power consumption as described in item 3 of the scope of the application, wherein the power saving control switch circuit (3) comprises: A fifth PMOS transistor (MP5), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the enable control terminal (EN), and its drain is connected to the sixth node (N6) is connected; A fifth NMOS transistor (MN5), its source is connected to ground (GND), its gate is connected to the inverting enable control terminal (ENB), and its drain is connected to the fifth node (N5) connect; an enable control terminal (EN) coupled to the gate of the fifth PMOS transistor (MP5) for providing an enable signal; and An inversion enable control terminal (ENB) is coupled to the gate of the fifth NMOS transistor (MN5) for providing an inversion enable signal. The potential conversion circuit for reducing power consumption as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The potential conversion circuit for reducing power consumption as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The potential conversion circuit for reducing power consumption as described in claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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