TWM647689U - High speed voltage level converter with low power consumption - Google Patents

Abstract

This invention proposes a high-speed and low-power voltage level converter, which is composed of an input circuit (1), a latch circuit (2) and a level shift circuit (3), wherein the input circuit ( 1) is used to provide a differential input signal; the latch circuit (2) is used to preserve the differential input signal from the input circuit (1) and suppress the competition phenomenon of the output terminal (OUT) potential; and The level shift circuit (3) is used to convert the potential of the differential input signal.

The high-speed and low-power voltage level converter proposed by this invention not only can accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device. It can also Effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

High Speed Low Power Voltage Level Converter

This invention proposes a high-speed and low-power voltage level converter, especially one composed of an input circuit (1), a latch circuit (2) and a level shift circuit (3), in order to obtain accurate voltage Level conversion can also effectively reduce the power loss of electronic circuits.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (ICs for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the level converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

Figure 1 shows another prior art mirror type potential converter circuit. The potential converter is connected by connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror-type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too Big changes. Therefore, the mirror type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Figure 2 shows a prior art latch-type potential converter circuit, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1). , a second NMOS transistor (MN2) and an inverter (INV) to form a potential converter circuit, wherein the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively. . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output end (OUT) of the potential converter is in a stable state, the latch There is no static current generated in this type of potential converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, thereby pulling up the gate potential of the second PMOS transistor (MP2) and turning off the second PMOS transistor (MP2); furthermore, when the second PMOS transistor (MP2) is turned off; When one NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and causes the second PMOS transistor (MP2) to be turned on, causing it to be pulled up. The gate potential of the first PMOS transistor (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) approaches to be turned on (or turned off) and the second NMOS transistor (MN2) approaches to be turned off (or turned on), for the output terminal The potential on (OUT) rises and falls in competition with each other, so the second signal (V(OUT)) is slower when it transitions to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not cause the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or completely turned off, which will cause a static current (static current) between the first high power supply voltage (VDDH) and the ground (GND). current), this quiescent current will increase power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH) due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage

(VDDL). Therefore, the range of the first high power supply voltage (VDDH) in which the latch-type potential converter can operate normally is limited. In the process that the second PMOS transistor (MP2) approaches to turn on (or turns off) and the second NMOS transistor (MN2) approaches to turn off (or turns on), the pull of the potential on the output terminal (OUT) There is contention between rising and pulling down, so the second signal (V(OUT)) is slower when it transitions to a low potential.

In view of this, the main purpose of this invention is to propose a high-speed and low-power voltage level converter that can not only accurately and quickly convert the first signal into a second signal, but also effectively reduce the pull-up path and pull-down path. Paths compete with each other, thereby reducing power loss.

This invention proposes a high-speed and low-power voltage level converter, which is composed of an input circuit (1), a latch circuit (2) and a level shift circuit (3), wherein the input circuit ( 1) is used to provide the first signal (V(IN)) and the inverted signal of the first signal (V(IN)); the latch circuit (2) is used to preserve the converted output potential; and the The level shift circuit (3) is used to convert the potential of the differential input signal.

The simulation results confirm that the high-speed and low-power voltage level converter proposed by this invention can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is conducive to the miniaturization of the device. It has multiple functions and can also effectively reduce power loss.

1:Input circuit

2:Latching circuit

3:Level shift circuit

I1: first inverter

N1: first node

N2: second node

N3: The third node

N4: fourth node

MN1: The first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

MN4: The fourth NMOS transistor

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

OUT: output terminal

V(OUT): second signal

IN: first input terminal

V(IN): first signal

INB: second input terminal

GND: ground

VDDH: first high power supply voltage

VDDL: second highest power supply voltage

GND: ground

Figure 1 is a circuit diagram showing a potential converter in the first prior art; Figure 2 is a circuit diagram showing a voltage level converter in the second prior art; Figure 3 is a circuit diagram showing a high speed and low power consumption voltage level converter according to the preferred embodiment of the present invention;

According to the above purpose, this invention proposes a high-speed and low-power voltage level converter, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2) and a level shift circuit (3) Composed of, wherein, the input circuit (1) is used to provide a first signal (V(IN)) and an inverted signal of the first signal (V(IN)); the latch circuit (2) ) is used to save the converted output potential; and the level shift circuit (3) is used to convert the potential of the differential input signal; the input circuit (1) is composed of a first NMOS transistor (MN1), a It is composed of a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), and its gate is connected to the first The input terminal (IN), and its drain is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the ground (GND), and its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)), and provides a signal inverted with the first signal (V(IN)); the latch circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor Crystal (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first High power supply voltage (VDDH), with its gate connected to the third node (N3), Its drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the first node (N1), and its gate is connected to the first input terminal (IN ), and its drain is connected to the third node (N3); the source of the fourth PMOS transistor (MP4) is connected to the second node (N2), and its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the level shift circuit (3) is composed of a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4) Composed of, wherein the source of the third NMOS transistor (MN3) is connected to the second input terminal (INB), its gate is connected to the gate of the fourth NMOS transistor (MN4), and is connected to The second high power supply voltage (VDDL), and its drain is connected to the third node (N3); the source of the fourth NMOS transistor (MN4) is connected to the first input terminal (IN), Its gate is connected to the gate of the third NMOS transistor (MN3) and connected to the second high power supply voltage (VDDL), and its drain is connected to the fourth node (N4); The first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the high-speed and low-power voltage level converter, and the second high power supply voltage (VDDL) is used to provide the high-speed and low-power voltage level converter. The second high power supply voltage required by the voltage level converter. The level of the second high power supply voltage (VDDL) is smaller than the level of the first high power supply voltage (VDDH). The first signal is the intermediate A rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage The supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is between 0 volts and 1.8 volts. Corresponding waveforms between volts.

Please refer to Figure 3 again, now consider the steady-state operation of the high-speed and low-power voltage level converter when the first signal (V(IN)) is logic '0': the logic on the first input terminal (IN) '0' is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the third PMOS transistor (MP3), the gate of the first NMOS transistor (MN1) and the fourth NMOS transistor. The source of the crystal (MN4) causes the fourth NMOS transistor (MN4) and the third PMOS transistor (MP3) to be turned on (ON), and the first NMOS transistor (MN1) is turned off (OFF). The potential of the fourth node (N4) will be pulled down to a logic '0', and the first inverter (I1) transmits a logic '1' to the gate of the fourth PMOS transistor (MP4), the The gate of the two NMOS transistors (MN2) and the source of the third NMOS transistor (MN3) cause the fourth PMOS transistor (MP4) and the third NMOS transistor (MN3) to be turned OFF, And the second NMOS transistor (MN2) is turned on (ON), and the logic '0' on the fourth node (N4) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on. At this time, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on, the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are all turned off, therefore, the potential of the third node (N3) will be pulled up to a logic '1', and the logic '1' of the third node (N3) causes the second PMOS transistor (MP2) to turn off, because The second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off, and the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, and the fourth node ( The potential of N4) will maintain a steady-state value of logic '0' and is output from the output terminal (OUT). In other words, when the first signal (V(IN)) is logic '0', it is converted into a second signal with logic '0' through the potential converter, and is output from the output terminal (OUT).

Consider again the steady-state operation situation of the high-speed and low-power voltage level converter when the first signal (V(IN)) is logic '1': the logic '1' on the first input terminal (IN) is simultaneously transmitted to the first inverter (I1), the gate of the third PMOS transistor (MP3), the gate of the first NMOS transistor (MN1) and the source of the fourth NMOS transistor (MN4), so that the fourth The NMOS transistor (MN4) and the third PMOS transistor (MP3) are both OFF, while the first NMOS transistor (MN1) is ON, and the first inverter (I1) transmits logic ' 1' to the source of the third NMOS transistor (MN3), the gate of the fourth PMOS transistor (MP4) and the gate of the second NMOS transistor (MN2), so that the third NMOS transistor (MN2) MN3) and the fourth PMOS transistor (MP4) are both turned on (ON), and the second NMOS transistor (MN2) is turned off (OFF), and the potential of the third node (N3) will be pulled down to a logic ' 0', the logic '0' of the third node (N3) causes the second PMOS transistor (MP2) to be turned on. At this time, since both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) is turned on, and the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, the potential of the fourth node (N4) will be pulled up to a logic '1', and the fourth node The logic '1' on (N4) causes the first PMOS transistor (MP1) to turn off. At this time, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off (OFF), The first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on. Therefore, the potential of the third node (N3) will maintain a logic '0'. Therefore, the fourth node (N4 ) will maintain a steady-state value of logic '1' and be output from the output terminal (OUT). In other words, when the first signal (V(IN)) is a logic '1', it is converted into a second signal with a first high power supply voltage (VDDH) through a high-speed and low-power voltage level converter, and is output from terminal (OUT) output.

To sum up, when the first signal (V(IN)) is logic '0', the second signal (V(OUT)) is also logic '0'; and the first signal (V(IN)) When logic '1', the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of potential conversion is achieved now.

The Spice transient analysis simulation results of the high-speed and low-power voltage level converter proposed by this creation can confirm that the high-speed and low-power voltage level converter proposed by this creation can not only quickly and accurately convert the first The signal is converted into a second signal, and competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power loss.

Although the present invention specifically discloses and describes selected preferred embodiments, those familiar with the art will understand that any possible changes in form or details may be made without departing from the spirit and scope of the invention. Therefore, all changes within the relevant technical scope are included in the patentable scope of this creation.

1:Input circuit

2:Latching circuit

3:Level shift circuit

I1: first inverter

N1: first node

N2: second node

N3: The third node

N4: fourth node

MN1: The first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

MN4: The fourth NMOS transistor

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

OUT: output terminal

V(OUT): second signal

IN: first input terminal

V(IN): first signal

INB: second input terminal

GND: ground

VDDH: first high power supply voltage

VDDL: second highest power supply voltage

GND: ground

Claims (7)

A high-speed and low-power voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: a first node (N1) for The drain of a first PMOS transistor (MP1) and the source of a third PMOS transistor (MP3) are connected together; a second node (N2) is used to connect a second PMOS transistor (MP2) The drain electrode and the source electrode of a fourth PMOS transistor (MP4) are connected together; a third node (N3) is used to connect the drain electrode of a first NMOS transistor (MN1) and a third NMOS transistor The drain of (MN3), the drain of the third PMOS transistor (MP3) and the gate of the second PMOS transistor (MP2) are connected together; a fourth node (N4) is used to connect a second The drain of the NMOS transistor (MN2), the drain of a fourth NMOS transistor (MN4), the drain of the fourth PMOS transistor (MP4) and the gate of the first PMOS transistor (MP1) are connected to Together; a first input terminal (IN) coupled to the input terminal of the first inverter (I1), the gate of the third PMOS transistor (MP3), and the gate of the first NMOS transistor (MN1) The gate and the source of the fourth NMOS transistor (MN4) are used to provide the first signal (V(IN)); a second input terminal (INB) is coupled to the fourth PMOS transistor (MP4) ), the gate of the second NMOS transistor (MN2) and the source of the third NMOS transistor (MN3) are used to provide the inversion signal of the first signal (V(IN)); a The output terminal (OUT) is coupled to the fourth node (N4) for outputting the second signal (V(OUT)); A first high power supply voltage (VDDH) coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the fourth PMOS transistor The source of (MP4) is used to provide the first high potential voltage required by the high-speed and low-power voltage level converter; a second high power supply voltage (VDDL) is coupled to the first inverter ( The source electrode of I1), the gate electrode of the third NMOS transistor (MN3) and the gate electrode of the fourth NMOS transistor (MN4) are used to provide the second voltage level converter required by the high speed and low power consumption. A high potential voltage, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH); an input circuit (1) coupled to the first input terminal (IN), used to provide a differential input signal; a latch circuit (2) coupled to the first high power supply voltage (VDDH) to preserve the converted output potential; and a level shift circuit (3) coupled to Connected to the latch circuit (2), it is used to output the signal generated by the differential input signal. As for the high-speed and low-power voltage level converter described in item 1 of the patent application, the input circuit (1) includes: a first NMOS transistor (MN1), the source of which is connected to the ground (GND), and the The gate is connected to the first input terminal (IN), and the drain is connected to the third node (N3); A second NMOS transistor (MN2), its source is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing an inverter with the first signal (V(IN) ) inverted signal. The high-speed and low-power voltage level converter described in item 2 of the patent application, wherein the latch circuit (2) includes: a first PMOS transistor (MP1), the source of which is connected to the first high power supply Supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to The gate of the first high power supply voltage (VDDH) is connected to the third node (N3), and its drain is connected to the second node (N2); a third PMOS transistor (MP3), Its source is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); and a fourth PMOS transistor (MP4), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4). The high-speed and low-power voltage level converter described in item 3 of the patent application, wherein the level shift circuit (3) includes: A third NMOS transistor (MN3), its source is connected to the second input terminal (INB), its gate is connected to the gate of the fourth NMOS transistor (MN4), and is connected to the second high The power supply voltage (VDDL), and its drain is connected to the third node (N3); and a fourth NMOS transistor (MN4), its source is connected to the first input terminal (IN), and its gate The gate electrode of the third NMOS transistor (MN3) is connected to the second high power supply voltage (VDDL), and the drain electrode is connected to the fourth node (N4). For the high-speed and low-power voltage level converter described in claim 1 of the patent application, the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). For the high-speed and low-power voltage level converter described in claim 5 of the patent application, the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The high-speed and low-power voltage level converter described in item 2 of the patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

Images