TWM626417U - High-speed low-power level shifter circuit - Google Patents

Abstract

The present invention proposes a high-speed and low-power potential converter circuit, which is composed of an input circuit (1), a latch circuit (2), a pre-charge transistor (3), an output control transistor (4), and a It is composed of an output control transistor (5), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used for potential conversion; the precharge transistor (3) Used to precharge the second node (N2) when turned on to increase the potential of the output terminal (OUT); the output control transistor (4) is used to pull down the potential of the first node (N1); the The output control transistor (5) is used to pull down the potential of the second node (N2).

The high-speed and low-power level converter circuit proposed in this work can not only convert the first signal into a second signal quickly, but also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

Description

High-speed and low-power potential converter circuit

The present invention proposes a high-speed and low-power potential converter circuit, which is composed of an input circuit (1), a latch circuit (2), a pre-charge transistor (3), an output control transistor (4), and a The electronic circuit is composed of an output control transistor (5), in order to quickly obtain accurate voltage level conversion, and at the same time, it can also effectively reduce power consumption.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a prior art latch-type potential converter circuit, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type There is no static current generated in the potential converter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), the output terminal is Pull-up and pull-up of the potential on (OUT) There is contention between the two voltages, so the second signal (V(OUT)) is slow when transitioning to a low level. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) are completely turned on or turned off, which will cause a static current to exist between the first high potential voltage (VDDH) and the ground (GND). ), this quiescent current will increase the power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high potential voltage (VDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type potential converter can operate normally is limited.

FIG. 2 shows another prior art mirror-type potential shifter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and connecting to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the saturation region, And its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the potential conversion The performance of the device will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is created between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of the fact that the potentials at the output terminals of the latch-type potential converters compete with each other, the main purpose of this creation is to propose a high-speed and low-power potential converter circuit, which can not only accurately and quickly convert the first signal Converted to a second signal, and can effectively reduce power consumption.

The present invention proposes a high-speed and low-power potential converter circuit, which is composed of an input circuit (1), a latch circuit (2) and a pre-charge transistor (3), wherein the potential conversion circuit (1) ) is used for potential conversion; the input circuit (2) is used to provide a differential input signal; the output control switch (3) is used to reduce transient current consumption in standby mode; and the current blocking switch ( 4) is used to control the different operations of the potential converter model.

It is confirmed by the simulation results that the high-speed and low-power potential converter circuit proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is conducive to the miniaturization of the device, etc. Multiple functions can also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

1: Input circuit

2: Latch circuit

3: Precharge transistor

4: Output control transistor

5: Output control transistor

I1: first inverter

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

GND: ground

IN: the first input terminal

V(IN): The first signal

OUT: output terminal

V(OUT): Second signal

OUTB: Inverted output terminal

INB: the second input terminal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

FIG. 1 is a circuit diagram showing a potential converter in the first prior art;

FIG. 2 is a circuit diagram showing a potential converter in the second prior art;

FIG. 3 is a circuit diagram showing a high-speed and low-power potential converter circuit according to a preferred embodiment of the present invention;

FIG. 4 is a timing chart of transient analysis of the first signal and the second signal according to the preferred embodiment of the present invention;

According to the above purpose, the present invention proposes a high-speed and low-power potential converter circuit, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2), and a precharge transistor (3). ), an output control transistor (4) and an output control transistor (5), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used for is potential conversion; the pre-charging transistor (3) is used to pre-charge the second node (N2) when it is turned on, so as to increase the potential of the output terminal (OUT); the output control transistor (4) is used for Pulling down the potential of the first node (N1); the output control transistor (5) is used to pull down the potential of the second node (N2); the input circuit (1) is coupled to the first input terminal (IN ), used to provide a differential input signal; it is composed of a first NMOS Transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), which The gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the ground (GND), and its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) for receiving The first signal (V(IN)) is provided with an inverted signal of the first signal (V(IN)); the latch circuit (2) is coupled to the first high power supply voltage (VDDH) and An input circuit (1) for potential conversion; it consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a fourth PMOS transistor (MP4) and a fifth PMOS transistor (MP4) It consists of a PMOS transistor (MP5), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), the gate of the first PMOS transistor (MP1) is connected to the fourth node (N4), and Its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), and its gate is connected to the third node ( N3), and its drain is connected to the second node (N2); the source of the fourth PMOS transistor (MP4) is connected to the first node (N1), and its gate is connected to the second input terminal (INB), and its drain is connected to the third node (N3); the source of the fifth PMOS transistor (MP5) is connected to the second node (N2), and its gate is connected to the third node (N2) An input terminal (IN), and its drain is connected to the fourth node (N4); the precharge transistor (3) is composed of a third PMOS transistor (MP3), the source of which is connected to A first high power supply voltage (VDDH), the gate of which is connected to the second input terminal (INB), and the drain of which is connected to the second node (N2) connected; the output control transistor (4) is composed of a third NMOS transistor (MN3), its source is connected to ground (GND), its gate is connected to the first input terminal (IN), and its The drain electrode is connected to the first node (N1); the output control transistor (5) is composed of a fourth NMOS transistor (MN4), the source electrode is connected to the ground (GND), and the gate electrode is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first high power supply voltage (VDDH) is used to provide the high-speed and low-power level converter circuit The first high power supply voltage required, the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the high-speed low-power level converter circuit, the second high power supply voltage (VDDL) The level is lower than the level of the first high power supply voltage (VDDH), the first signal is a square wave between 0 volts and 1.2 volts, and the second signal is between 0 volts and 1.8 volts Corresponding waveforms between, the first high power supply voltage (VDDH) is 1.8 volts, the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is between 0 volts and A rectangular wave between 1.2 volts, the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again, now consider the steady-state operation of the high-speed and low-power level converter circuit when the first signal (V(IN)) is at a logic low level (0 volts): on the first input terminal (IN) The logic low level is simultaneously transmitted to the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), the gate of the fourth PMOS transistor (MP4) and a first inverter The input terminal of the phase device (I1), so that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off (OFF), the fourth PMOS transistor (MP4) is turned on (ON), and The first inverter (I1) transmits a logic high level (VDDL) to the gate of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), the third PMOS transistor ( MP3) gate and the fifth The gate of the PMOS transistor (MP5) makes both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) conductive (ON), the third PMOS transistor (MP3) and the fifth PMOS transistor The transistors (MP5) are all turned off (OFF). At this time, since the fourth NMOS transistor (MN4) is turned on, the third PMOS transistor (MP3) is turned off (OFF), and the potential of the second node (N2) will be is pulled down to a logic low level (0 volts) and output from the output terminal (OUT), since the fifth PMOS transistor (MP5) is also turned off, the second NMOS transistor (MN2) is turned on (ON), the The potential of the fourth node (N4) is pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) makes the first PMOS transistor (MP1) conductive (ON), At this time, since the first PMOS transistor (MP1) is turned on (ON), the potential of the first node (N1) will be pulled up to a logic high level and output by the inverting output terminal (OUTB). The four PMOS transistors (MP4) are also turned on, and the first NMOS transistor (MN1) is turned off (OFF). Therefore, the potential of the third node (N3) will be pulled up to a logic high level, the third node The logic high level of (N3) makes the second PMOS transistor (MP2) off, since the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are also off, and the fourth NMOS transistor (MN4) is turned on, therefore, the potential of the second node (N2) will be maintained at a logic low level (0 volts), that is, the potential of the output terminal (OUT) will be maintained at a logic low level (0 volts) stable state value. In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through a high-speed and low-power potential converter circuit, and is sent from the output terminal. (OUT) output.

Then consider the steady state operation of the high-speed and low-power level converter circuit when the first signal (V(IN)) is at the logic high level (VDDL): the logic high level (VDDL) on the first input terminal (IN) is simultaneously to the input of the first inverter (I1), the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3) and the fourth PMOS transistor (MP4) gate, so that both the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). The three NMOS transistors (MN3) are turned on, the potential of the first node (N1) will be pulled down to a logic low level (0 volts) and output by the inverting output terminal (OUTB), and the first inverter (I1) transmit a logic low level to the gate of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), the gate of the third PMOS transistor (MP3) and the fifth The gate of the PMOS transistor (MP5), so that the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off (OFF), while the third PMOS transistor (MP3) and the fifth The PMOS transistors (MP5) are all turned on (ON). At this time, since the third PMOS transistor (MP3) is turned on (ON) and the fourth NMOS transistor (MN4) is turned off (OFF), the second node ( The potential of N2) will be pulled up to a logic high level and output by the output terminal (OUT). Since the fifth PMOS transistor (MP5) is also turned on (ON), therefore, the potential of the fourth node (N4) will be pulled up to a logic high level, and the logic high level of the fourth node (N4) makes the first PMOS transistor (MP1) off. At this time, because the first PMOS transistor (MP1) and the fourth PMOS transistor (MP1) The transistors (MP4) are all turned off, and the first NMOS transistor (MN1) is turned on. Therefore, the potential of the third node (N3) will be pulled down to a logic low level (0 volts). The third node ( The logic low level on N3) makes the second PMOS transistor (MP2) turn on. At this time, since the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are both turned on, the second NMOS transistor (MP2) is turned on. The crystal (MN2) is turned off, therefore, the potential of the output terminal (OUT) will maintain a steady state value of a logic high level. In other words, when the first signal (V(IN)) is a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) through a high-speed and low-power level converter circuit, and is converted by Output terminal (OUT) output.

To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the The second signal (V(OUT)) is also at a logic low level (0 volts); and when the first signal (V(IN)) is at a logic high level (VDDL), the second signal (V(OUT)) is The first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The Spice transient analysis simulation results of the high-speed and low-power potential converter circuit proposed in this work are shown in Figure 4. The simulation results can confirm that the high-speed and low-power potential converter circuit proposed in this work has Not only can the first signal be converted into a second signal quickly and accurately, but also the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power consumption.

Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1: Input circuit

2: Latch circuit

3: Precharge transistor

4: Output control transistor

5: Output control transistor

I1: first inverter

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

GND: ground

IN: the first input terminal

V(IN): The first signal

OUT: output terminal

V(OUT): Second signal

OUTB: Inverted output terminal

INB: the second input terminal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (9)

A high-speed and low-power potential converter circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the source of a fourth PMOS transistor (MP4) and the drain of a third NMOS transistor (MN3) together; A second node (N2) for connecting the drain of a second PMOS transistor (MP2), the drain of a third PMOS transistor (MP3), the drain of a fifth PMOS transistor (MP5), and The drains of a fourth NMOS transistor (MN4) are connected together; A third node (N3) for connecting the gate of the second PMOS transistor (MP2), the drain of the fourth PMOS transistor (MP4) and the drain of a first NMOS transistor (MN1) together; A fourth node (N4) for connecting the gate of the first PMOS transistor (MP1), the drain of the fifth PMOS transistor (MP5) and the drain of a second NMOS transistor (MN2) together; A first input terminal (IN), coupled to the gate of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), and the gate of the fourth PMOS transistor (MP4) and an input end of a first inverter (I1) for providing a first signal (V(IN)); A second input terminal (INB), coupled to the gate of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), and the gate of the third PMOS transistor (MP3) , the gate of the fifth PMOS transistor (MP5) and the output terminal of the first inverter (I1) to provide the inverted signal (V(INB)) of the first signal (V(IN)) ; an output terminal (OUT) coupled to the second node (N2) for outputting the second signal (V(OUT)); an inversion output terminal (OUTB), coupled to the first node (N1), for outputting an inversion signal of the second signal (V(OUT)); A first high power supply voltage (VDDH) coupled to the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) for providing the first high power supply voltage required by the potential converter circuit; A second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the potential converter circuit, and the potential of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage ( VDDH) potential; an input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; a latching circuit (2) coupled to the first high power supply voltage (VDDH) and an input circuit (1) for potential conversion; A pre-charging transistor (3) is used to pre-charge the second node (N2) when turned on, so as to increase the potential of the output terminal (OUT); an output control transistor (4) for pulling down the potential of the first node (N1); and An output control transistor (5) is used to pull down the potential of the second node (N2). The high-speed and low-power-consumption potential converter circuit as described in item 1 of the patent application scope, wherein the input circuit (1) comprises: a first NMOS transistor (MN1), its source is connected to ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a second NMOS transistor (MN2) whose source is connected to ground (GND), whose gate is connected to the second input terminal (INB), and whose drain is connected to the fourth node (N4); and A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) inverted signal. The high-speed and low-power-consumption potential converter circuit as described in item 2 of the patent application scope, wherein the latch circuit (2) comprises: A first PMOS transistor (MP1), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node ( N1) is connected; A second PMOS transistor (MP2) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the third node (N3), and whose drain is connected to the second node ( N2) is connected; A fourth PMOS transistor (MP4) has its source connected to the first node (N1), its gate connected to the second input terminal (INB), and its drain connected to the third node (N3) connected; and A fifth PMOS transistor (MP5), whose source is connected to the second node (N2), whose gate is connected to the first input terminal (IN), and whose drain is connected to the fourth node (N4) connected. The high-speed and low-power-consumption potential converter circuit of claim 3, wherein the pre-charge transistor (3) is composed of a third PMOS transistor (MP3), the source of which is connected to To the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2). The high-speed and low-power-consumption potential converter circuit as claimed in claim 4, wherein the output control transistor (4) is composed of a third NMOS transistor (MN3), the source of which is connected to the ground (GND) ), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1). The high-speed and low-power-consumption potential converter circuit as claimed in claim 5, wherein the output control transistor (5) is composed of a fourth NMOS transistor (MN4), the source of which is connected to the ground (GND) ), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2). The high-speed and low-power level converter circuit of claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The high-speed and low-power level converter circuit of claim 7, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The high-speed and low-power level converter circuit of claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

Images