TWM598007U - High performance voltage level converter - Google Patents

Abstract

This creation proposes a high-performance voltage level converter, which is composed of a latch circuit (1), a potential raising circuit (2) and an input circuit (3), wherein the latch circuit (1) It is used to save the differential input signal received by the input transistor; the potential raising circuit (2) is used to raise the potential of the first node (N1) and the second node (N2) to the first high The power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V(IN)) and the inverted signal of the first signal (V(IN)).

The high-performance voltage level converter proposed by this creation not only can accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and it can also effectively Reduce leakage current, thereby reducing power consumption.

Description

High performance voltage level converter

This creation is related to a high-performance voltage level converter, especially using a latch circuit (1), a potential-raising circuit (2) and an input circuit (3) to obtain accurate voltage level conversion And effectively reduce the power consumption of the electronic circuit.

A voltage level converter is an electronic circuit used to communicate signals between different integrated circuits (ICs). In many applications, when the application system needs to transfer the signal from the core logic with a lower voltage level to the peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low-voltage working signal into a high-voltage working signal .

Figure 1 shows a prior art latch-type voltage-level converter circuit, which uses a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1 ), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2) and an inverting Inverter (INV) constitutes a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the first signal (V(IN) The potential of) is also between the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . because Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; furthermore, when the first NMOS transistor When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up. The gate potential of the transistor (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional voltage level converter, when the second PMOS transistor (MP2) is approaching to turn on (or off) and the second NMOS transistor (MN2) is approaching to turn off (or on), for The pull-up and pull-down of the potential on the output terminal (OUT) have a contention phenomenon, so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) And the second NMOS transistor (MN2) is fully turned on or completely turned off. This will cause a static current between the first high potential voltage (VDDH) and ground (GND). This static current will increase the power Loss.

Moreover, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH), due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The voltage is the first high potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type voltage level converter operate normally is limited.

Figure 2 shows another mirror-type voltage level converter circuit of the prior art by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the The saturation region and its gate voltage make the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate electrodes of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The bit is pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a high-performance voltage level converter, which can not only accurately and quickly convert the first signal to a second signal, but also can effectively reduce leakage current, thereby reducing power consumption .

This creation proposes a high-performance voltage level converter, which is composed of a latch circuit (1), a potential raising circuit (2) and an input circuit (3), wherein the latch circuit (1) It is used to save the differential input signal received by the input transistor; the potential raising circuit (2) is used to raise the potential of the first node (N1) and the second node (N2) to the first high The power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V(IN)) and the inverted signal of the first signal (V(IN)).

The simulation results confirm that the high-performance voltage level converter proposed by this creation can not only accurately and quickly convert the first signal to a second signal, but also has the advantages of simple circuit structure and miniaturization of the device. Efficacy, while also effectively reducing power loss.

1: Latching circuit

2: Potential rise circuit

3: Input circuit

N1: the first node

N2: second node

N3: third node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MP4: fourth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

IN: the first input

V(IN): first signal

INB: second input

OUT: output terminal

V(OUT): second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

I1: First inverter

Figure 1 shows the circuit diagram of the voltage level converter in the first prior art;

Figure 2 is a circuit diagram showing the voltage level converter in the second prior art;

Figure 3 is a circuit diagram showing the high-performance voltage-level converter of the preferred embodiment of the invention;

Figure 4 shows the transient analysis timing of the first signal and the second signal of the preferred embodiment of this creation Figure.

According to the above-mentioned purpose, this creation proposes a high-performance voltage level converter, as shown in Figure 3, which consists of a latch circuit (1), a potential rise circuit (2) and an input circuit (3) The latch circuit (1) is used to store the differential input signal received by the input transistor; the potential up circuit (2) is used to store the first node (N1) and the second The potential of the node (N2) is pulled up to the first high power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V(IN)) and the first signal (V(IN)) ) Inverted signal; the latch circuit (1) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS transistor The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), the gate is connected to the second node (N2), and the source of the first PMOS transistor (MP1) is connected to the second node (N2). The pole is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), and the gate is connected to the first node (N1) ), and its drain is connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), and its gate is connected to The second node (N2), and its drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4) , Its gate is connected to the first node (N1), and its drain is connected to the second node (N2); the potential raising circuit (2) is composed of a third PMOS transistor (MP3) and A fourth PMOS transistor (MP4), where the source of the third PMOS transistor (MP3) The pole is connected to the first high power supply voltage (VDDH), the gate is connected to the first input (IN), and the drain is connected to the first node (N1); the fourth PMOS transistor The source of (MP4) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the The input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the third NMOS transistor (MN3) The source of is connected to the third node (N3), its gate is connected to the first input (IN), and its drain is connected to the source of the first NMOS transistor (MN1); The source of the quad NMOS transistor (MN4) is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the second NMOS transistor (MN2) The source is connected; the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal that is connected to the first signal (V (IN)) an inverted signal; the first high power supply voltage (VDDH) is used to provide the first high potential voltage required by the voltage level converter; and the second high power supply voltage (VDDL) is Used to provide the second high potential voltage required by the voltage level converter, the potential of the second high power supply voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH), the first high power The supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second The signal (V(OUT)) has a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again to explain the working principle of Figure 3 as follows:

Now consider the steady state of the voltage level converter when the first signal (V(IN)) is low (0 volt) Operation situation: The low potential on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the third NMOS transistor (MN3) and the gate of the third PMOS transistor (MP3), The third NMOS transistor (MN3) is turned off and the third PMOS transistor (MP3) is turned on. At this time, the potential of the first node (N1) is pulled up to a high potential close to the first high potential voltage (VDDH) ; And the first inverter (I1) transmits the second high potential voltage (VDDL) to the gates of the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor ( MN4) is turned on, the fourth PMOS transistor (MP4) is turned off, and the high potential of the first node (N1) causes the second PMOS transistor (MP2) to turn off and the second NMOS transistor (MN2) to turn on. Since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, the potential of the second node (N2) will be pulled down to a low potential (0 volt) steady state value, Furthermore, the low potential on the second node (N2) is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first PMOS transistor (MP1) is turned on and the The first NMOS transistor (MN1) is turned off. Since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on, the first NMOS transistor (MN1) and the third NMOS transistor ( MN3) are all turned off. Therefore, the potential of the first node (N1) will maintain a first high voltage (VDDH), and since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, The second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off. Therefore, the potential of the second node (N2) will be maintained at a low potential (0V), that is, the potential of the output terminal (OUT) Will be pulled down to a steady-state value of a low potential (0 volts). In a nutshell, when the first signal (V(IN)) is at a low potential (0 volt), it is converted into a second signal with a low potential (0 volt) by the voltage level converter, and is output from the output terminal (OUT).

Consider the steady state operation of the voltage level converter when the first signal (V(IN)) is at a high potential (1.2 volts): the high potential on the first input terminal (IN) is simultaneously transmitted to the first inverter (I1) The input terminal of the third NMOS transistor (MN3) and the gate of the third PMOS transistor (MP3) make the third NMOS transistor (MN3) turn on, the third PMOS transistor (MP3) turn off, and the The first inverter (I1) transmits a low potential to the gates of the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4) is turned off and the fourth PMOS transistor The transistor (MP4) is turned on. At this time, because the fourth PMOS transistor (MP4) is turned on, the potential of the second node (N2) will be pulled up to a high potential close to the first high potential voltage (VDDH); and the The high potential of the second node (N2) causes the first PMOS transistor (MP1) to turn off and the first NMOS transistor (MN1) to turn on. At this time, the first NMOS transistor (MN1) and the third NMOS transistor ( MN3) are all turned on. Therefore, the potential of the first node (N1) will be pulled down to a low potential (0 volts). Furthermore, the low potential on the first node (N1) is transmitted to the second PMOS transistor (MP2) and the gate of the second NMOS transistor (MN2), so that the second PMOS transistor (MP2) is turned on and the second NMOS transistor (MN2) is turned off. At this time, due to the second PMOS transistor (MP2) ) And the fourth PMOS transistor (MP4) are turned on, the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, therefore, the potential of the second node (N2) will be maintained at the first high potential Voltage (VDDH), and the potential of the first node (N1) is maintained at a low potential (0V), that is, the potential of the output terminal (OUT) will be pulled up to a steady state of a first high potential voltage (VDDH) value. In a nutshell, when the first signal (V(IN)) is the second high-potential voltage (1.2V), it is converted into a second signal with the first high-potential voltage (1.8V) by the output Terminal (OUT) output.

To sum up, when the first signal (V(IN)) is at a low potential (0 volt), the second signal (V(OUT)) is also at a low potential (0 volt); and the first signal (V(IN)) When) is the second high potential voltage (1.2V), the second signal (V(OUT)) is the first high potential voltage (1.8V). In this way, the purpose of voltage level conversion is achieved.

The Spice transient analysis simulation results of the high-performance voltage-level converter proposed in this creation are shown in Figure 4. The simulation results can confirm that the high-performance voltage-level converter proposed in this creation is not only The first signal can be quickly and accurately converted into a second signal, and the power loss can be effectively reduced.

Although this creation specifically discloses and describes the selected best embodiment, anyone familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.

1: Latching circuit

2: Potential rise circuit

3: Input circuit

N1: the first node

N2: second node

N3: third node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MP4: fourth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

IN: the first input

V(IN): first signal

INB: second input

OUT: output terminal

V(OUT): second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

I1: First inverter

Claims (7)

A high-performance voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the gate of a second PMOS transistor (MP2), the drain of a first NMOS transistor (MN1), The drain of a third PMOS transistor (MP3) and the gate of a second NMOS transistor (MN2) are connected together; A second node (N2) for the drain of the second PMOS transistor (MP2), the gate of the first PMOS transistor (MP1), the drain of the second NMOS transistor (MN2), The drain of a fourth PMOS transistor (MP4) and the gate of the first NMOS transistor (MN1) are connected together; A third node (N3) for connecting the source of a third NMOS transistor (MN3) and the source of a fourth NMOS transistor (MN4) together; A first input terminal (IN), coupled to the third PMOS transistor (MP3) and the gate of the third NMOS transistor (MN3), for providing a first signal (V(IN)); A second input terminal (INB) is coupled to the gate of the fourth PMOS transistor (MP4) and the fourth NMOS transistor (MN4) to provide the inverse of the first signal (V(IN)) Phase signal An output terminal (OUT), coupled to the second node (N2), for outputting the second signal (V(OUT)); A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal A first high power supply voltage (VDDH), coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) source to provide the first high-potential voltage required by the high-performance voltage-level converter; A second high power supply voltage (VDDL) is used to provide the second high potential voltage required by the high-performance voltage-level converter. The second high power supply voltage (VDDL) has a lower potential than the first high power supply The potential of the supply voltage (VDDH); A latch circuit (1) for storing the differential input signal received by the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4); A potential raising circuit (2) for raising the second signal (V(OUT)) to the first high power supply voltage (VDDH); and An input circuit (3) is used to provide the first signal (V(IN)) and an inverted signal of the first signal (V(IN)). The high-performance voltage level converter described in item 1 of the scope of patent application, wherein the latch circuit (1) includes: A first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node ( N1) phase connection; A second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node ( N2) phase connection; A first NMOS transistor (MN1), its source is connected to the drain of the third NMOS transistor (MN3), its gate is connected to the second node (N2), and its drain is connected to the first Node (N1) is connected; and A second NMOS transistor (MN2) whose source is connected to the drain of the fourth NMOS transistor (MN4), whose gate is connected to the first node (N1), and whose drain is connected to the second node (N1) The node (N2) is connected. The high-performance voltage level converter described in item 2 of the scope of patent application, wherein the potential raising circuit (2) includes: A third PMOS transistor (MP3) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1) are connected; and A fourth PMOS transistor (MP4) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2) Connected. The high-performance voltage level converter described in item 3 of the scope of patent application, wherein the input circuit (3) includes: A third NMOS transistor (MN3) whose source is connected to the third node (N3), its gate is connected to the first input terminal (IN), and its drain is connected to the first NMOS transistor ( The source of MN1) is connected; A fourth NMOS transistor (MN4), its source is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the second NMOS transistor ( The source of MN2) is connected; and A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal. The high-performance voltage level converter described in the first item of the scope of patent application, wherein the amplitude of the first signal (V(IN)) is between 0 volt and the second high power supply voltage (VDDL). According to the high-performance voltage level converter described in item 5 of the scope of patent application, the amplitude of the second signal (V(OUT)) is between 0 volt and the first high power supply voltage (VDDH). In the high-performance voltage level converter described in item 6 of the scope of patent application, the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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