TWM627595U - Voltage level conversion circuit exhibiting reduced power consumption - Google Patents

Abstract

The present invention proposes a potential conversion circuit for reducing power consumption, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), wherein the latch circuit (1) is a used to store the differential input signal; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the differential input signal of the potential conversion circuit.

The potential conversion circuit for reducing power consumption proposed in this work can not only accurately convert the first signal into a second signal, but also effectively reduce leakage current, thereby reducing power consumption.

Description

Potential conversion circuit for reducing power consumption

The present invention relates to a potential conversion circuit for reducing power consumption, especially composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), in order to obtain precise voltage level conversion and Electronic circuits that effectively reduce power consumption.

A potential conversion circuit is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential conversion circuit is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a prior art latch-type potential conversion circuit, which uses a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1), a A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) ) to form a potential conversion circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the first signal (V(IN)) is also at the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, in the same During the time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential conversion circuit is in a stable state, the latch type There is no static current generated in the potential conversion circuit. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential conversion circuit, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the output terminal The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention with each other, so the second signal (V(OUT)) is slower when it transitions to a logic low level. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a logic low level, The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS electrical The crystal ( MN1 ) and the second NMOS transistor ( MN2 ) are completely turned on or turned off, which will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND). Current increases power loss.

Furthermore, the performance of the latch-type potential conversion circuit is affected by the first high potential voltage (VDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type potential conversion circuit can operate normally is limited.

FIG. 2 shows another prior art mirror-type potential conversion circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and to The drain of the first PMOS transistor (MP1) makes the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in the saturation region, and its The gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential conversion circuit is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the potential conversion The performance of the circuit will not change much either. Therefore, the mirror-type potential conversion circuit can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a voltage is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1). a quiescent current path.

In view of this, the main purpose of this creation is to provide a potential conversion circuit with reduced power consumption, which can not only accurately and quickly convert a first signal into a second signal, but also can effectively reduce leakage current, thereby reducing power consumption. .

The present invention proposes a potential conversion circuit for reducing power consumption, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3), wherein the latch circuit (1) is a used to store the differential input signal; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used to provide the differential input signal of the potential conversion circuit.

The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has the advantages of simple circuit structure and the advantages of miniaturization of the device. efficiency, while also effectively reducing power loss.

1: Latch circuit

2: Output control circuit

3: Input circuit

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

I1: first inverter

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

MN6: sixth NMOS transistor

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

OUT: output terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Figure 1 shows the circuit diagram of the potential conversion circuit in the first prior art; Figure 2 shows the circuit diagram of the potential conversion circuit in the second prior art; Figure 3 shows the potential conversion for reducing power consumption according to the preferred embodiment of the present invention Circuit diagram of the circuit; FIG. 4 is a timing diagram of transient analysis of the first signal and the second signal in the preferred embodiment of the present invention.

According to the above purpose, the present invention proposes a potential conversion circuit for reducing power consumption, as shown in FIG. 3, which is composed of a latch circuit (1), an output control circuit (2) and an input circuit (3). composition, wherein, the latch circuit (1) is used to store the differential input signal; the output control circuit (2) is used to control the potential of the output signal of the potential conversion circuit; and the input circuit (3) is used for to provide the differential input signal of the potential conversion circuit; the latch circuit (1) consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , a first NMOS transistor (MN1), a second NMOS transistor (MN2), a fifth NMOS transistor (MN5) and a sixth NMOS transistor (MN6), wherein the first PMOS transistor The source of the crystal (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the A second PMOS transistor (MP2) has its source connected to the first high power supply voltage (VDDH), its gate connected to the third node (N3), and its drain connected to the second node (N2) ) is connected; the source of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), its gate is connected to the fourth node (N4), and its drain is connected to The third node (N3) is connected; the source of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4), and the gate is connected to the third node (N3), The drain electrode is connected to the fourth node (N4); the source electrode of the fifth NMOS transistor (MN5) is connected to the third node (N3), and the gate electrode is connected to the second input end (INB). ), and its drain is connected to the first node (N1); the source of the sixth NMOS transistor (MN6) is connected to the fourth node (N4), and its gate is connected to the first input terminal (IN), and its drain is the same as the second section point (N2) is connected; the output control circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the third PMOS transistor (MP3) The source is connected to the first high power supply voltage (VDDH), the gate is connected to the first input terminal (IN), and the drain is connected to the first node (N1); the fourth PMOS power The source of the crystal (MP4) is connected to the first high power supply voltage (VDDH), the gate is connected to the second input terminal (INB), and the drain is connected to the second node (N2); The input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the third NMOS transistor (MN3) ) is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); the fourth NMOS The source electrode of the transistor (MN4) is connected to the ground (GND), the gate electrode is connected to the second input terminal (INB), and the drain electrode is connected to the source electrode of the second NMOS transistor (MN2); The first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing an inverse of the first signal (V(IN)). phase signal; the first high power supply voltage (VDDH) is used to provide the first high potential voltage required by the potential conversion circuit; and the second high power supply voltage (VDDL) is used to provide the potential conversion circuit The required second high potential voltage, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) is 1.8 volts, The second high power supply voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is Corresponding waveforms between 0 volts and 1.8 volts.

Please refer to FIG. 3 again to explain the working principle of FIG. 3 as follows: Now consider the steady-state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic low level (0 volts): the first input terminal ( The logic low level on IN) is simultaneously transmitted to the input of the first inverter (I1), the third NMOS transistor (MN3), the sixth NMOS transistor (MN6) and the third PMOS transistor ( MP3) gate, so that both the third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are turned off (OFF), and the third PMOS transistor (MP3) is turned on (ON), at this time the The potential of the first node (N1) is pulled up to a high potential close to the first high potential voltage (VDDH); and the first inverter (I1) transmits the second high potential voltage (VDDL) to the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the gates of the fourth PMOS transistor (MP4) so that both the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are is turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). At this time, since the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are both turned on (ON), therefore , the potential of the third node (N3) will be pulled to a high potential, and the high potential of the third node (N3) will turn off the second PMOS transistor (MP2), the second NMOS transistor (MN2) ) is turned on, at this time, since both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are turned on, the potential of the fourth node (N4) will be pulled down to a logic low level ( 0 volts), and further, the low potential of the fourth node (N4) is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first NMOS transistor ( MN1) is turned off and the first PMOS transistor (MP1) is turned on. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off, therefore, the potential of the fourth node (N4) maintains a steady state value at a logic low level (0 volt). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a logic low level through a potential conversion circuit. The second signal of level (0 volt) is output from the output terminal (OUT).

Then consider the steady-state operation of the potential conversion circuit when the first signal (V(IN)) is at a logic high level (1.2 volts): the logic high level on the first input terminal (IN) is simultaneously transmitted to the first inverter the input terminal of the device (I1), the third NMOS transistor (MN3), the sixth NMOS transistor (MN6) and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3 ) and the sixth NMOS transistor (MN6) are turned on (ON), and the third PMOS transistor (MP3) is turned off (OFF); and the first inverter (I1) transmits a low level (0 volts) to the gates of the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN4) The crystal (MN5) is turned off (OFF), and the fourth PMOS transistor (MP4) is turned on (ON). At this time, since the fourth PMOS transistor (MP4) and the sixth NMOS transistor (MN6) are both turned on (ON), and the fourth NMOS transistor (MN4) is turned off (OFF), therefore, the potential of the fourth node (N4) will be pulled to a logic high level, and furthermore, the fourth node (N4) The high potential is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first PMOS transistor (MP1) is turned off and the first NMOS transistor (MN1) is turned on. , at this time, since the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on, the potential of the third node (N3) will be pulled down to a logic low level (0 volts) ), furthermore, the low potential of the third node (N3) is transmitted to the gate of the second PMOS transistor (MP2) and the second NMOS transistor (MN2), so that the second PMOS transistor (MP2) turned on, the second NMOS transistor (MN2) is turned off. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off, the sixth NMOS transistor (MN6), the Both the second PMOS transistor ( MP2 ) and the fourth PMOS transistor ( MP4 ) are turned on, so the potential of the fourth node ( N4 ) is maintained at a steady state value of a logic high level. Qualitatively speaking, first When the signal (V(IN)) is at a logic high level (1.2 volts), it is converted into a second signal with a high level (VDDH) through a potential conversion circuit, and is output from the output terminal (OUT).

To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal (V( When IN)) is the second high potential voltage (1.2 volts), the second signal (V(OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

Figure 4 shows the simulation results of Spice transient analysis of the potential conversion circuit for reducing power consumption proposed in this work. The simulation results confirm that the potential conversion circuit for reducing power consumption proposed in this work not only still remains The first signal can be quickly and accurately converted into a second signal, and the power loss can be effectively reduced.

Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1: Latch circuit

2: Output control circuit

3: Input circuit

N1: the first node

N2: second node

N3: The third node

N4: Fourth Node

I1: first inverter

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: the third NMOS transistor

MN4: Fourth NMOS transistor

MN5: Fifth NMOS transistor

MN6: sixth NMOS transistor

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

OUT: output terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A potential conversion circuit for reducing power consumption for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for converting a The drain of the first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the drain of a fifth NMOS transistor (MN5) are connected together; a second node (N2) is connected with The drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the drain of a sixth NMOS transistor (MN6) are connected together; a third node (N3 ) for the source of the fifth NMOS transistor (MN5), the drain of a first NMOS transistor (MN1), the gate of the second PMOS transistor (MP2) and a second NMOS transistor The gates of (MN2) are connected together; a fourth node (N4) is used for the source of the sixth NMOS transistor (MN6), the drain of a second NMOS transistor (MN2), the first The gate of the PMOS transistor (MP1) and the gate of a first NMOS transistor (MN1) are connected together; a first input terminal (IN) is coupled to the third PMOS transistor (MP3) and a first The gates of the three NMOS transistors (MN3) are used to provide a first signal (V(IN)); a second input terminal (INB) is coupled to the fourth PMOS transistor (MP4) and a fourth The gate of the NMOS transistor (MN4) is used to provide an inversion signal of the first signal (V(IN)); an output terminal (OUT) is coupled to the fourth node (N4) and used to output the the second signal (V(OUT)); A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) Inverted signal; a first high power supply voltage (VDDH), coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the The source of the fourth PMOS transistor (MP4) is used to provide the first high potential voltage required by the potential conversion circuit for reducing power consumption; a second high power supply voltage (VDDL) is used to provide the power consumption reducing circuit The second high potential voltage required by the potential conversion circuit, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH); a latch circuit (1), coupled to The first high power supply voltage (VDDH) is used to store the differential input signal; an output control circuit (2) is coupled to the latch circuit (1) for controlling the output signal of the potential conversion circuit. electric potential; and an input circuit (3) coupled to the first input end (IN) for providing a differential input signal. The potential conversion circuit for reducing power consumption as described in claim 1, wherein the latch circuit (1) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); A second PMOS transistor (MP2) whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the third node (N3), and whose drain is connected to the second node ( N2) is connected; a first NMOS transistor (MN1), its source is connected to the drain of the third NMOS transistor (MN3), its gate is connected to the second node (N2), and its drain Then it is connected to the first node (N1); a second NMOS transistor (MN2), its source is connected to the drain of the fourth NMOS transistor (MN4), and its gate is connected to the first node ( N1), and its drain is connected to the second node (N2); a fifth NMOS transistor (MN5), its source is connected to the third node (N3), and its gate is connected to the second an input terminal (INB) whose drain is connected to the first node (N1); and a sixth NMOS transistor (MN6) whose source is connected to the fourth node (N4) and whose gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The potential conversion circuit for reducing power consumption as described in claim 2, wherein the output control circuit (2) comprises: a third PMOS transistor (MP3), the source of which is connected to the first high power supply voltage (VDDH), the gate of which is connected to the first input terminal (IN), and the drain of which is connected to the first node (N1); and A fourth PMOS transistor (MP4), whose source is connected to the first high power supply voltage (VDDH), whose gate is connected to the second input terminal (INB), and whose drain is connected to the second node (N2) is connected. The potential conversion circuit for reducing power consumption as described in claim 3, wherein the input circuit (3) comprises: a third NMOS transistor (MN3), the source of which is connected to the ground (GND), and the gate of which is connected to the ground (GND). connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), its source is connected to the ground (GND) ), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1), coupled to The first input terminal (IN) is used to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)). The potential conversion circuit for reducing power consumption as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The potential conversion circuit for reducing power consumption as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The potential conversion circuit for reducing power consumption as described in claim 4, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

Images