TWM643204U - Level conversion circuit for converting a small-amplitude input signal - Google Patents

Abstract

This creation proposes a potential converter for converting small-amplitude input signals, which is composed of a first node (N1), a second node (N2), a third node (N3), a first input terminal (IN), a second input terminal (INB), an output terminal (OUT), a first high power supply voltage (VDDH), a second high power supply voltage (VDDL), an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) It is used to provide differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); the output control circuit (3) is used to control the potential of the output signal of the potential converter.

The potential converter proposed by the invention for converting small-amplitude input signals can not only accurately convert a first signal into a second signal, but also effectively reduce power loss.

Description

Potential shifters for converting small-amplitude input signals

This invention relates to a potential converter for converting small-amplitude input signals, especially an electronic circuit composed of an input circuit (1), a latch circuit (2) and an output control circuit (3) in order to obtain precise voltage level conversion and effectively reduce power loss.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC for short). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

Fig. 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor, P channel metal oxide semiconductor) transistor (MP1), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN1) N2) and an inverter (INV) to form a potential converter circuit for converting a small-amplitude input signal, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the potential of the input voltage (V(IN)) is also between the ground (GND) and the second high potential voltage (VDDL). The input voltage (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) Pole (gate). Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the level shifter is in a stable state, no static current is generated in the latch type level shifter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down (pull down) and the first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up (pull up) and the second PMOS transistor (MP2) is turned off; moreover, when the first NMOS transistor (MN 1) When the second NMOS transistor (MN2) is turned on, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up and the first PMOS transistor (MP1) is turned off. Therefore, there will not be a current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional level converter, when the second PMOS transistor (MP2) is close to on (or off) and the second NMOS transistor (MN2) is close to off (or on), there is a contention phenomenon for pulling up and down the potential on the output node (OUT), so the output voltage signal (V(OUT)) is slow when it changes to a low potential. In addition, consider that when the input voltage (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low potential, so that the second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantaneously transitioned to 1.8 volts, the lower input voltage (V(IN)) during the transition may not allow the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and The second NMOS transistor ( MN2 ) is fully turned on or completely turned off, which will cause a static current between the first high potential voltage ( VDDH ) and the ground ( GND ), and the static current will increase power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high potential voltage (VDDH), because the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are the first high potential voltage (VDDH), while the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type level shifter can operate normally is limited.

Figure 2 shows another prior art mirror-type potential converter circuit. The potential converter connects the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) together and to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the performance of the potential converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, an a quiescent current path.

In view of this, the main purpose of this invention is to propose a potential converter for converting small-amplitude input signals, which can not only accurately and quickly convert the first signal into a second signal, but also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power loss.

This creation proposes a potential converter for converting small-amplitude input signals, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store the differential input signal from the input circuit (1); the output control circuit (3) is used to control the potential of the output signal of the potential converter. .

It is confirmed by the simulation results that the potential converter proposed by the invention for converting small-amplitude input signals can not only convert a first signal into a second signal accurately and quickly, but also effectively reduce power loss.

1: Input circuit

2: Latch circuit

3: Output control circuit

N1: the first node

N2: second node

N3: the third node

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

MN1: the first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

GND: ground

IN: the first input terminal

V(IN): the first signal

INB: the second input terminal

I1: the first inverter

OUT: output terminal

V(OUT): the second signal

VDDH: the first high power supply voltage

VDDL: The second highest power supply voltage

Figure 1 is a circuit diagram showing a potential converter in the first prior art;

Figure 2 is a circuit diagram showing a potential converter in the second prior art;

Fig. 3 is a circuit diagram showing a potential converter for converting a small-amplitude input signal according to a preferred embodiment of the invention;

According to the above purpose, this creation proposes a method for converting small-amplitude input signals The potential converter, as shown in Figure 3, is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) is used to provide the first signal (V(IN)) and the inversion signal of the first signal (V(IN)); it is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the first NMOS The source of the transistor (MN1) is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the third node (N3); the first inverter (I1) is coupled to the first input terminal (IN) for Accepting the first signal (V(IN)), and providing a signal inverse to the first signal (V(IN)); the latch circuit (2) is used to save the differential input signal from the input circuit (1); it is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2) and a third NMOS transistor (MN3), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), and The gate is connected to the third node (N3), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the third node (N3), and its gate is connected to the first input terminal (IN), and Its drain is connected to the second node (N2); the output control circuit (3) is used to control the potential of the output signal of the potential converter; it is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), and its gate is connected to the first output input terminal (IN), and its drain is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the level converter, and the second high power supply voltage (VDDL) is used to provide the potential The second high power supply voltage required by the converter, the level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH), the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to FIG. 3 again, and the working principle of FIG. 3 is explained according to the working mode of the potential converter: Now consider the steady-state operation of the potential converter when the first signal (V(IN)) is at a logic low level (“0”): the logic low level (“0”) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the first NMOS transistor (MN1), the third NMOS transistor (MN3) and the third PMOS transistor (MP3) gate, so that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are all off, the third PMOS transistor (MP3) is turned on, and the first inverter (I1) transmits a logic high level ("VDDL") to the gates of the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned on, and the fourth PMOS transistor (MP4) At this time, since the second NMOS transistor (MN2) is turned on, the potential of the third node (N3) will be pulled down to a logic low level ("0"), and the logic low level ("0") of the third node (N3) will make the first PMOS transistor (MP1) turn on, and the potential of the first node (N1) will be pulled up to a logic high level ("VDDH"); moreover, because the second NMOS transistor (MN2) is turned on, and the The third NMOS transistor (MN3) is turned off, therefore, the potential of the third node (N3) will maintain at a logic low level (“0”), therefore, the potential of the output terminal (OUT) also maintains a steady state value at a logic low level (“0”).

Considering again that when the first signal (V(IN)) is at a logic high level (“VDDL”), the steady-state operation of the potential converter: the logic high level (“VDDL”) on the first input terminal (IN) is transmitted to the input terminal of the first inverter (I1), the gates of the first NMOS transistor (MN1), the third NMOS transistor (MN3) and the third PMOS transistor (MP3), so that the first NMOS transistor (MN1), the third Both NMOS transistors (MN3) are turned on, the third PMOS transistor (MP3) is turned off, and the first inverter (I1) transmits a logic low level ("0") to the gates of the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned off, and the fourth PMOS transistor (MP4) is turned on. At this time, because the first NMOS transistor (MN1) is turned on, the first The potential of the node (N1) will be pulled down to a logic low level ("0"), and the logic low level ("0") on the first node (N1) is transmitted to the gate of the second PMOS transistor (MP2), so that the second PMOS transistor (MP2) is turned on; since the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the third NMOS transistor (MN3) are all turned on, and the second NMOS transistor (MN2) is turned off Therefore, the potential of the third node (N3) will be pulled up to a logic high level ("VDDH"); and the logic high level ("VDDH") of the third node (N3) will cause the first PMOS transistor (MP1) to be turned off. It will also be maintained at a logic high level (“VDDH”), therefore, the potential of the output terminal (OUT) will also be maintained at a steady state value of a logic high level (“VDDH”).

In summary, because the first PMOS transistor (MP1), the first NMOS transistor (MN1) or the second PMOS transistor (MP2), the second NMOS transistor (MN2) can be conduct simultaneously for a short period of time. The present invention reduces contention by cutting off the pull-up path of the output terminal through the third NMOS transistor (MN3). When the second NMOS transistor (MN2) is turned on (that is, the pull-down path is enabled), the third NMOS transistor (MN3) will cut off the pull-up path to avoid competition between the pull-up path and the pull-down path, so delay time can be greatly reduced, and short-circuit power loss can be eliminated.

The potential converter proposed in this creation can be verified by the Spice transient analysis simulation results. The potential converter proposed in this creation for converting small-amplitude input signals can not only quickly and accurately convert the first signal into a second signal, but also effectively reduce power loss.

While the invention has particularly disclosed and described selected preferred embodiments, those skilled in the art will appreciate that any possible changes in form or detail would not depart from the spirit and scope of the invention. Therefore, all changes in the relevant technical categories are included in the patent application scope of this creation.

1: Input circuit

2: Latch circuit

3: Output control circuit

N1: the first node

N2: second node

N3: the third node

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

MN1: the first NMOS transistor

MN2: The second NMOS transistor

MN3: The third NMOS transistor

GND: ground

IN: the first input terminal

V(IN): the first signal

INB: the second input terminal

I1: the first inverter

OUT: output terminal

V(OUT): the second signal

VDDH: the first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A potential converter for converting a small-amplitude input signal, for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3), the drain of a first NMOS transistor (MN1) and the gate of a second PMOS transistor (MP2); A second node (N2) for connecting the drains of a second PMOS transistor (MP2), a fourth PMOS transistor (MP4) and a third NMOS transistor (MN3) together; a third node (N3) for connecting the drain of a second NMOS transistor (MN2), the source of the third NMOS transistor (MN3) and the gate of the first PMOS transistor (MP1); a first input terminal (IN), coupled to the gate of the third PMOS transistor (MP3), the gate of the third NMOS transistor (MN3), the gate of the first NMOS transistor (MN1) and the input terminal of a first inverter (I1), for providing the first signal (V(IN)); a second input terminal (INB), coupled to the gate of the fourth PMOS transistor (MP4), the gate of the second NMOS transistor (MN2) and the output terminal of the first inverter (I1), for providing an inverted signal of the first signal (V(IN)); an output terminal (OUT), coupled to the third node (N3), for outputting the second signal (V(OUT)); A first high power supply voltage (VDDH), coupled to the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4), to provide the potential for converting small-amplitude input signals The first high potential voltage required by the converter; A second high power supply voltage (VDDL), used to provide the second high potential voltage required by the potential converter for converting small-amplitude input signals, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH); An input circuit (1), coupled to the first input terminal (IN), for providing differential input signals; a latch circuit (2) for holding the differential input signal from the input circuit (1); and An output control circuit (3), used to control the potential of the output signal of the potential converter for converting small-amplitude input signals. The potential converter for converting small-amplitude input signals as described in item 1 of the scope of patent application, wherein the input circuit (1) includes: A first NMOS transistor (MN1), its source connected to the ground (GND), its gate connected to the first input terminal (IN), and its drain connected to the first node (N1); a second NMOS transistor (MN2), its source connected to ground (GND), its gate connected to the second input terminal (INB), and its drain connected to the third node (N3); and A first inverter (I1), coupled to the first input terminal (IN), is used to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)). The potential converter for converting small-amplitude input signals as described in item 2 of the scope of the patent application, wherein the latch circuit (2) includes: A first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source connected to the first high power supply voltage (VDDH), its gate connected to the first node (N1), and its drain connected to the second node (N2); and A third NMOS transistor (MN3), its source is connected to the third node (N3), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The potential converter for converting small-amplitude input signals as described in item 3 of the scope of the patent application, wherein the output control circuit (3) includes: a third PMOS transistor (MP3), its source connected to the first high power supply voltage (VDDH), its gate connected to the first input terminal (IN), and its drain connected to the first node (N1); and A fourth PMOS transistor (MP4), its source connected to the first high power supply voltage (VDDH), its gate connected to the second input terminal (INB), and its drain connected to the second node (N2). The potential converter for converting a small-amplitude input signal as described in claim 1 of the patent application, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The potential converter for converting a small-amplitude input signal as described in item 5 of the scope of the patent application, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The potential converter for converting small-amplitude input signals as described in item 2 of the scope of the patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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