TWM531694U - Voltage level converter - Google Patents

Description

Voltage level converter

The present invention relates to a voltage level converter, especially comprising an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3) for obtaining a precise voltage level. An electronic circuit that converts and effectively reduces power consumption.

A voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low voltage operation signal into a high voltage operation signal. .

Figure 1 shows a prior art latch-type voltage level converter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor (MP1). a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverting phase The inverter (INV) constitutes a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the input voltage (V(IN)) The potential is also between ground (GND) and the second high potential voltage (VDDL). The input voltage (V(IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. because Thus, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned ON. In addition, due to the cross-coupled manner of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the lock type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned "ON", the gate potential of the first PMOS transistor (MP1) is pulled down and Making the first PMOS transistor (MP1) turn on, so as to pull up the gate potential of the second PMOS transistor (MP2) to turn off the second PMOS transistor (MP2); further, when the first NMOS transistor When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS is pulled up. The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-described conventional voltage level converter is in the process of approaching (or turning off) the second PMOS transistor (MP2) and approaching (or turning on) the second NMOS transistor (MN2), The pull-up and pull-down of the potential on the output node (OUT) have a contention, so the output voltage signal (V(OUT)) is slower when it is converted to a low potential. Further, considering that when the input voltage (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantaneously converted to 1.8 volts, the lower input voltage (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or completely turned off, which causes a static current between the first high potential voltage (VDDH) and ground (GND). Will increase the power loss.

Furthermore, the performance of the latch type voltage level converter is affected by the first high potential voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The voltage is the first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type voltage level converter operate normally is limited.

Figure 2 is a diagram showing another prior art mirror type voltage level converter circuit for connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Connected to the drain of the first PMOS transistor (MP1) together such that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is The saturation region, and its gate voltage, causes the saturation current to be equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror type voltage level converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are electrically charged. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. As such, a quiescent current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of the present invention is to propose a voltage level converter that not only accurately and quickly converts a first signal into a second signal, but also effectively reduces leakage current, thereby reducing power consumption.

The present invention proposes a voltage level converter which is composed of an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3), wherein the amplitude conversion circuit (1) Is used as a potential conversion; the potential control transistor (2) is used to pull up the voltage level of the first node (N1); and the potential control transistor (3) is used to pull up the first The voltage level of the two nodes (N2).

It is confirmed by the simulation results that the voltage level converter proposed by the present invention not only can accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and miniaturization of the device. At the same time, it can effectively reduce power loss.

1‧‧‧Amplitude conversion circuit

2‧‧‧potential control transistor

3‧‧‧potential control transistor

I1‧‧‧First Inverter

N1‧‧‧ first node

N2‧‧‧ second node

MP1‧‧‧First PMOS transistor

MP2‧‧‧second PMOS transistor

MP3‧‧‧ Third PMOS transistor

MP4‧‧‧fourth PMOS transistor

MN1‧‧‧First NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧ Third NMOS transistor

MN4‧‧‧4th NMOS transistor

IN‧‧‧ first input

V(IN)‧‧‧first signal

INB‧‧‧ second input

OUT‧‧‧ output

GND‧‧‧

V(OUT)‧‧‧second signal

VDDH‧‧‧first high potential voltage

VDDL‧‧‧ second high potential voltage

1 is a circuit diagram showing a voltage level converter in a first prior art; FIG. 2 is a circuit diagram showing a voltage level converter in a second prior art; and FIG. 3 is a voltage level showing a preferred embodiment of the present invention. a circuit diagram of a quasi-converter; FIG. 4 is a timing diagram showing transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

According to the above purpose, the present invention proposes a voltage level converter, as shown in FIG. 3, which is composed of an amplitude conversion circuit (1), a potential control transistor (2) and a potential control transistor (3). The amplitude conversion circuit (1) is used for potential conversion; the potential control transistor (2) is used to pull up the voltage level of the first node (N1); the potential control transistor (3) is used to pull up the voltage level of the second node (N2); the amplitude conversion circuit (1) is coupled to the first power voltage and ground (GND) for use as a potential conversion It is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a third NMOS transistor. (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the source of the first PMOS transistor (MP1) is connected to the first high potential voltage (VDDH) a gate connected to the second node (N2) and a drain connected to the first node (N1); a source of the second PMOS transistor (MP2) connected to the first high potential voltage ( VDDH), a gate is connected to the first node (N1), and a drain is connected to the second node (N2); a source of the first NMOS transistor (MN1) is connected to the third NMOS transistor (MN3) a drain whose gate is connected to the second node (N2) and whose drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the first a drain of a four NMOS transistor (MN4) having a gate connected to the first node (N1) and a drain connected to the second node (N2); the third NMOS transistor (MN3) The source is connected to the ground (GND), the gate thereof is connected to the first input terminal (IN), and the drain thereof is connected to the source of the first NMOS transistor (MN1); The source of the NMOS transistor (MN4) is connected to the ground (GND), the gate thereof is connected to the second input terminal (INB), and the drain thereof is connected to the source of the second NMOS transistor (MN2). And the first inverter (I1) is configured to receive the first signal (V(IN)) and provide the second input terminal (INB) to be inverted from the first signal (V(IN)) The potential control transistor (2) is composed of a third PMOS transistor (MP3) whose source is connected to a first high potential voltage (VDDH) whose gate is connected to the first input terminal ( IN), and its drain is connected to the first node (N1); the potential control transistor (3) is composed of a fourth PMOS transistor (MP4) whose source is connected to the first high potential a voltage (VDDH) whose gate is connected to the second input terminal (INB) and whose drain is connected to the second node (N2); the first power supply voltage is used to provide the voltage level converter a first high potential voltage (VDDH) required to provide a second high potential voltage (VDDL) required by the voltage level converter, the second high potential voltage (VDDL) The standard is less than the first high potential voltage (V DDH), the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high potential voltage (VDDH) Is 1.8 volts, and the second high potential voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT) )) is the corresponding waveform between 0 volts and 1.8 volts. .

Please refer to Figure 3 again. Now consider the steady-state operation of the voltage level converter when the first signal (V(IN)) is low (0 volts): the low potential at the first input (IN) Transmitting to the input of the first inverter (I1), the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3) is turned off, the third PMOS The transistor (MP3) is turned on, at which time the potential of the first node (N1) is pulled up to a high potential; and the first inversion The device (I1) transmits a second high potential voltage (VDDL) to the gates of the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4) such that the fourth NMOS transistor (MN4) is turned on, and the fourth PMOS is turned on The crystal (MP4) is turned off, the second PMOS transistor (MP2) is turned off and the second NMOS transistor (MN2) is turned on due to the high potential of the first node (N1), at this time, due to the second NMOS transistor (MN2) And the fourth NMOS transistor (MN4) is turned on, therefore, the potential of the second node (N2) is pulled down to a low potential (0 volt) steady state value, and further, the second node (N2) The upper low potential is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1) such that the first PMOS transistor (MP1) is turned on and the first NMOS transistor (MN1) is turned off due to the A PMOS transistor (MP1) and a third PMOS transistor (MP3) are both turned on, and the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off, so that the potential of the first node (N1) is Is pulled up to a first high potential voltage (VDDH), and since both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are turned on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are all off, therefore, Potential of the second node (N2) will be maintained at a low potential (0 volts), and therefore, the output terminal (OUT) will be pulled down to the potential of a low potential (0 volt) steady-state value. In other words, when the first signal (V(IN)) is low (0 volts), it is converted into a second signal with a low potential (0 volt) by a voltage level converter, and is outputted by the output terminal (OUT).

Considering the steady state operation of the voltage level converter when the first signal (V(IN)) is the second high potential voltage (1.2 volts): the second high potential voltage at the first input (IN) (VDDL) Simultaneously transmitting to the input terminal of the first inverter (I1), the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3), so that the third NMOS transistor (MN3) is turned on, The three PMOS transistors (MP3) are turned off, and the first inverter (I1) transmits a low potential to the gates of the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4), so that the fourth NMOS is Crystal (MN4) is turned off, the fourth PMOS transistor (MP4) is turned on, and at this time, since the fourth PMOS transistor (MP4) is turned on, the potential of the second node (N2) is pulled up to a high potential; and the second The high potential of the node (N2) causes the first PMOS transistor (MP1) to be turned off and the first NMOS transistor (MN1) to be turned on, at which time both the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are turned on. Therefore, the potential of the first node (N1) is pulled down to a low potential (0 volt) steady state value, and the low potential at the first node (N1) is transferred to the second PMOS transistor. (MP2) and the gate of the second NMOS transistor (MN2) such that the second PMOS transistor (MP2) is turned on and the second NMOS transistor (MN2) is turned off due to the second PMOS transistor (MP2) and the fourth PMOS The transistor (MP4) is turned on, and the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off. Therefore, the potential of the second node (N2) is maintained at the first high potential voltage (VDDH). While the potential of the first node (N1) is maintained at a low potential (0 volts), the potential of the output terminal (OUT) is pulled up to a steady state value of a first high potential voltage (VDDH). In a word, when the first signal (V(1N)) is the second high potential voltage (1.2 volts), it is converted into a second signal having a first high potential voltage (1.8 volts) by the voltage level converter, and the output is output. End (OUT) output.

In summary, when the first signal (V(IN)) is low (0 volts), the second signal (V(OUT)) is also low (0 volts); and the first signal (V(IN)) When the second high potential voltage (1.2 volts) is, the second signal (V(OUT)) is the first high potential voltage (1.8 volts). Thus, the purpose of voltage level conversion is achieved.

The result of the Spice transient analysis of the voltage level converter proposed by this work, as shown in Fig. 4, can be confirmed by the simulation results. The voltage level converter proposed by the present invention can not only be fast and accurate. The first signal is converted into a second signal, and the power loss can be effectively reduced.

Although the present invention has been particularly described and described in detail, it is understood by those skilled in the art that the present invention may be modified in any form or detail without departing from the spirit and scope of the present invention. Therefore, all changes in the relevant technical scope are included in the scope of the patent application of this creation.

1‧‧‧Amplitude conversion circuit

2‧‧‧potential control transistor

3‧‧‧potential control transistor

I1‧‧‧First Inverter

N1‧‧‧ first node

N2‧‧‧ second node

MP1‧‧‧First PMOS transistor

MP2‧‧‧second PMOS transistor

MP3‧‧‧ Third PMOS transistor

MP4‧‧‧fourth PMOS transistor

MN1‧‧‧First NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧ Third NMOS transistor

MN4‧‧‧4th NMOS transistor

IN‧‧‧ first input

V(IN)‧‧‧first signal

INB‧‧‧ second input

OUT‧‧‧ output

GND‧‧‧

V(OUT)‧‧‧second signal

VDDH‧‧‧first high potential voltage

VDDL‧‧‧ second high potential voltage

Claims (7)

A voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for using a first a drain of a PMOS transistor (MP1), a gate of a second PMOS transistor (MP2), a drain of a first NMOS transistor (MN1), a drain of a third PMOS transistor (MP3), and a drain The gates of the second NMOS transistor (MN2) are connected together; a second node (N2) is used to gate the drain of a second PMOS transistor (MP2) and the gate of a first PMOS transistor (MP1) a pole, a drain of a second NMOS transistor (MN2), a drain of a fourth PMOS transistor (MP4), and a gate of a first NMOS transistor (MN1) are connected together; a first input terminal ( IN), coupled to a third PMOS transistor (MP3) and a third NMOS transistor (MN3) gate for providing a first signal (V(IN)); a second input terminal (INB) a gate coupled to the fourth PMOS transistor (MP4) and a fourth NMOS transistor (MN4) for providing an inverted signal of the first signal (V(IN)); an output terminal ( OUT), coupled to the second node (N2) for outputting the second signal (V(OUT)); a first Voltage to provide a desired voltage level of a first high potential voltage converter (the VDDH); a second power supply voltage for providing a second high potential voltage (VDDL) required by the voltage level converter, the potential of the second high potential voltage (VDDL) being less than the potential of the first high potential voltage (VDDH) a first inverter (I1) coupled to the first input terminal (IN) for accepting the first signal (V(IN)) and providing a first signal (V(IN) An inverted signal; an amplitude conversion circuit (1) coupled to the first supply voltage and ground (GND) for use as a potential conversion; a potential control transistor (2) coupled to the first An input terminal (IN) for pulling up the voltage level of the first node (N1); and a potential control transistor (3) coupled to the second input terminal (INB) for pulling up the first The voltage level of the two nodes (N2). The voltage level converter according to claim 1, wherein the amplitude conversion circuit (1) comprises: a first PMOS transistor (MP1) whose source is connected to the first high potential voltage (VDDH), The gate is connected to the second node (N2), and the drain is connected to the first node (N1); a second PMOS transistor (MP2) whose source is connected to the first high potential voltage ( VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2); a first NMOS transistor (MN1) whose source is connected to the third a drain of the NMOS transistor (MN3) having a gate connected to the second node (N2) and a drain connected to the first node (N1); a second NMOS transistor (MN2) having a source connected to the drain of the fourth NMOS transistor (MN4), a gate connected to the first node (N1), and a drain connected to the second a node (N2) connected; a third NMOS transistor (MN3) having a source connected to ground (GND), a gate connected to the first input terminal (IN), and a drain connected to the first The source of the NMOS transistor (MN1) is connected; a fourth NMOS transistor (MN4) has a source connected to ground (GND), a gate connected to the second input terminal (INB), and a drain And connected to the source of the second NMOS transistor (MN2); and a first inverter (I1) for receiving the first signal (V(IN)) and providing a first signal (V(IN)) Inverted signal. The voltage level converter according to claim 2, wherein the potential control transistor (2) is composed of a third PMOS transistor (MP3) whose source is connected to the first high potential voltage ( VDDH) has its gate connected to the first input (IN) and its drain connected to the first node (N1). The voltage level converter according to claim 3, wherein the potential control transistor (3) is composed of a fourth PMOS transistor (MP4) whose source is connected to the first high potential voltage ( VDDH) has its gate connected to the second input (INB) and its drain connected to the second node (N2). The voltage level converter of claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high potential voltage (VDDL). The voltage level converter of claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high potential voltage (VDDH). The voltage level converter of claim 6, wherein the voltage source of the first inverter (I1) is the second high potential voltage (VDDL).