TWM565915U - Voltage level converter - Google Patents

Abstract

This creation proposes a voltage level converter, which is composed of a pull-up transistor pair (1), a latch (2), a pull-down transistor pair (3), and an input transistor pair (4). Composition, wherein the pull-up transistor pair (1) is used to pull the potential of the first node (N1) and the second node (N2) to a second high potential voltage (VDDL); the latch (2) is used for storing the input signal received by the input transistor pair (4); the pull-down transistor pair (3) is used for the first node (N1) and the second node (N2) The potential is pulled down to ground (GND); the input transistor pair (4) is used to provide the first signal (V (IN)) and the inverted signal of the first signal (V (IN)).

The voltage level converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device, and it can also effectively reduce leakage. Current, which reduces power consumption.

Description

Voltage level converter

This creation is about a voltage level converter, especially using a pull-up transistor pair (1), a latch (2), a pull-down transistor pair (3) and an input transistor pair (4) The electronic circuit is composed to obtain accurate voltage level conversion and effectively reduce power consumption.

The voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the voltage level converter is responsible for converting low-voltage working signals into high-voltage working signals. .

FIG. 1 shows a latch-type voltage level converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1 ), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter Voltage converter (INV) to form a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the first signal (V (IN) ) Is also between ground (GND) and the second high potential voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. . because Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-mentioned conventional voltage level converter is approaching (or turning off) the second PMOS transistor (MP2) and the process of turning off (or turning on) the second NMOS transistor (MN2). There is a phenomenon of contention between the pull-up and pull-down of the potential at the output terminal (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) And the second NMOS transistor (MN2) is completely turned on or completely turned off, so that there will be a static current between the first high potential voltage (VDDH) and ground (GND), and this static current will increase the power Loss.

In addition, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH), because the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The voltage is the first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited.

Figure 2 shows a mirrored voltage level converter circuit, which is one of the other prior art. The voltage level converter is connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The first PMOS transistor (MP1) is in The saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirrored voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate electrodes of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a voltage level converter, which can not only accurately and quickly convert a first signal into a second signal, but also effectively reduce leakage current and thus reduce power consumption.

This creation proposes a voltage level converter, which is composed of a pull-up transistor pair (1), a latch (2), a pull-down transistor pair (3), and an input transistor pair (4). Composition, wherein the pull-up transistor pair (1) is used to pull the potential of the first node (N1) and the second node (N2) to a second high potential voltage (VDDL); the latch (2) is used to save the input signal received by the input transistor; the pull-down transistor pair (3) is used to pull the potential of the first node (N1) and the second node (N2) to ground (GND); The input transistor pair (4) is used to provide the first signal (V (IN)) and the inverted signal of the first signal (V (IN)).

The simulation results confirm that the voltage level converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. It can also effectively reduce power loss.

1‧‧‧Pull-up transistor pair

2‧‧‧ latch

3‧‧‧ pull down crystal pair

4‧‧‧ Input transistor pair

N1‧‧‧First Node

N2‧‧‧Second Node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧Fifth NMOS transistor

MN6‧‧‧Sixth NMOS transistor

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

OUT‧‧‧output

I1‧‧‧first inverter

GND‧‧‧ Ground

VDDH‧‧‧The first high potential voltage

VDDL‧‧‧Second High Voltage

Fig. 1 is a circuit diagram showing a voltage level converter in the first prior art; Fig. 2 is a circuit diagram showing a voltage level converter in the second prior art; Fig. 3 is a circuit diagram showing a voltage level converter of the preferred embodiment of the present invention; Fig. 4 is a timing analysis diagram of the first signal and the second signal of the preferred embodiment of the present invention.

According to the above purpose, this creation proposes a voltage level converter, as shown in Figure 3, which consists of a pull-up transistor pair (1), a latch (2), and a pull-down transistor pair ( 3) and an input transistor pair (4), wherein the pull-up transistor pair (1) is used to pull the potential of the first node (N1) and the second node (N2) to the The second high potential voltage (VDDL); the latch (2) is used to save the differential input signal received by the input transistor pair (4); the pull-down transistor pair (3) is used to connect the The potentials of the first node (N1) and the second node (N2) are pulled down to ground (GND); the input transistor pair (4) is used to provide the first signal (V (IN)) and the first The inverted signal of the signal (V (IN)); the pull-up transistor pair (1) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), where the third The source of the PMOS transistor (MP3) is connected to the second high potential voltage (VDDL), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1). ; The source of the fourth PMOS transistor (MP4) is connected to the second high-potential transistor; (VDDL), whose gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the latch (2) is a first PMOS transistor ( MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the source of the first PMOS transistor (MP1) is connected To the first high potential voltage (VDDH), its gate is connected to the second node (N2), and its drain A source is connected to the first node (N1); a source of the second PMOS transistor (MP2) is connected to the first high potential voltage (VDDH); a gate is connected to the first node (N1); The drain is connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), and the gate is connected to the first node. Two nodes (N2), and its drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4), which The gate is connected to the first node (N1), and its drain is connected to the second node (N2); the pull-down transistor pair (3) is composed of a fifth NMOS transistor (MN5) and a A sixth NMOS transistor (MN6), wherein the source of the fifth NMOS transistor (MN5) is connected to the ground (GND), the gate of the fifth NMOS transistor (MN5) is connected to the first input terminal (IN), and the drain thereof Is connected to the first node (N1); the source of the sixth NMOS transistor (MN6) is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is Connected to the second node (N2); the input transistor pair (4) is connected by a third An NMOS transistor (MN3), a fourth NMOS transistor (MN4), and a first inverter (I1), wherein the source of the third NMOS transistor (MN3) is connected to the ground (GND), Its gate is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); the source of the fourth NMOS transistor (MN4) is connected to ground (GND), whose gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and the first inverter (I1) is Coupled to the first input terminal (IN) for receiving the first signal (V (IN)), and providing the second input terminal (INB) with an inversion with the first signal (V (IN)) Signal; the first power supply voltage is used to provide the electricity A first high-potential voltage (VDDH) required by the voltage level converter. The second power supply voltage is used to provide a second high-potential voltage (VDDL) required by the voltage-level converter. The level of (VDDL) is less than the level of the first high potential voltage (VDDH). The first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is between 0 volts and Corresponding waveform between 1.8 volts, the first high potential voltage (VDDH) is 1.8 volts, the second high potential voltage (VDDL) is 1.2 volts, and the first signal (V (IN)) is between 0 volts and For a rectangular wave between 1.2 volts, the second signal (V (OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again. Now consider the steady-state operation of the voltage level converter when the first signal (V (IN)) is low (0 volts): the low potential on the first input (IN) is simultaneously To the input of the first inverter (I1), the third NMOS transistor (MN3), the fifth NMOS transistor (MN5), and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor The crystal (MN1), the fifth NMOS transistor (MN5) are turned off, and the third PMOS transistor (MP3) is turned on. At this time, the potential of the first node (N1) is pulled up to a voltage close to the second high potential ( VDDL); and the first inverter (I1) transmits the second high-potential voltage (VDDL) to the fourth NMOS transistor (MN4), the sixth NMOS transistor (MN6), and the fourth PMOS transistor ( MP4) gate, so that the fourth NMOS transistor (MN4), the sixth NMOS transistor (MN6) are turned on, the fourth PMOS transistor (MP4) is turned off, at this time the potential of the second node (N2) Is pulled to ground (GND); the second PMOS transistor (MP2) is turned off and the second NMOS transistor (MN2) is turned on due to the high potential of the first node (N1); at this time, due to the second NMOS Transistor (MN2), fourth NMOS transistor (M N4) and the sixth NMOS transistor (MN6) are both turned on. Therefore, the potential of the second node (N2) will be pulled down to a steady state value of a low potential (0 volts), and the second node ( N2) is transferred to the gate of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that The first PMOS transistor (MP1) is turned on and the first NMOS transistor (MN1) is turned off. Because the first PMOS transistor (MP1) is turned on, the first NMOS transistor (MN1) and the third NMOS transistor ( MN3) are all turned off, so the potential of the first node (N1) will be pulled up to a first high potential voltage (VDDH), and because the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) And the sixth NMOS transistor (MN6) are both on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both off, so the potential of the second node (N2) will be maintained at a low potential (0 volts) ), That is, the potential of the output terminal (OUT) is pulled down to a steady state value of a low potential (0 volts). In other words, when the first signal (V (IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) by a voltage level converter and output from the output terminal (OUT).

Consider again the steady-state operation of the voltage level converter when the first signal (V (IN)) is the second high potential voltage (1.2 volts): the second high potential voltage (VDDL) at the first input (IN) ) Are simultaneously transmitted to the input terminal of the first inverter (I1), the third NMOS transistor (MN3), the fifth NMOS transistor (MN5), and the gate of the third PMOS transistor (MP3), so that the third The NMOS transistor (MN3), the fifth NMOS transistor (MN5) are all on, the third PMOS transistor (MP3) is off, and the first inverter (I1) transmits a low potential to the fourth NMOS transistor (MN4), the gates of the sixth NMOS transistor (MN6) and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4), the sixth NMOS transistor (MN6) are turned off, and the first The four PMOS transistors (MP4) are turned on. At this time, because the fourth PMOS transistor (MP4) is turned on, the potential of the second node (N2) will be pulled up to a high potential close to the second high potential voltage (VDDL); The high potential of the second node (N2) causes the first PMOS transistor (MP1) to be turned off and the first NMOS transistor (MN1) to be turned on. At this time, due to the first NMOS transistor (MN1) and the third NMOS transistor The crystals (MN3) are all on, so The first node (N1) will be pulled down to the potential of a low potential (0 volt). Furthermore, the first The low potential at the node (N1) is transmitted to the gates of the second PMOS transistor (MP2) and the fourth NMOS transistor (MN4), so that the second PMOS transistor (MP2) is turned on and the second NMOS transistor (MP2) is turned on. MN2) is turned off. Because both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned on, the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off. Therefore, the second node The potential of (N2) will be pulled up to the first high potential voltage (VDDH), while the potential of the first node (N1) is maintained at a low potential (0 volts), that is, the potential of the output terminal (OUT) will be pulled Rise to a steady state value of a first high potential voltage (VDDH). In other words, when the first signal (V (IN)) is the second high-potential voltage (1.2 volts), it is converted into a second signal with the first high-potential voltage (1.8 volts) by the voltage level converter and output by (OUT) output.

In summary, when the first signal (V (IN)) is low potential (0 volts), the second signal (V (OUT)) is also low potential (0 volts); and the first signal (V (IN) ) Is the second high potential voltage (1.2 volts), the second signal (V (OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

The Spice transient analysis simulation results of the voltage level converter proposed in this creation are shown in Figure 4. From the simulation results, it can be confirmed that the voltage level converter proposed in this creation can not only be fast and accurate The ground converts the first signal into a second signal, and can effectively reduce power loss.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (8)

A voltage level converter for converting a first signal (V (IN)) into a second signal (V (OUT)). The voltage level converter includes a first node (N1) for converting a second signal (N1). The gate of the PMOS transistor (MP2), a drain of a first PMOS transistor (MP1), a drain of a third PMOS transistor (MP3), a drain of a first NMOS transistor (MN1), and a The gates of the second NMOS transistor (MN2) are connected together; a second node (N2) is used to connect the gate of a first PMOS transistor (MP1) and the drain of a second PMOS transistor (MP2) Electrodes, a drain of a fourth PMOS transistor (MP4), a gate of a first NMOS transistor (MN1), and a drain of a second NMOS transistor (MN2) are connected together; a first input terminal ( IN), coupled to the gate of the third PMOS transistor (MP3), the gate of a third NMOS transistor (MN3), the gate of a fifth NMOS transistor (MN5), and a first inverter The input terminal of the converter (I1) is used to provide a first signal (V (IN)); a second input terminal (INB) is coupled to the gate of the fourth PMOS transistor (MP4), a fourth The gate of the NMOS transistor (MN4), the gate of a sixth NMOS transistor (MN6), and the first inverter (I1 ) Is used to provide an inverted signal of the first signal (V (IN)); an output (OUT) is coupled to the second node (N2) to output the second signal (V (OUT)); a first power supply voltage for providing a first high-potential voltage (VDDH) required by the voltage level converter; a second power supply voltage for providing a second required by the voltage level converter High potential voltage (VDDL), the potential of the second high potential voltage (VDDL) is less than the potential of the first high potential voltage (VDDH); a pull-up transistor pair (1) is used to connect the first node ( N1) and the potential of the second node (N2) are pulled up to the second high potential voltage (VDDL); a latch (2) is used to store the third NMOS transistor (MN3) and the fourth NMOS A differential input signal received by the transistor (MN4); a pull-down transistor pair (3) for pulling the potentials of the first node (N1) and the second node (N2) to ground (GND); And an input transistor pair (4) for providing the first signal (V (IN)) and an inverted signal of the first signal (V (IN)). The voltage level converter according to item 1 of the patent application scope, wherein the pull-up transistor pair (1) includes a third PMOS transistor (MP3), the source of which is connected to the second high-potential voltage ( VDDL), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1); and a fourth PMOS transistor (MP4), whose source is connected to the The second high-potential voltage (VDDL) has its gate connected to the second input terminal (INB), and its drain connected to the second node (N2). The voltage level converter according to item 2 of the patent application scope, wherein the latch (2) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high potential voltage (VDDH) , Its gate is connected to the second node (N2), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the first high potential Voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2); a first NMOS transistor (MN1), its source is connected to the The drain of the third NMOS transistor (MN3) has its gate connected to the second node (N2), and its drain is connected to the first node (N1); and a second NMOS transistor (MN2) ), Its source is connected to the drain of the fourth NMOS transistor (MN4), its gate is connected to the first node (N1), and its drain is connected to the second node (N2). The voltage level converter according to item 3 of the patent application scope, wherein the pull-down transistor pair (3) includes: a fifth NMOS transistor (MN5), the source of which is connected to the ground (GND), and the gate Is connected to the first input terminal (IN), and its drain is connected to the first node (N1); and a sixth NMOS transistor (MN6), its source is connected to the ground (GND), and The gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2). The voltage level converter according to item 4 of the scope of patent application, wherein the input transistor pair (4) includes: a third NMOS transistor (MN3), the source of which is connected to ground (GND), and the gate of which is connected To the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), whose source is connected to the ground (GND) , Its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1) is coupled to The first input terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). The voltage level converter according to item 5 of the application, wherein the voltage source of the first inverter (I1) is the second high potential voltage (VDDL). The voltage level converter according to item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high potential voltage (VDDL). The voltage level converter according to item 7 of the scope of patent application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high potential voltage (VDDH).