TWM565920U - Voltage level converter - Google Patents

Abstract

This creation proposes a voltage level converter, which is composed of a latch circuit (1), a potential pull-up circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to save the differential input signal received by the input transistor; the potential pull-up circuit (2) is used to store the potential of the first node (N1) and the second node (N2) Pulled up to the first high power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V (IN)) and the inverted signal of the first signal (V (IN)); The mode control switch (4) is used to control different operation modes of the voltage level converter.

The voltage level converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device, and it can also effectively reduce leakage. Current, which reduces power consumption.

Description

Voltage level converter

This creation is about a voltage level converter, especially using a latch circuit (1), a potential pull-up circuit (2), an input circuit (3), and a mode control switch (4). An electronic circuit that achieves precise voltage level conversion and effectively reduces power consumption.

The voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the voltage level converter is responsible for converting low-voltage working signals into high-voltage working signals. .

FIG. 1 shows a latch-type voltage level converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1 ), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter Voltage converter (INV) to form a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the first signal (V (IN) ) Is also between ground (GND) and the second high potential voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. . because Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-mentioned conventional voltage level converter is approaching (or turning off) the second PMOS transistor (MP2) and the process of turning off (or turning on) the second NMOS transistor (MN2). There is a phenomenon of contention between the pull-up and pull-down of the potential at the output terminal (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) And the second NMOS transistor (MN2) is completely turned on or completely turned off, so that there will be a static current between the first high potential voltage (VDDH) and ground (GND), and this static current will increase the power Loss.

In addition, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH), because the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The voltage is the first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited.

Figure 2 shows a mirrored voltage level converter circuit, which is one of the other prior art. The voltage level converter is connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The first PMOS transistor (MP1) is in The saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirrored voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate electrodes of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a voltage level converter, which can not only accurately and quickly convert a first signal into a second signal, but also effectively reduce leakage current and thus reduce power consumption.

This creation proposes a voltage level converter, which is composed of a latch circuit (1), a potential pull-up circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to save the differential input signal received by the input transistor; the potential pull-up circuit (2) is used to store the potential of the first node (N1) and the second node (N2) Pulled up to the first high power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V (IN)) and the inverted signal of the first signal (V (IN)); The mode control switch (4) is used to control different operation modes of the voltage level converter.

The simulation results confirm that the voltage level converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. It can also effectively reduce power loss.

1‧‧‧ latch circuit

2‧‧‧Potential pull-up circuit

3‧‧‧input circuit

4‧‧‧Mode control switch

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

EN‧‧‧Enable control terminal

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧Fifth NMOS transistor

I1‧‧‧first inverter

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

OUT‧‧‧output

V (OUT) ‧‧‧Second signal

GND‧‧‧ Ground

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

Fig. 1 is a circuit diagram showing a voltage level converter in the first prior art; Fig. 2 is a circuit diagram showing a voltage level converter in the second prior art; FIG. 3 is a circuit diagram showing a voltage level converter of the preferred embodiment of the present invention; FIG. 4 is a timing analysis diagram of the first signal and the second signal of the preferred embodiment of the present invention;

According to the above purpose, this creation proposes a voltage level converter, as shown in FIG. 3, which is composed of a latch circuit (1), a potential pull-up circuit (2), an input circuit (3), and a It is composed of a mode control switch (4), wherein the latch circuit (1) is used to save the differential input signal received by the input transistor; the potential pull-up circuit (2) is used to connect the first node ( N1) and the potential of the second node (N2) are pulled up to the first high power supply voltage (VDDH); and the input circuit (3) is used to provide the first signal (V (IN)) and the first The inverted signal of the signal (V (IN)); the mode control switch (4) is used to control different operation modes of the voltage level converter; the latch circuit (1) is composed of a first PMOS transistor ( MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the source of the first PMOS transistor (MP1) is connected To the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node (N1); the second PMOS transistor (MP2) , Its source is connected Connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2); the first NMOS transistor (MN1) ) Is connected to the source of the third NMOS transistor (MN3), its gate is connected to the second node (N2), and its drain is connected to the first node (N1); The source of the two NMOS transistors (MN2) is connected to the drain of the fourth NMOS transistor (MN4). The pole is connected to the first node (N1), and its drain is connected to the second node (N2); the potential pull-up circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), and its gate is connected to the first input terminal (IN), The drain is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), and the gate is connected to the second input. Terminal (INB), and its drain is connected to the second node (N2); the input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a A first inverter (I1), wherein the source of the third NMOS transistor (MN3) is connected to the third node (N3), the gate of the third NMOS transistor (MN3) is connected to the first input terminal (IN), and Its drain is connected to the source of the first NMOS transistor (MN1); the source of the fourth NMOS transistor (MN4) is connected to the third node (N3), and its gate is connected to the second Input terminal (INB), and its drain is electrically connected to the second NMOS The source of the body (MN2) is connected; the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)) and provide a connection with the The first signal (V (IN)) is an inverted signal; the mode control switch (4) is composed of a fifth NMOS transistor (MN5), whose source is connected to ground (GND) and its gate is connected to The enable control terminal (EN), and its drain is connected to the third node (N3); the first high power supply voltage (VDDH) is the first required to provide the voltage level converter High potential voltage; and the second high power supply voltage (VDDL) is used to provide a second high potential voltage required by the voltage level converter, and the potential of the second high power supply voltage (VDDL) is less than the first A potential of a high power supply voltage (VDDH), the first high voltage The source supply voltage (VDDH) is 1.8 volts, and the second highest power supply voltage (VDDL) is 1.2 volts; the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts. The two signals (V (OUT)) are corresponding waveforms between 0 volts and 1.8 volts.

Please refer to FIG. 3 again. The working mode of the voltage-level converter is described below. The working principle of FIG. 3 is as follows:

(I) Active mode

In the active mode, that is, when the enable control terminal (EN) is in a high potential state, the fifth NMOS transistor (MN5) is in an ON state.

Now consider the steady-state operation of the voltage level converter when the first signal (V (IN)) is low (0 volts): the low potential on the first input (IN) is simultaneously transmitted to the first inverter The input terminal of (I1), the gate of the third NMOS transistor (MN3) and the third PMOS transistor (MP3), so that the third NMOS transistor (MN3) is turned off and the third PMOS transistor (MP3) is turned on, At this time, the potential of the first node (N1) is pulled up to a high potential close to the first high potential voltage (VDDH); and the first inverter (I1) transmits the second high potential voltage (VDDL) to the first The gates of the four NMOS transistors (MN4) and the fourth PMOS transistor (MP4) cause the fourth NMOS transistor (MN4) to be turned on, the fourth PMOS transistor (MP4) to be turned off, and the first node (N1) The high potential causes the second PMOS transistor (MP2) to be turned off and the second NMOS transistor (MN2) to be turned on. At this time, due to the second NMOS transistor (MN2), the fourth NMOS transistor (MN4), and the fifth The NMOS transistor (MN5) is all on, so the potential of the second node (N2) is pulled down to a steady state value of a low potential (0 volts), and further, the low on the second node (N2) The potential is transferred to the first PMOS transistor ( MP1) and the gate of the first NMOS transistor (MN1), so that the first PMOS transistor (MP1) is turned on and the first NMOS transistor (MN1) is turned off, because the first PMOS transistor (MP1), the Third PMOS The transistor (MP3) is turned on, the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off, so the potential of the first node (N1) will maintain a first high potential voltage ( VDDH), and because the second NMOS transistor (MN2), the fourth NMOS transistor (MN4), and the fifth NMOS transistor (MN5) are all turned on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) ) Are turned off, so the potential of the second node (N2) will be maintained at a low potential (0 volts), that is, the potential of the output (OUT) will be pulled down to a steady state value of a low potential (0 volts) . In other words, when the first signal (V (IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) by a voltage level converter and output from the output terminal (OUT).

Consider again the steady-state operation of the voltage level converter when the first signal (V (IN)) is high (1.2 volts): the high potential at the first input (IN) is simultaneously transmitted to the first inverter The input of (I1), the gate of the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3) make the third NMOS transistor (MN3) turn on and the third PMOS transistor (MP3) turn off And the first inverter (I1) transmits a low potential to the gates of the fourth NMOS transistor (MN4) and the fourth PMOS transistor (MP4), so that the fourth NMOS transistor (MN4) is turned off, the The fourth PMOS transistor (MP4) is turned on. At this time, because the fourth PMOS transistor (MP4) is turned on, the potential of the second node (N2) is pulled up to a high potential close to the first high potential voltage (VDDH). ; And the high potential of the second node (N2) causes the first PMOS transistor (MP1) to be turned off and the first NMOS transistor (MN1) to be turned on. At this time, due to the first NMOS transistor (MN1) and the third NMOS The transistor (MN3) and the fifth NMOS transistor (MN5) are both turned on. Therefore, the potential of the first node (N1) is pulled down to a low potential (0 volts), and further, the first node (N1) N1) is transferred to The gates of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) cause the second PMOS transistor (MP2) to be turned on and the second NMOS transistor (MN2) to be turned off. At this time, due to the second PMOS transistor Both the body (MP2) and the fourth PMOS transistor (MP4) are turned on, and the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off. Therefore, the potential of the second node (N2) will be maintained at the first A high potential voltage (VDDH), and the potential of the first node (N1) is maintained at a low potential (0 volts), that is, the potential of the output terminal (OUT) is pulled up to a first high potential voltage (VDDH) Steady state value. In other words, when the first signal (V (IN)) is the second high-potential voltage (1.2 volts), it is converted into a second signal with the first high-potential voltage (1.8 volts) by the voltage level converter and output by (OUT) output.

In summary, when the first signal (V (IN)) is low potential (0 volts), the second signal (V (OUT)) is also low potential (0 volts); and the first signal (V (IN) ) Is the second high potential voltage (1.2 volts), the second signal (V (OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

(II) Standby mode

Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential state, the fifth NMOS transistor (MN5) is in an OFF state, and at this time, the voltage level converter stops action. At this time, the input of any first signal (V (IN)) will not affect the value of the second signal (V (OUT)) that has been locked. Its working principle is not repeated here.

The Spice transient analysis simulation results of the voltage level converter proposed in this creation are shown in Figure 4. From the simulation results, it can be confirmed that the voltage level converter proposed in this creation can not only be fast and accurate The ground converts the first signal into a second signal, and can effectively reduce power loss.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the application for this creation. Within the range.

Claims (8)

A voltage level converter for converting a first signal (V (IN)) into a second signal (V (OUT)). The voltage level converter includes a first node (N1) for converting a first signal (N1). The drain of the PMOS transistor (MP1), the gate of a second PMOS transistor (MP2), the drain of a first NMOS transistor (MN1), the drain of a third PMOS transistor (MP3), and a The gates of the second NMOS transistor (MN2) are connected together; a second node (N2) is used to drain the second PMOS transistor (MP2) and the gate of the first PMOS transistor (MP1) Electrodes, the drain of the second NMOS transistor (MN2), the drain of a fourth PMOS transistor (MP4), and the gate of the first NMOS transistor (MN1) are connected together; a third node (N3 ) For connecting the source of a third NMOS transistor (MN3), the source of a fourth NMOS transistor (MN4) and the drain of a fifth NMOS transistor (MN5); a first The input terminal (IN) is coupled to the gate of the third PMOS transistor (MP3) and the third NMOS transistor (MN3), and is used to provide a first signal (V (IN)); a second input Terminal (INB), coupled to the fourth PMOS transistor (MP4) and the fourth NMOS transistor (MN4) The gate is used to provide an inverted signal of the first signal (V (IN)); an output terminal (OUT) is coupled to the second node (N2) to output the second signal (V ( OUT)); a first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V (IN)), and providing a first signal (V) (IN)) Inverted signal; Uniform energy control terminal (EN) is coupled to the gate of the fifth NMOS transistor (MN5) to provide a uniform energy signal; a first high power supply voltage (VDDH) Is coupled to the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) to provide A first high potential voltage required by the voltage level converter; a second high power supply voltage (VDDL) for providing a second high potential voltage required by the voltage level converter, the second high power supply The potential of the voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH); a latch circuit (1) is used to store the third NMOS transistor (MN3) and the fourth NMOS transistor ( MN4) Differential input signal received; A bit pull-up circuit (2) is used to pull up the second signal (V (OUT)) to the first high power supply voltage (VDDH); an input circuit (3) is used to provide the first signal (V (IN)) and an inverted signal of the first signal (V (IN)); and a mode control switch (4) for controlling different operation modes of the voltage level converter. The voltage level converter according to item 1 of the patent application scope, wherein the latch circuit (1) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage (VDDH) ), Its gate is connected to the second node (N2), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the first high The power supply voltage (VDDH), whose gate is connected to the first node (N1), and whose drain is connected to the second node (N2); a first NMOS transistor (MN1), whose source is connected To the drain of the third NMOS transistor (MN3), its gate is connected to the second node (N2), and its drain is connected to the first node (N1); and a second NMOS transistor (MN2), whose source is connected to the drain of the fourth NMOS transistor (MN4), whose gate is connected to the first node (N1), and whose drain is connected to the second node (N2) . The voltage level converter according to item 2 of the scope of patent application, wherein the potential pull-up circuit (2) includes: a third PMOS transistor (MP3) whose source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1); and a fourth PMOS transistor (MP4), whose source is connected to the The first high power supply voltage (VDDH) has a gate connected to the second input terminal (INB) and a drain connected to the second node (N2). The voltage level converter according to item 3 of the patent application scope, wherein the input circuit (3) includes: a third NMOS transistor (MN3), the source of which is connected to the third node (N3), and the gate Is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), whose source is connected to the first A three-node (N3) whose gate is connected to the second input terminal (INB) and whose drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1 ), Coupled to the first input terminal (IN), for receiving the first signal (V (IN)), and providing a signal that is opposite to the first signal (V (IN)). The voltage level converter according to item 4 of the scope of patent application, wherein the mode control switch (4) is composed of the fifth NMOS transistor (MN5), and its source is connected to the ground (GND) and its gate The electrode is connected to the enable control terminal (EN), and its drain is connected to the third node (N3). The voltage level converter according to item 1 of the patent application range, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The voltage level converter according to item 6 of the application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). The voltage level converter according to item 7 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).