TWM569528U - Voltage level converter - Google Patents
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- TWM569528U TWM569528U TW107204529U TW107204529U TWM569528U TW M569528 U TWM569528 U TW M569528U TW 107204529 U TW107204529 U TW 107204529U TW 107204529 U TW107204529 U TW 107204529U TW M569528 U TWM569528 U TW M569528U
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Abstract
本創作提出一種電位轉換器,其係由一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成,其中,該電位拉升電路(1)係用來將第二信號(V(OUT))拉升到第一高電源供應電壓(VDDH)之電位;該模式控制開關(2)係設計成可因應不同操作模式而控制該第一節點(N1)和該第二節點(N2)之電壓位準,亦即該模式控制開關(2)於對應之該致能控制端(EN)的輸入信號為邏輯高位準時代表主動(active)模式,而該致能控制端(EN)的輸入信號為邏輯低位準時則為待機(standby)模式,俾藉此以於待機模式時,可有效降低功率的損耗;而該輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號。 This creation proposes a potential converter, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to Pull the second signal (V (OUT)) to the potential of the first high power supply voltage (VDDH); the mode control switch (2) is designed to control the first node (N1) and The voltage level of the second node (N2), that is, the input signal of the mode control switch (2) corresponding to the enable control terminal (EN) is a logic high level and represents the active mode, and the enable When the input signal of the control terminal (EN) is at a logic low level, it is in standby mode, so that the standby mode can effectively reduce power loss; and the input circuit (3) is used to provide the first Signal (V (IN)) and an inverted signal of the first signal (V (IN)).
本創作所提出之電位轉換器,不但能精確地將第一信號轉換為一第二信號,並且兼具電路結構簡單以及有利於裝置之小型化等多重功效,同時亦能有效地減少漏電流,進而降低功率消耗。 The potential converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device, and can also effectively reduce leakage current. This reduces power consumption.
Description
本創作係有關一種電位轉換器,尤指利用一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成,以求獲得精確電壓位準轉換且有效地降低功率消耗之電子電路。 This creation relates to a potential converter, especially using a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3) to obtain accurate voltage level conversion and effectively reduce Electronic circuit for power consumption.
電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit,簡稱IC)之間的信號傳遞之電子電路。在許多應用中,當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時,電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the potential converter is responsible for converting low-voltage working signals into high-voltage working signals.
第1圖係顯示一先前技藝(prior art)之一閂鎖型電位轉換器電路,其係使用一第一PMOS(P-channel metal oxide semiconductor,P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor,N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路,其中,該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND),而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極 (gate)。因此,在同一時間內,第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外,由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式,使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時,閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其,當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時,第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通,以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2);再者,當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時,第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通,以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此,在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V (IN)) Also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. (gate). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, because of the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potentiometer. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).
然而,上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中,對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象,因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外,考慮當第一信號(V(IN))由0伏特改變至1.8伏特時,第一NMOS電晶體(MN1)導通,而第二PMOS電晶體(MP2)的閘極變為低電位,使得第二PMOS電晶體(MP2)導通。所以,輸出為一第一高電源供應電壓(VDDH)。但是,由於0伏特無法瞬間轉換至1.8伏特,因此,在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體 (MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉,如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current),此靜態電流會增加功率的損耗。 However, in the process of the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) approaches to turn on (or off) and the second NMOS transistor (MN2) approaches to turn off (or on), the output terminal There is a phenomenon of contention between the pull-up and pull-down of the potential at (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current between the first high power supply voltage (VDDH) and ground (GND). This static Current increases power loss.
再者,閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響,由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH),而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此,限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The first high power supply voltage (VDDH) is supplied, and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type potential converter operate normally is limited.
第2圖係顯示另一先前技藝之一鏡像型電位轉換器電路,該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極,使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路,第一PMOS電晶體(MP1)是處於飽和區,並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流,而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定,因此,即使輸出的第一高電源供應電壓(VDDH)改變,電位轉換器的性能也不會有太大的改變。因此,鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 2 shows one of the other prior art mirror-type potential converter circuits. The potential converter is connected and connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). To the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in a saturation region, and Its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power supply voltage (VDDH) changes, the potential The performance of the converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.
然而,當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時,第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降,使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。 如此,在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).
有鑑於此,本創作之主要目的係提出一種電位轉換器,其不但能精確且快速地將第一信號轉換為一第二信號,並且可有效地減少漏電流,進而降低功率消耗。 In view of this, the main purpose of this creation is to propose a potential converter, which can not only accurately and quickly convert the first signal into a second signal, but also effectively reduce the leakage current and thus the power consumption.
本創作提出一種電位轉換器,其係由一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成,其中,該電位拉升電路(1)係用來將該第二信號(V(OUT))拉升到第一高電源供應電壓(VDDH);該模式控制開關(2)係設計成可因應不同操作模式而控制該第一節點(N1)和該第二節點(N2)之電壓位準,亦即該模式控制開關(2)於對應之該致能控制端(EN)的輸入信號為邏輯高位準時代表主動(active)模式,而輸入信號為邏輯低位準時則為待機(standby)模式,俾藉此以於待機模式時,可有效降低功率的損耗;而該輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號;該第一高電源供應電壓(VDDH)係用以提供該電位轉換器所需之第一高電位電壓;而該第二高電源供應電壓(VDDL)係用以提供該電位轉換器所需之第二高電位電壓,該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位,該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準,該第一信號為介於0伏特及1.2伏特間的矩形波,而該第二信號則為介於0伏特及1.8伏特間的對應波形。 This creation proposes a potential converter, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to Pull the second signal (V (OUT)) to the first high power supply voltage (VDDH); the mode control switch (2) is designed to control the first node (N1) and the The voltage level of the second node (N2), that is, the input signal of the mode control switch (2) corresponding to the enable control terminal (EN) is a logic high level, which represents the active mode, and the input signal is logic The low level is in standby mode, so that in the standby mode, the power loss can be effectively reduced; and the input circuit (3) is used to provide the first signal (V (IN)) and the first signal An inverted signal of a signal (V (IN)); the first high power supply voltage (VDDH) is used to provide a first high potential voltage required by the potential converter; and the second high power supply voltage (VDDL) ) Is used to provide the second high potential voltage required by the potential converter, and the potential of the second high power supply voltage (VDDL) is At the potential of the first high power supply voltage (VDDH), the level of the second high power supply voltage (VDDL) is less than the level of the first high power supply voltage (VDDH), and the first signal is between A rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts.
由模擬結果證實,本創作所提出之電位轉換器,不但能精確且快速地將第一信號轉換為一第二信號,並且兼具電路結構簡單以及有利於裝置之小型化等多重功效,同時亦能有效地減少功率損耗。 The simulation results confirm that the potential converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. Can effectively reduce power loss.
1‧‧‧電位拉升電路 1‧‧‧Potential pull-up circuit
2‧‧‧模式控制開關 2‧‧‧mode control switch
3‧‧‧輸入電路 3‧‧‧input circuit
EN‧‧‧致能控制端 EN‧‧‧Enable control terminal
N1‧‧‧第一節點 N1‧‧‧First Node
N2‧‧‧第二節點 N2‧‧‧Second Node
MP1‧‧‧第一PMOS電晶體 MP1‧‧‧The first PMOS transistor
MP2‧‧‧第二PMOS電晶體 MP2‧‧‧Second PMOS transistor
MP3‧‧‧第三PMOS電晶體 MP3‧‧‧Third PMOS Transistor
MP4‧‧‧第四PMOS電晶體 MP4‧‧‧Fourth PMOS transistor
MP5‧‧‧第五PMOS電晶體 MP5‧‧‧Fifth PMOS transistor
MP6‧‧‧第六PMOS電晶體 MP6‧‧‧sixth PMOS transistor
MN1‧‧‧第一NMOS電晶體 MN1‧‧‧The first NMOS transistor
MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor
IN‧‧‧第一輸入端 IN‧‧‧first input
V(IN)‧‧‧第一信號 V (IN) ‧‧‧First Signal
INB‧‧‧第二輸入端 INB‧‧‧Second Input
OUT‧‧‧輸出端 OUT‧‧‧output
GND‧‧‧地 GND‧‧‧ Ground
V(OUT)‧‧‧第二信號 V (OUT) ‧‧‧Second signal
VDDH‧‧‧第一高電源供應電壓 VDDH‧‧‧The first highest power supply voltage
VDDL‧‧‧第二高電源供應電壓 VDDL‧‧‧The second highest power supply voltage
I1‧‧‧第一反相器 I1‧‧‧first inverter
第1圖 係顯示第一先前技藝中電位轉換器之電路圖;第2圖 係顯示第二先前技藝中電位轉換器之電路圖;第3圖 係顯示本創作較佳實施例之電位轉換器之電路圖;第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖; Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; Figure 3 shows the circuit diagram of the potential converter in the preferred embodiment of the present invention; FIG. 4 is a timing diagram showing the transient analysis of the first signal and the second signal in the preferred embodiment of the present invention;
根據上述之目的,本創作提出一種電位轉換器,如第3圖所示,其係由一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成,其中,該電位拉升電路(1)係用來將該第二信號(V(OUT))拉升到第一高電源供應電壓(VDDH)之位準,其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成,其中,該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH),其閘極連接至該第一輸入端(IN),而其汲極則與該第三PMOS電晶體(MP3)的源極相連接;該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH),其閘極連接至該第二輸入端(INB),而其汲極則與該第四PMOS電晶體(MP4)的源極相連接; 該第三PMOS電晶體(MP3)的源極連接至該第一PMOS電晶體(MP1)的汲極,其閘極連接至該第二節點(N2),而其汲極則與該第一節點(N1)相連接;而該第四PMOS電晶體(MP4)的源極連接至該第二PMOS電晶體(MP2)的汲極,其閘極連接至該第一節點(N1),而其汲極則與該第二節點(N2)相連接;該模式控制開關(2)係用以控制該電位轉換器之不同操作模式;其係由一第五PMOS電晶體(MP5)、一第六PMOS電晶體(MP6)以及一致能控制端(EN)所組成,其中,該第五PMOS電晶體(MP5)的源極連接至該第一高電源供應電壓(VDDH),其閘極與該第六PMOS電晶體(MP6)的閘極相連接,而其汲極則與該第一節點(N1)相連接;該第六PMOS電晶體(MP6)的源極連接至該第一高電源供應電壓(VDDH),其閘極與該第五PMOS電晶體(MP5)的閘極相連接,而其汲極則與該第二節點(N2)相連接;而該致能控制端(EN)係耦接至該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極,用以提供一致能信號;該輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號;其係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成,其中,該第一NMOS電晶體(MN1)的源極連接至地(GND),其閘極連接至該第一輸入端(IN),而其汲極則與該第五PMOS電晶體(MP5)的汲極相連接;該第二NMOS電晶體(MN2)的源極連接至地(GND),其閘極連接至該第二輸入端(INB),而其汲極則與該第六PMOS電晶體(MP6)的汲極相連接;而該第一反相器(I1)係耦接於該第一輸 入端(IN),用以接受該第一信號(V(IN)),並提供一個與該第一信號(V(IN))反相的信號;該第一高電源供應電壓(VDDH)係用以提供該電位轉換器所需之第一高電位電壓;而該第二高電源供應電壓(VDDL)係用以提供該電位轉換器所需之第二高電位電壓,該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位,該第一高電源供應電壓(VDDH)為1.8伏特,而該第二高電源供應電壓(VDDL)為1.2伏特;該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波,該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, this creation proposes a potential converter, as shown in FIG. 3, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to pull up the second signal (V (OUT)) to the level of the first high power supply voltage (VDDH), which is controlled by a first PMOS transistor (MP1 ), A second PMOS transistor (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to The gate of the first high power supply voltage (VDDH) is connected to the first input terminal (IN), and its drain is connected to the source of the third PMOS transistor (MP3); the second PMOS The source of the transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth PMOS transistor (MP4). Connected to the source; The source of the third PMOS transistor (MP3) is connected to the drain of the first PMOS transistor (MP1), its gate is connected to the second node (N2), and its drain is connected to the first node (N1) phase connection; and the source of the fourth PMOS transistor (MP4) is connected to the drain of the second PMOS transistor (MP2), its gate is connected to the first node (N1), and its sink The pole is connected to the second node (N2); the mode control switch (2) is used to control different operation modes of the potential converter; it is composed of a fifth PMOS transistor (MP5), a sixth PMOS The transistor (MP6) and the uniform energy control terminal (EN) are composed, wherein the source of the fifth PMOS transistor (MP5) is connected to the first high power supply voltage (VDDH), and its gate is connected to the sixth The gate of the PMOS transistor (MP6) is connected, and its drain is connected to the first node (N1); the source of the sixth PMOS transistor (MP6) is connected to the first high power supply voltage ( VDDH), whose gate is connected to the gate of the fifth PMOS transistor (MP5), and its drain is connected to the second node (N2); and the enable control terminal (EN) is coupled To the fifth PMOS transistor (MP5) and The gate of the sixth PMOS transistor (MP6) is used to provide a uniform energy signal; the input circuit (3) is used to provide the first signal (V (IN)) and the first signal (V (IN)) It is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1). The first NMOS transistor (MN1) ) The source is connected to the ground (GND), its gate is connected to the first input (IN), and its drain is connected to the drain of the fifth PMOS transistor (MP5); the second NMOS The source of the transistor (MN2) is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the drain of the sixth PMOS transistor (MP6); The first inverter (I1) is coupled to the first output. An input terminal (IN) for receiving the first signal (V (IN)) and providing a signal opposite to the first signal (V (IN)); the first high power supply voltage (VDDH) is Is used to provide a first high potential voltage required by the potential converter; and the second high power supply voltage (VDDL) is used to provide a second high potential voltage required by the potential converter, the second high power supply The potential of the voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts; The first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is a corresponding waveform between 0 volts and 1.8 volts.
請再參閱第3圖,茲依電位轉換器之工作模式說明圖3之工作原理如下: Please refer to Figure 3 again. The working mode of the potential-dependent converter is illustrated in Figure 3. The working principle is as follows:
(I)主動模式(Active mode) (I) Active mode
在主動模式下,亦即,當該致能控制端(EN)是在高電位狀態時,該第五PMOS電晶體(MP5)和第六PMOS電晶體(MP6)均呈關閉(OFF)狀態。 In the active mode, that is, when the enable control terminal (EN) is in a high potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an OFF state.
現在考慮第一信號(V(IN))為低電位(0伏特)時,電位轉換器的穩態操作情形:第一輸入端(IN)上的低電位同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)以及第一PMOS電晶體(MP1)的閘極,使得該第一NMOS電晶體(MN1)關閉、第一PMOS電晶體(MP1)導通,而該第一反相器(I1)傳送第二高電位電壓(1.2伏特)到第二NMOS電晶體(MN2)和第二PMOS電晶體(MP2)的閘極,使得第二NMOS電晶體(MN2)導通、第二PMOS電晶體(MP2)關閉,此時,由於第二NMOS電晶體(MN2)導通,使得該第二節點(N2)的電位會被拉降至一低電位(0伏特)的值,該第二節點(N2)的低電位使得第三PMOS電晶體(MP3)導通,此時由於第一PMOS電晶體(MP1)和第三 PMOS電晶體(MP3)都導通,使得該第一節點(N1)的電位被拉升至一高電位,該第一節點(N1)的高電位使得第四PMOS電晶體(MP4)關閉,此時,由於第一PMOS電晶體(MP1)和第三PMOS電晶體(MP3)都導通,第一NMOS電晶體(MN1)關閉,因此,該第一節點(N1)的電位會被拉升至一第一高電位電壓(1.8伏特),而由於第二NMOS電晶體(MN2)導通,第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都關閉,因此,該第二節點(N2)的電位將維持在低電位(0伏特),因此,輸出端(OUT)的電位會被拉降至一低電位(0伏特)的穩態值。質言之,第一信號(V(IN))為低電位(0伏特)時,經過電位轉換器轉換成具低電位(0伏特)的第二信號,由輸出端(OUT)輸出。 Now consider the steady-state operation of the potential converter when the first signal (V (IN)) is low (0 volts): the low potential on the first input (IN) is simultaneously transmitted to the first inverter (I1) ) Input terminal, the first NMOS transistor (MN1) and the gate of the first PMOS transistor (MP1), so that the first NMOS transistor (MN1) is turned off, the first PMOS transistor (MP1) is turned on, and the The first inverter (I1) transmits the second high-potential voltage (1.2 volts) to the gates of the second NMOS transistor (MN2) and the second PMOS transistor (MP2), so that the second NMOS transistor (MN2) is turned on. 2. The second PMOS transistor (MP2) is turned off. At this time, because the second NMOS transistor (MN2) is turned on, the potential of the second node (N2) will be pulled down to a low potential (0 volt). The low potential of the second node (N2) causes the third PMOS transistor (MP3) to be turned on. At this time, due to the first PMOS transistor (MP1) and the third The PMOS transistor (MP3) is turned on, so that the potential of the first node (N1) is pulled up to a high potential, and the high potential of the first node (N1) causes the fourth PMOS transistor (MP4) to be turned off. Since both the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned on, the first NMOS transistor (MN1) is turned off, so the potential of the first node (N1) will be pulled up to a first A high potential voltage (1.8 volts), and because the second NMOS transistor (MN2) is turned on, both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned off, so the second node (N2) The potential of will be maintained at a low potential (0 volts), so the potential at the output (OUT) will be pulled down to a steady state value of a low potential (0 volts). In other words, when the first signal (V (IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) by a potential converter, and is output by the output terminal (OUT).
再考慮第一信號(V(IN))為第二高電位電壓(1.2伏特)時,電位轉換器的穩態操作情形:第一輸入端(IN)上的第二高電位電壓(1.2伏特)同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)以及第一PMOS電晶體(MP1)的閘極,使得該第一NMOS電晶體(MN1)導通、第一PMOS電晶體(MP1)關閉,該第一節點(N1)的低電位使得第四PMOS電晶體(MP4)導通,而該第一反相器(I1)傳送一低電位到第二NMOS電晶體(MN2)和第二PMOS電晶體(MP2)的閘極,使得第二NMOS電晶體(MN2)關閉、第二PMOS電晶體(MP2)導通,此時由於第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都導通,因此,該第二節點(N2)的電位會被拉升至一高電位;而該第二節點(N2)的高電位使得該第三PMOS電晶體(MP3)關閉,此時由於該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都關閉、該第一NMOS電晶體(MN1)導通,因此,該第一節點(N1)的電位會被拉降至一低電位(0伏特)的穩態值,因此,輸出端(OUT)的電位會被拉升至一第一高電位電壓(1.8伏 特)的穩態值。質言之,第一信號(V(IN))為第二高電位電壓(1.2伏特)時,經過電位轉換器轉換成具第一高電位電壓(1.8伏特)的第二信號,由輸出端(OUT)輸出。 Consider again the steady-state operation of the potential converter when the first signal (V (IN)) is the second high potential voltage (1.2 volts): the second high potential voltage (1.2 volts) on the first input terminal (IN) Simultaneously transmitted to the input of the first inverter (I1), the gate of the first NMOS transistor (MN1), and the gate of the first PMOS transistor (MP1), so that the first NMOS transistor (MN1) is turned on and the first The PMOS transistor (MP1) is turned off, the low potential of the first node (N1) causes the fourth PMOS transistor (MP4) to be turned on, and the first inverter (I1) transmits a low potential to the second NMOS transistor ( MN2) and the gate of the second PMOS transistor (MP2), so that the second NMOS transistor (MN2) is turned off and the second PMOS transistor (MP2) is turned on. At this time, the second PMOS transistor (MP2) and the fourth The PMOS transistor (MP4) is turned on, so the potential of the second node (N2) is pulled up to a high potential; and the high potential of the second node (N2) makes the third PMOS transistor (MP3) Off, at this time, because the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off, and the first NMOS transistor (MN1) is turned on, the potential of the first node (N1) will be Pulled down to a low Bit (0 volt) steady state value, and therefore, the output terminal (OUT) will be pulled up to the potential of a first high potential voltage (1.8 volts Special) steady state value. In other words, when the first signal (V (IN)) is the second high-potential voltage (1.2 volts), it is converted into a second signal with the first high-potential voltage (1.8 volts) by a potential converter, and the output terminal ( OUT) output.
綜上所述,第一信號(V(IN))為低電位(0伏特)時,第二信號(V(OUT))亦為低電位(0伏特);而第一信號(V(IN))為第二高電位電壓(1.2伏特)時,第二信號(V(OUT))為第一高電位電壓(1.8伏特)。如此,電壓位準轉換的目的便實現。 In summary, when the first signal (V (IN)) is low potential (0 volts), the second signal (V (OUT)) is also low potential (0 volts); and the first signal (V (IN) ) Is the second high potential voltage (1.2 volts), the second signal (V (OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.
(II)待機模式(Standby mode) (II) Standby mode
請再參考圖3。在待機狀態下,亦即,當該致能控制端(EN)是在低電位狀態時,該第五PMOS電晶體(MP5)和第六PMOS電晶體(MP6)均呈導通(ON)狀態,此時,由於該第一節點(N1)和該第二節點(N2)皆處於接近第一高電位電壓(VDDH)之電位,使得該第三PMOS電晶體(MP3)和該第四PMOS電晶體(MP4)都關閉,因此,該電位拉升電路(1)被除能。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an ON state. At this time, since the first node (N1) and the second node (N2) are both at a potential close to the first high potential voltage (VDDH), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are both turned off, so the potential pull-up circuit (1) is disabled. Its working principle is not repeated here.
本創作所提出之電位轉換器之Spice暫態分析模擬結果,如第4圖所示,由該模擬結果可証實,本創作所提出之電位轉換器,其不但仍能快速且精確地將第一信號轉換為一第二信號,並且能有效地降低功率的損耗。 The simulation results of Spice transient analysis of the potential converter proposed in this creation are shown in Figure 4. From the simulation results, it can be confirmed that the potential converter proposed in this creation can not only quickly and accurately convert the first The signal is converted into a second signal, and the power loss can be effectively reduced.
雖然本創作特別揭露並描述了所選之最佳實施例,但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此,所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.
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