TWM569528U - Voltage level converter - Google Patents

Abstract

This creation proposes a potential converter, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to Pull the second signal (V (OUT)) to the potential of the first high power supply voltage (VDDH); the mode control switch (2) is designed to control the first node (N1) and The voltage level of the second node (N2), that is, the input signal of the mode control switch (2) corresponding to the enable control terminal (EN) is a logic high level and represents the active mode, and the enable When the input signal of the control terminal (EN) is at a logic low level, it is in standby mode, so that the standby mode can effectively reduce power loss; and the input circuit (3) is used to provide the first Signal (V (IN)) and an inverted signal of the first signal (V (IN)).

The potential converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device, and can also effectively reduce leakage current. This reduces power consumption.

Description

Potentiometer

This creation relates to a potential converter, especially using a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3) to obtain accurate voltage level conversion and effectively reduce Electronic circuit for power consumption.

A potential converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the potential converter is responsible for converting low-voltage working signals into high-voltage working signals.

Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V (IN)) Also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. (gate). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, because of the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potentiometer. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the process of the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) approaches to turn on (or off) and the second NMOS transistor (MN2) approaches to turn off (or on), the output terminal There is a phenomenon of contention between the pull-up and pull-down of the potential at (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current between the first high power supply voltage (VDDH) and ground (GND). This static Current increases power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The first high power supply voltage (VDDH) is supplied, and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type potential converter operate normally is limited.

Figure 2 shows one of the other prior art mirror-type potential converter circuits. The potential converter is connected and connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). To the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in a saturation region, and Its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power supply voltage (VDDH) changes, the potential The performance of the converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a potential converter, which can not only accurately and quickly convert the first signal into a second signal, but also effectively reduce the leakage current and thus the power consumption.

This creation proposes a potential converter, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to Pull the second signal (V (OUT)) to the first high power supply voltage (VDDH); the mode control switch (2) is designed to control the first node (N1) and the The voltage level of the second node (N2), that is, the input signal of the mode control switch (2) corresponding to the enable control terminal (EN) is a logic high level, which represents the active mode, and the input signal is logic The low level is in standby mode, so that in the standby mode, the power loss can be effectively reduced; and the input circuit (3) is used to provide the first signal (V (IN)) and the first signal An inverted signal of a signal (V (IN)); the first high power supply voltage (VDDH) is used to provide a first high potential voltage required by the potential converter; and the second high power supply voltage (VDDL) ) Is used to provide the second high potential voltage required by the potential converter, and the potential of the second high power supply voltage (VDDL) is At the potential of the first high power supply voltage (VDDH), the level of the second high power supply voltage (VDDL) is less than the level of the first high power supply voltage (VDDH), and the first signal is between A rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts.

The simulation results confirm that the potential converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. Can effectively reduce power loss.

1‧‧‧Potential pull-up circuit

2‧‧‧mode control switch

3‧‧‧input circuit

EN‧‧‧Enable control terminal

N1‧‧‧First Node

N2‧‧‧Second Node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MP4‧‧‧Fourth PMOS transistor

MP5‧‧‧Fifth PMOS transistor

MP6‧‧‧sixth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

OUT‧‧‧output

GND‧‧‧ Ground

V (OUT) ‧‧‧Second signal

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

I1‧‧‧first inverter

Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; Figure 3 shows the circuit diagram of the potential converter in the preferred embodiment of the present invention; FIG. 4 is a timing diagram showing the transient analysis of the first signal and the second signal in the preferred embodiment of the present invention;

According to the above purpose, this creation proposes a potential converter, as shown in FIG. 3, which is composed of a potential pull-up circuit (1), a mode control switch (2), and an input circuit (3). The potential pull-up circuit (1) is used to pull up the second signal (V (OUT)) to the level of the first high power supply voltage (VDDH), which is controlled by a first PMOS transistor (MP1 ), A second PMOS transistor (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to The gate of the first high power supply voltage (VDDH) is connected to the first input terminal (IN), and its drain is connected to the source of the third PMOS transistor (MP3); the second PMOS The source of the transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth PMOS transistor (MP4). Connected to the source; The source of the third PMOS transistor (MP3) is connected to the drain of the first PMOS transistor (MP1), its gate is connected to the second node (N2), and its drain is connected to the first node (N1) phase connection; and the source of the fourth PMOS transistor (MP4) is connected to the drain of the second PMOS transistor (MP2), its gate is connected to the first node (N1), and its sink The pole is connected to the second node (N2); the mode control switch (2) is used to control different operation modes of the potential converter; it is composed of a fifth PMOS transistor (MP5), a sixth PMOS The transistor (MP6) and the uniform energy control terminal (EN) are composed, wherein the source of the fifth PMOS transistor (MP5) is connected to the first high power supply voltage (VDDH), and its gate is connected to the sixth The gate of the PMOS transistor (MP6) is connected, and its drain is connected to the first node (N1); the source of the sixth PMOS transistor (MP6) is connected to the first high power supply voltage ( VDDH), whose gate is connected to the gate of the fifth PMOS transistor (MP5), and its drain is connected to the second node (N2); and the enable control terminal (EN) is coupled To the fifth PMOS transistor (MP5) and The gate of the sixth PMOS transistor (MP6) is used to provide a uniform energy signal; the input circuit (3) is used to provide the first signal (V (IN)) and the first signal (V (IN)) It is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1). The first NMOS transistor (MN1) ) The source is connected to the ground (GND), its gate is connected to the first input (IN), and its drain is connected to the drain of the fifth PMOS transistor (MP5); the second NMOS The source of the transistor (MN2) is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the drain of the sixth PMOS transistor (MP6); The first inverter (I1) is coupled to the first output. An input terminal (IN) for receiving the first signal (V (IN)) and providing a signal opposite to the first signal (V (IN)); the first high power supply voltage (VDDH) is Is used to provide a first high potential voltage required by the potential converter; and the second high power supply voltage (VDDL) is used to provide a second high potential voltage required by the potential converter, the second high power supply The potential of the voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts; The first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again. The working mode of the potential-dependent converter is illustrated in Figure 3. The working principle is as follows:

(I) Active mode

In the active mode, that is, when the enable control terminal (EN) is in a high potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an OFF state.

Now consider the steady-state operation of the potential converter when the first signal (V (IN)) is low (0 volts): the low potential on the first input (IN) is simultaneously transmitted to the first inverter (I1) ) Input terminal, the first NMOS transistor (MN1) and the gate of the first PMOS transistor (MP1), so that the first NMOS transistor (MN1) is turned off, the first PMOS transistor (MP1) is turned on, and the The first inverter (I1) transmits the second high-potential voltage (1.2 volts) to the gates of the second NMOS transistor (MN2) and the second PMOS transistor (MP2), so that the second NMOS transistor (MN2) is turned on. 2. The second PMOS transistor (MP2) is turned off. At this time, because the second NMOS transistor (MN2) is turned on, the potential of the second node (N2) will be pulled down to a low potential (0 volt). The low potential of the second node (N2) causes the third PMOS transistor (MP3) to be turned on. At this time, due to the first PMOS transistor (MP1) and the third The PMOS transistor (MP3) is turned on, so that the potential of the first node (N1) is pulled up to a high potential, and the high potential of the first node (N1) causes the fourth PMOS transistor (MP4) to be turned off. Since both the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned on, the first NMOS transistor (MN1) is turned off, so the potential of the first node (N1) will be pulled up to a first A high potential voltage (1.8 volts), and because the second NMOS transistor (MN2) is turned on, both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned off, so the second node (N2) The potential of will be maintained at a low potential (0 volts), so the potential at the output (OUT) will be pulled down to a steady state value of a low potential (0 volts). In other words, when the first signal (V (IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) by a potential converter, and is output by the output terminal (OUT).

Consider again the steady-state operation of the potential converter when the first signal (V (IN)) is the second high potential voltage (1.2 volts): the second high potential voltage (1.2 volts) on the first input terminal (IN) Simultaneously transmitted to the input of the first inverter (I1), the gate of the first NMOS transistor (MN1), and the gate of the first PMOS transistor (MP1), so that the first NMOS transistor (MN1) is turned on and the first The PMOS transistor (MP1) is turned off, the low potential of the first node (N1) causes the fourth PMOS transistor (MP4) to be turned on, and the first inverter (I1) transmits a low potential to the second NMOS transistor ( MN2) and the gate of the second PMOS transistor (MP2), so that the second NMOS transistor (MN2) is turned off and the second PMOS transistor (MP2) is turned on. At this time, the second PMOS transistor (MP2) and the fourth The PMOS transistor (MP4) is turned on, so the potential of the second node (N2) is pulled up to a high potential; and the high potential of the second node (N2) makes the third PMOS transistor (MP3) Off, at this time, because the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off, and the first NMOS transistor (MN1) is turned on, the potential of the first node (N1) will be Pulled down to a low Bit (0 volt) steady state value, and therefore, the output terminal (OUT) will be pulled up to the potential of a first high potential voltage (1.8 volts Special) steady state value. In other words, when the first signal (V (IN)) is the second high-potential voltage (1.2 volts), it is converted into a second signal with the first high-potential voltage (1.8 volts) by a potential converter, and the output terminal ( OUT) output.

In summary, when the first signal (V (IN)) is low potential (0 volts), the second signal (V (OUT)) is also low potential (0 volts); and the first signal (V (IN) ) Is the second high potential voltage (1.2 volts), the second signal (V (OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

(II) Standby mode

Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an ON state. At this time, since the first node (N1) and the second node (N2) are both at a potential close to the first high potential voltage (VDDH), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are both turned off, so the potential pull-up circuit (1) is disabled. Its working principle is not repeated here.

The simulation results of Spice transient analysis of the potential converter proposed in this creation are shown in Figure 4. From the simulation results, it can be confirmed that the potential converter proposed in this creation can not only quickly and accurately convert the first The signal is converted into a second signal, and the power loss can be effectively reduced.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (7)

A potential converter is used to convert a first signal (V (IN)) into a second signal (V (OUT)). The potential converter includes a first node (N1) for converting a fourth PMOS voltage The gate of the crystal (MP4), the drain of a third PMOS transistor (MP3) and the drain of a fifth PMOS transistor (MP5) are connected together; a second node (N2) is used to connect a first The gates of the three PMOS transistors (MP3), the drain of a fourth PMOS transistor (MP4) and the drain of a sixth PMOS transistor (MP6) are connected together; a first input (IN), coupled Connected to a gate of a first PMOS transistor (MP1), a gate of a first NMOS transistor (MN1), and an input terminal of a first inverter (I1) for providing a first signal (V (IN)); a second input terminal (INB), coupled to a gate of a second PMOS transistor (MP2), a gate of a second NMOS transistor (MN2), and the first inverter ( The output terminal of I1) is used to provide the inverted signal of the first signal (V (IN)); the uniform control input terminal (EN) is used to provide the uniform energy signal; an output terminal (OUT) is coupled to The second node (N2) is used to output the second signal (V (OUT)); a first high power supply The voltage (VDDH) is coupled to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to provide a first high-potential voltage required by the potential converter; a second A high power supply voltage (VDDL) is used to provide a second high potential voltage required by the potential converter. The potential of the second high power supply voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH). A potential pull-up circuit (1) for pulling the second signal (V (OUT)) to the potential of the first high power supply voltage (VDDH); a mode control switch (2) for controlling the Different operation modes of the potential converter; and an input circuit (3) for providing the first signal (V (IN)) and an inverted signal of the first signal (V (IN)). The potential converter according to item 1 of the scope of patent application, wherein the potential pull-up circuit (1) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH) , Its gate is connected to the first input terminal (IN), and its drain is connected to the source of the third PMOS transistor (MP3); a second PMOS transistor (MP2), its source is connected To the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the fourth PMOS transistor (MP4); a third The source of the PMOS transistor (MP3) is connected to the drain of the first PMOS transistor (MP1), the gate is connected to the second node (N2), and the drain is connected to the first node (N1) ) Phase connection; and a fourth PMOS transistor (MP4), its source is connected to the drain of the second PMOS transistor (MP2), its gate is connected to the first node (N1), and its drain It is connected to the second node (N2). The potential converter according to item 2 of the scope of patent application, wherein the mode control switch (2) includes a fifth PMOS transistor (MP5) whose source is connected to the first high power supply voltage (VDDH), Its gate is connected to the gate of the sixth PMOS transistor (MP6), and its drain is connected to the first node (N1); a sixth PMOS transistor (MP6), its source is connected to The gate of the first high power supply voltage (VDDH) is connected to the gate of the fifth PMOS transistor (MP5), and the drain is connected to the second node (N2); The terminal (EN) is coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) to provide a uniform energy signal. The potential converter according to item 3 of the scope of patent application, wherein the input circuit (3) includes: a first NMOS transistor (MN1), a source of which is connected to ground (GND), and a gate of which is connected to the first The input terminal (IN), and its drain is connected to the drain of the fifth PMOS transistor (MP5); a second NMOS transistor (MN2), whose source is connected to ground (GND), and its gate Connected to the second input terminal (INB), and its drain is connected to the drain of the sixth PMOS transistor (MP6); and a first inverter (I1) is coupled to the first input The terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). The potential converter according to item 4 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL). The potential converter according to item 1 of the patent application range, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The potential converter according to item 6 of the application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH).