TWM591738U - Low power voltage level converter - Google Patents

Abstract

This author proposes a low power voltage level converter, which is composed of an input circuit (1), a latch circuit (2) and a competition suppression circuit (3), wherein the input circuit (1) is used To provide a differential input signal; the latch circuit (2) is used to save the second signal (V(OUT)); the competition suppression circuit (3) is used to suppress the competition phenomenon of the output (OUT) potential .

The low-power voltage level converter proposed in this work not only can accurately convert the first signal to a second signal, but also has multiple functions such as simple circuit structure and device miniaturization, and it can also effectively Suppresses the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

Low power voltage level converter

This author proposes a low-power voltage level converter, especially an input circuit (1), a latch circuit (2) and a competition suppression circuit (3), in order to obtain accurate voltage level conversion at the same time An electronic circuit that can effectively reduce power loss.

A voltage level converter is an electronic circuit used to communicate signals between different integrated circuits (ICs). In many applications, when the application system needs to transfer the signal from the core logic with a lower voltage level to the peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low-voltage working signal into a high-voltage working signal .

Figure 1 shows a mirror-type voltage level converter circuit of another prior art. The voltage level converter uses a first PMOS transistor (MP1) and a second PMOS transistor (MP2). The gates of are connected together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor ( MP1) is in the saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Also equal. Since the performance of the mirror-type voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power supply voltage (VDDH) changes , The performance of the voltage level converter There will not be much change. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Figure 2 shows a prior art latch-type voltage level converter circuit that uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor ( MN1), a second NMOS transistor (MN2) and an inverter (INV) to form a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second highest power supply voltage ( VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned ON. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; furthermore, When the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that The gate potential of the first PMOS transistor (MP1) is raised to turn off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-mentioned conventional voltage level converter is approaching (or turning off) the second PMOS transistor (MP2) and turning off (or turning on) the second NMOS transistor (MN2). There is a phenomenon of contention between the pull-up and pull-down of the potential at the output (OUT), so the second signal (V(OUT)) is slower when it transitions to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) turns on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be instantaneously converted to 1.8 volts, the lower first signal (V(IN)) during the conversion may not make the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or turned off, which will cause a static current (static) between the first high power supply voltage (VDDH) and the ground (GND) current), this quiescent current will increase the power loss.

Furthermore, the performance of the latch-type voltage level converter is affected by the first high power supply voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The pole voltage is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second highest power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can normally operate the latch-type voltage level converter is limited. In the process of the second PMOS transistor (MP2) tending to turn on (or off) and in the process of the second NMOS transistor (MN2) tending to turn off (or turn on), the pull on the potential at the output (OUT) There is a phenomenon of contention between rise and fall, so the second signal (V(OUT)) is slower when it transitions to a low potential.

In view of this, the main purpose of this creation is to propose a low-power voltage level converter, which not only can accurately and quickly convert the first signal to a second signal, but also can effectively reduce the pull-up path and the pull-down path Compete with each other to reduce power consumption.

This author proposes a low power voltage level converter, which is composed of an input circuit (1), a latch circuit (2) and a competition suppression circuit (3), wherein the input circuit (1) is used To provide a differential input signal; the latch circuit (2) is used to save the second signal (V(OUT)); the competition suppression circuit (3) is used to suppress the competition phenomenon of the output (OUT) potential .

It is confirmed by the simulation results that the low-power voltage level converter proposed in this work not only can accurately and quickly convert the first signal to a second signal, but also has a simple circuit structure and is beneficial to the miniaturization of the device. It can also effectively reduce power loss.

1‧‧‧ input circuit

2‧‧‧ latch circuit

3‧‧‧Competition suppression circuit

I1‧‧‧First inverter

N1‧‧‧First node

N2‧‧‧The second node

MP1‧‧‧First PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧third PMOS transistor

MP4‧‧‧ Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

OUT‧‧‧Output

V(OUT)‧‧‧Second signal

IN‧‧‧First input

V(IN)‧‧‧First signal

INB‧‧‧Second input terminal

GND‧‧‧Ground

VDDH‧‧‧The highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

Figure 1 is a circuit diagram showing the voltage level converter in the first prior art;

Figure 2 is a circuit diagram showing a voltage level converter in the second prior art;

Figure 3 is a circuit diagram showing the low power voltage level converter of the preferred embodiment of the present invention;

Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

Based on the above purpose, the author proposes a low-power voltage level converter, as shown in Figure 3, which is composed of an input circuit (1), a latch circuit (2) and a competition suppression circuit (3) Composition, wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the second signal (V (OUT)); the competition suppression circuit (3) is used To suppress the competition of the potential of the output terminal (OUT); the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1) The source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input (IN), and the drain is connected to the third PMOS transistor (MP3) the drain is connected; the source of the second NMOS transistor (MN2) is connected to ground (GND), its gate is connected to the second input (INB), and its drain is connected to the first The drains of the four PMOS transistors (MP4) are connected; the first inverter (I1) is coupled to the first input (IN) for receiving the first signal (V(IN)), and Provide a signal inverse to the first signal (V(IN)); the latch circuit (2) is composed of a first PMOS transistor (MP1) and a second PMOS transistor (MP2), where , The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node (N1 ) Connected; the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), the gate is connected to the first node (N1), and the drain is connected to the second The node (N2) is connected; the competition suppression circuit (3) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the third PMOS transistor (MP3) is connected to the first node (N1), and the gate is connected to the second input terminal (INB), and its drain is connected to the drain of the first NMOS transistor (MN1); the source of the fourth PMOS transistor (MP4) is connected to the second node (N2), and its gate Connected to the first input (IN), and its drain is connected to the drain of the second NMOS transistor (MN2); the first high power supply voltage (VDDH) is used to provide the low power voltage The first high power supply voltage required by the level converter, the second high power supply voltage (VDDL) is used to provide the second highest power supply voltage required by the low power voltage level converter, the second high power supply The level of the voltage (VDDL) is less than the level of the first high power supply voltage (VDDH), the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is between 0 Corresponding waveform between volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, and the first signal (V(IN)) is For a rectangular wave between 0 volts and 1.2 volts, the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to Fig. 3 again. Now consider the steady-state operation of the low-power voltage level converter when the first signal (V(IN)) is at a logic low level (0 volts): on the first input (IN) The logic low level is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the gate of the fourth PMOS transistor (MP4), so that the first NMOS Transistor (MN1) is turned off, the fourth PMOS transistor (MP4) is turned on, and the first inverter (I1) transmits a logic high level (VDDL) to the second NMOS transistor (MN2) ) And the gate of the third PMOS transistor (MP3), so that the second NMOS transistor (MN2) is turned on (ON), the third PMOS transistor (MP3) is turned off (OFF), at this time, due to the first Four PMOS transistors (MP4) And the second NMOS transistor (MN2) are turned on, the potential of the second node (N2) is pulled down to a logic low level (0 volts), and the logic on the second node (N2) The low level is transmitted to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on. At this time, since the first PMOS transistor (MP1) is turned on, the first NMOS transistor (MN1) and the third PMOS transistor (MP3) are turned off, therefore, the potential of the first node (N1) will be raised to a logic high level, the logic high level of the first node (N1) makes the The second PMOS transistor (MP2) is turned off. Since the second PMOS transistor (MP2) is turned off, and the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4) are both turned on, therefore, the second The potential of the node (N2) will be maintained at a logic low level (0 volts), and the potential of the output terminal (OUT) will be maintained at a steady state value of a logic low level (0 volts). In short, when the first signal (V(IN)) is a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by a low-power voltage level converter. OUT) output.

Considering the steady state operation of the low power voltage level converter when the first signal (V(IN)) is at logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is transmitted simultaneously To the input of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the gate of the fourth PMOS transistor (MP4), so that the first NMOS transistor (MN1) On, the fourth PMOS transistor (MP4) is turned off, and the first inverter (I1) transmits a logic low level to the second NMOS transistor (MN2) and the third PMOS transistor (MP3), the second NMOS transistor (MN2) is turned off, and the third PMOS transistor (MP3) is turned on. At this time, due to the third PMOS transistor (MP3) and The first NMOS transistor (MN1) is turned on, the potential of the first node (N1) is pulled down to a logic low level, and the logic low level on the first node (N1) is transmitted to the first The gate of two PMOS transistors (MP2) makes The second PMOS transistor (MP2) is turned on. At this time, since the second PMOS transistor (MP2) is turned on, and both the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4) are turned off, therefore, The potential of the second node (N2) will be raised to a logic high level, and the logic high level of the second node (N2) causes the first PMOS transistor (MP1) to turn off. At this time, the first PMOS transistor The crystal (MP1) is turned off, and the first NMOS transistor (MN1) and the third PMOS transistor (MP3) are both turned on. Therefore, the potential of the first node (N1) will be maintained at a logic low level, and the The potential of the second node (N2) will also be maintained at a logic high level. Therefore, the potential of the output terminal (OUT) will be maintained at a logic high level. In short, when the first signal (V(IN)) is a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) by a low-power voltage level converter, which is output by (OUT) output.

In summary, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal When (V(IN)) is a logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The simulation results of Spice transient analysis of the low power voltage level converter proposed in this creation are shown in Figure 4. From the simulation results, it can be confirmed that the low power voltage level converter proposed in this creation not only remains The first signal can be converted into a second signal quickly and accurately, and the competition between the pull-up path and the pull-down path at the output (OUT) can be effectively reduced, thereby reducing power loss.

Although this creation specifically discloses and describes the selected preferred embodiment, anyone familiar with the technology may understand that any possible changes in form or detail have not departed from the spirit and scope of this creation. Therefore, all changes in the relevant technical category are included in the application Profitable.

1‧‧‧ input circuit

2‧‧‧ latch circuit

3‧‧‧Competition suppression circuit

I1‧‧‧First inverter

N1‧‧‧First node

N2‧‧‧The second node

MP1‧‧‧First PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧third PMOS transistor

MP4‧‧‧ Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

OUT‧‧‧Output

V(OUT)‧‧‧Second signal

IN‧‧‧First input

V(IN)‧‧‧First signal

INB‧‧‧Second input terminal

GND‧‧‧Ground

VDDH‧‧‧The highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

Claims (7)

A low power voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: A first node (N1) for connecting the source of a third PMOS transistor (MP3), the gate of a second PMOS transistor (MP2) and the drain of a first PMOS transistor (MP1) Together A second node (N2) for connecting the source of a fourth PMOS transistor (MP4), the gate of the first PMOS transistor (MP1) and the drain of the second PMOS transistor (MP2) Together A first input terminal (IN), coupled to the gates of the first NMOS transistor (MN1) and the fourth PMOS transistor (MP4), for providing the first signal (V(IN)); A second input terminal (INB) is coupled to the gate of a second NMOS transistor (MN2) and the third PMOS transistor (MP3) to provide the inverse of the first signal (V(IN)) Phase signal (V(INB)); An output terminal (OUT), coupled to the second node (N2), is used to output the second signal (V(OUT)); A first inverter (I1), coupled to the first input terminal (IN), is used to receive the first signal (V(IN)) and provide a first signal (V(IN)) Inverted signal; A first high power supply voltage (VDDH), coupled to the source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), is used to provide the first level required by the voltage level converter A high power supply voltage; A second high power supply voltage (VDDL) is used to provide a second high power supply voltage required by the voltage level converter. The potential of the second high power supply voltage (VDDL) is less than the first high power supply voltage (VDDH) potential; An input circuit (1), coupled to the first input terminal (IN), is used to provide a differential input signal; A latch circuit (2), coupled to the first high power supply voltage (VDDH), for storing the second signal (V(OUT)); and A competition suppression circuit (3), coupled to the input circuit (1) and the latch circuit (2), is used to suppress the competition of the potential of the output terminal (OUT). The low power voltage level converter as described in item 1 of the patent application scope, wherein the input circuit (1) includes: A first NMOS transistor (MN1), its source is connected to ground (GND), its gate is connected to the first input (IN), and its drain is connected to the third PMOS transistor (MP3) Drain connected A second NMOS transistor (MN2), its source is connected to ground (GND), its gate is connected to the second input (INB), and its drain is connected to the fourth PMOS transistor (MP4) Drain connected; and A first inverter (I1), coupled to the first input terminal (IN), is used to receive the first signal (V(IN)) and provide a first signal (V(IN)) Inverted signal. The low power voltage level converter as described in item 2 of the patent application scope, wherein the latch circuit (2) includes: A first PMOS transistor (MP1), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node (N1 ) Connected; and A second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2 ) Are connected. The low power voltage level converter as described in item 3 of the patent application scope, wherein the competition suppression circuit (3) includes: A third PMOS transistor (MP3) has its source connected to the first node (N1), its gate connected to the second input (INB), and its drain connected to the first NMOS transistor ( MN1) connected to the drain; and A fourth PMOS transistor (MP4), its source is connected to the second node (N2), its gate is connected to the first input (IN), and its drain is connected to the second NMOS transistor ( The drain of MN2) is connected. The low power voltage level converter as described in item 1 of the patent application range, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). The low-power voltage level converter according to item 5 of the patent application scope, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). The low power voltage level converter according to item 6 of the patent application scope, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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