WO2022116415A1

WO2022116415A1 - Level conversion circuit

Info

Publication number: WO2022116415A1
Application number: PCT/CN2021/082553
Authority: WO
Inventors: 王先宏; 梁爱梅; 温长清; 陆让天
Original assignee: 深圳市紫光同创电子有限公司
Priority date: 2020-12-01
Filing date: 2021-03-24
Publication date: 2022-06-09
Also published as: CN112532230A; JP2023547186A

Abstract

A level conversion circuit, comprising a level conversion unit and a duty cycle unit; wherein the level conversion unit comprises: an input node (IN), an output node (OUT) configured to output an output signal having a desired level, an adjustment input node (A), and an adjustment output node (B) configured to adjust the duty cycle of the output signal; the duty cycle unit is coupled between the adjustment input node (A) and the adjustment output node (B); and the duty cycle unit is configured to adjust the duty cycle of the output signal. The level conversion unit of the level conversion circuit is configured to output an output signal having a desired level, and is coupled to the duty cycle unit in the level conversion unit, so that the duty cycle of the output signal is effectively adjusted without changing the size proportion of the level conversion unit, thereby improving the quality of the output signal.

Description

Level shift circuit

【Technical field】

The present application relates to the technical field of integrated circuit chips, and in particular, to a level conversion circuit.

【Background technique】

In a semiconductor integrated circuit, the circuit signal is not very stable during the power-on or power-off process, especially when multiple power domains are used for power supply, the asynchrony of the power-on or power-off sequence of each power domain can easily lead to circuit signals Uncontrollable, this situation is particularly obvious in the level conversion circuit, which directly leads to an error in the output signal of the level conversion circuit, and may cause large leakage problems and damage related devices.

The level conversion circuit includes a high-voltage level conversion circuit and a low-voltage level conversion circuit, wherein the high-voltage level conversion circuit converts a low-voltage signal into a high-voltage signal, so as to realize the control of the low-voltage logic to the high-voltage logic; the low-voltage level conversion circuit is a Convert the high voltage signal to the low voltage signal, so as to realize the control of the high voltage logic to the low voltage logic.

The level conversion circuit in the prior art is composed of four high-voltage transistors, two high-voltage PMOS tubes are used for pull-up, and two high-voltage NMOS tubes are used for pull-down. The gates of the two high-voltage NMOS tubes are used as the two input terminals of the level conversion circuit, and the input terminal voltage is a low voltage potential; the drains of the two high-voltage PMOS tubes are used as the two output terminals of the level conversion circuit, and the output terminal voltage is high voltage potential. Since the two high-voltage NMOS tubes work in a low-voltage condition, the pull-down capability of the two high-voltage NMOS tubes is very weak. When the low-voltage value is low to a certain extent, the level conversion circuit cannot work, that is, the level conversion function cannot be realized. Moreover, the time difference between the rising edge and the falling edge of the converted signal is very large, which leads to the unreasonable duty cycle of the converted signal.

【Contents of application】

The purpose of the present application is to provide a level conversion circuit to improve the quality of the output signal.

In order to achieve the above object, the present application provides a level conversion circuit, including a level conversion unit and a duty cycle unit; the level conversion unit includes: an input node, a circuit for outputting an output signal with a required level an output node, an adjustment input node, and an adjustment output node for adjusting the duty cycle of the output signal; the duty cycle unit is coupled between the adjustment input node and the adjustment output node; the duty cycle unit, Used to adjust the duty cycle of the output signal.

Preferably, a feedback unit is also included, the feedback unit is coupled between the adjustment input node and the output node; the feedback unit is used to perform feedback compensation on the output signal.

Preferably, an enabling unit is further included, the output end of the enabling unit is connected to the adjustment input node; the enabling unit is used to control the operation of the level conversion unit.

Preferably, it also includes a second inverter and a third inverter; the input end of the second inverter is connected to the output node, and the output end of the second inverter is connected to the third inverter The input terminal of the phaser is connected.

Preferably, the feedback unit includes an NMOS transistor.

Preferably, the enabling unit includes a PMOS transistor.

Preferably, both the second inverter and the third inverter include a PMOS transistor and an NMOS transistor connected in series between the first power supply and the ground terminal.

The beneficial effects of the present application are as follows: a level conversion circuit is provided, wherein the level conversion unit is used to output an output signal with a required level, and by coupling the duty cycle unit in the level conversion unit, the Without changing the size ratio of the level conversion unit, the duty cycle of the output signal is effectively adjusted, thereby improving the quality of the output signal.

【Description of drawings】

FIG. 1 is a schematic circuit diagram of a level conversion circuit according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a level conversion circuit according to another embodiment of the present application;

3 is a schematic circuit diagram of a level conversion circuit according to still another embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a level conversion circuit according to another embodiment of the present application.

【Detailed ways】

In order to make the purpose, technical solutions and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present specification, but not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

The terms "first", "second" and "third" in the description and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

An embodiment of the present application provides a level conversion circuit, including a level conversion unit and a duty cycle unit.

The level conversion unit includes: an input node, an output node for outputting an output signal with a required level, an adjustment input node, and an adjustment output node for adjusting the duty cycle of the output signal; the duty cycle unit is coupled to connected between the adjustment input node and the adjustment output node.

The duty cycle unit is used to adjust the duty cycle of the output signal.

In the level conversion circuit of the present application, the level conversion unit of the level conversion unit is used to output an output signal with a required level, and by coupling the duty cycle unit in the level conversion unit, the size ratio of the level conversion unit is not changed. In the case of , effectively adjust the duty cycle of the output signal, thereby improving the quality of the output signal.

In one embodiment, the level conversion unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter.

The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the input node, the source of the first PMOS transistor is connected to the first power supply, and the drain of the first PMOS transistor is connected to the third PMOS The source of the transistor, the gate of the third PMOS transistor is connected to the output node, the drain of the third PMOS transistor and the drain of the first NMOS transistor are connected to the adjustment input node, and the source of the first NMOS transistor is connected to ground end.

The gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the reverse input node, the source of the second PMOS transistor is connected to the first power supply, and the drain of the second PMOS transistor is connected to the fourth PMOS The source of the transistor, the gate of the fourth PMOS transistor is connected to the adjustment output node, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are connected to the output node, and the source of the second NMOS transistor is connected to ground end.

The first inverter is connected in series between the input node and the reverse input node, and the first inverter is powered by a second power supply; Two PMOS tubes and NMOS tubes between the power supply and the ground.

In one of the embodiments, the duty cycle unit includes a first buffer, and the first buffer adjusts the duty cycle of the output signal through a delay. Wherein, the first buffer is powered by the first power supply.

In one of the embodiments, the level conversion circuit further includes a feedback unit for performing feedback compensation on the output signal, and the feedback unit is coupled between the adjustment input node and the output node.

Preferably, the feedback unit includes a fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the adjustment input node; the source of the fifth NMOS transistor is connected to the ground terminal; the drain of the fifth NMOS transistor is connected to the output node. By setting the feedback unit, feedback compensation can be performed on the output signal when there are multiple power supplies, so as to avoid the phenomenon that the output node outputs high and low level errors.

In one of the embodiments, the level conversion circuit further includes an enabling unit for controlling the operation of the level conversion unit, and an output end of the enabling unit is connected to the adjustment input node. When the enabling unit is valid, the input signal of the level converting unit is shielded, so that the level converting unit cannot work.

Preferably, the enabling unit includes a seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the enable signal of the level conversion circuit, the source of the seventh PMOS transistor is connected to the first power supply, and the drain of the seventh PMOS transistor is connected to the adjustment input node. When the enable signal is at a low level, the input signal of the level conversion unit is shielded, and the level conversion circuit cannot work; when the enable signal is at a high level, the level conversion circuit works normally.

On the basis of the above embodiments, the level conversion circuit further includes a second inverter and a third inverter; the input end of the second inverter is connected to the output node, and the second inverter is connected to the output node. The output terminal is connected to the input terminal of the third inverter. By adding two-stage inverters, the output signal can be shaped to further improve the output signal quality.

Preferably, the second inverter includes a fifth PMOS transistor and a third NMOS transistor connected in series between the first power supply and the ground terminal, and the gate of the fifth PMOS transistor and the gate of the third NMOS transistor are connected as the first The input terminal of the second inverter is connected to the output node, the drain of the fifth PMOS transistor and the drain of the third NMOS transistor are connected as the output terminal of the second inverter and the input terminal of the third inverter connection; the source of the fifth PMOS transistor is connected to the first power supply, and the source of the third NMOS transistor is connected to the ground terminal.

Preferably, the third inverter includes a sixth PMOS transistor and a fourth NMOS transistor connected in series between the first power supply and the ground terminal, and the gate of the sixth PMOS transistor and the gate of the fourth NMOS transistor are connected as the first The input end of the three-inverter is connected to the output end of the second inverter, the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor as the output end of the third inverter; the sixth PMOS transistor The source of the NMOS transistor is connected to the first power supply, and the source of the fourth NMOS transistor is connected to the ground terminal.

As shown in FIG. 1 , the level conversion circuit provided by the embodiment of the present application includes a level conversion unit and a duty cycle unit; the level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, a regulator Input node A and adjust output node B.

The level conversion unit is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2 and a first inverter I1 .

The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the input node IN, the source of the first PMOS transistor P1 is connected to the first power supply VDDH, and the drain of the first PMOS transistor P1 is connected to the third PMOS The source of the transistor P3, the gate of the third PMOS transistor P3 is connected to the output node OUT, the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1 are connected to the adjustment input node A, and the source of the first NMOS transistor N1 The pole is connected to the ground terminal GND.

The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the reverse input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, and the drain of the second PMOS transistor P2 is connected to the first power supply VDDH. The source of the four PMOS transistors P4, the gate of the fourth PMOS transistor P4 is connected to the adjustment output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor P2 are connected to the output node OUT, and the second NMOS transistor N2 The source is connected to the ground terminal GND.

The first inverter I1 is connected in series between the input node IN and the reverse input node INB, and the first inverter I1 is powered by a second power supply VDDL; wherein the first inverter I1 includes PMOS tube and NMOS tube, the gate of the PMOS tube and the gate of the NMOS tube are connected as the input end of the first inverter I1, and the input end of the first inverter I1 is connected to the input node IN; the drain of the PMOS tube The pole is connected to the drain of the NMOS transistor as the output terminal of the first inverter I1, and the output terminal of the first inverter I1 is connected to the reverse input node INB; the source terminal of the PMOS transistor is connected to the second power supply VDDL, NMOS The source of the tube is connected to the ground terminal GND.

The duty cycle unit includes a first buffer BUF1, the first buffer BUF1 is coupled between the adjustment input node A and the adjustment output node B, and is powered by the first power supply VDDH, and is delayed by the first buffer BUF1 to adjust the duty cycle of the output signal.

Specifically, when the input node IN is at a high level, the first NMOS transistor N1 is turned on, the drain of the first NMOS transistor N1 is at a low level, and the low level turns on the fourth PMOS transistor P4 through the first buffer BUF1 In addition, the high level of the input node IN is reversed by the first inverter I1 (the reverse input node is a low level) and the second PMOS tube P2 is turned on, because the input signal reaches the gate of the second PMOS tube P2. The transmission path of the polar signal is shorter than the transmission path of the input signal to the gate signal of the fourth PMOS transistor P4, so the gate low level signal of the second PMOS transistor P2 will arrive earlier than the gate low level signal of the fourth PMOS transistor P4. , so the rising edge time of the output signal of the output node OUT will be controlled by the delay of the first buffer BUF1, and the rising edge time of the output signal directly affects the duty cycle, so as to achieve the purpose of adjusting the duty cycle of the output signal. The output signal quality is improved in the case of flat conversion unit transistor size.

Wherein, the output node OUT of the level conversion unit is the total output node of the level conversion circuit.

The first power supply VDDH is configurable according to circuit applications at 3.3V, 5V; the second power supply VDDL is configurable according to circuit applications at 1.2V, 1.35V, 1.5V, and 1.8V.

As shown in FIG. 2 , the level conversion circuit provided by the embodiment of the present application includes a level conversion unit, a duty cycle unit, and a feedback unit; the level conversion unit includes an input node IN, an inverse input node INB, and an output node OUT, regulated input node A, and regulated output node B.

The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the reverse input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, and the drain of the second PMOS transistor P2 is connected to the first power supply VDDH. The source of the four PMOS transistors P4, the gate of the fourth PMOS transistor P4 is connected to the adjustment output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2 are connected to the output node OUT, and the second NMOS transistor N2 The source is connected to the ground terminal GND.

The first inverter I1 is connected in series between the input node IN and the reverse input node INB, and the first inverter I1 is powered by a second power supply VDDL; wherein the first inverter I1 includes PMOS tube and NMOS tube, the gate of the PMOS tube and the gate of the NMOS tube are connected as the input end of the first inverter I1, the input end of the first inverter I1 is connected with the input node IN; the drain of the PMOS tube The pole is connected to the drain of the NMOS transistor as the output terminal of the first inverter I1, and the output terminal of the first inverter I1 is connected to the reverse input node INB; the source terminal of the PMOS transistor is connected to the second power supply VDDL, NMOS The source of the tube is connected to the ground terminal GND.

The feedback unit includes a fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is connected to the adjustment input node A, the drain of the fifth NMOS transistor N5 is connected to the output node OUT, and the source of the fifth NMOS transistor N5 is connected to the ground terminal GND .

Specifically, the first PMOS transistor P1, the third PMOS transistor P3, and the first NMOS transistor N1 of the level conversion unit are symmetrical with the second PMOS transistor P2, the fourth PMOS transistor P4, and the second NMOS transistor N2, that is, the first The drain level of the NMOS transistor N1 and the drain level of the second NMOS transistor N2 are opposite. When the power-on or power-off sequences are not synchronized in the multi-power supply, the feedback unit will feedback compensation for the output signal, so that the The output node OUT outputs a level signal determined by the high and low states.

As shown in FIG. 3 , the level conversion circuit provided by the embodiment of the present application includes a level conversion unit, a duty cycle unit, a feedback unit and an enabling unit; the level conversion unit includes an input node IN and an inverse input node INB, output node OUT, regulation input node A, and regulation output node B.

The enabling unit includes a seventh PMOS transistor P7, the gate of the seventh PMOS transistor P7 is connected to the enable signal EN, the source of the seventh PMOS transistor P7 is connected to the first power supply VDDH, and the drain of the seventh PMOS transistor P7 is connected to Adjust input node A.

When the enable signal EN is at a low level, the seventh PMOS transistor P7 is turned on and the gate of the fifth NMOS transistor N5 is pulled high, so that the drain of the fifth NMOS transistor N5 is pulled low, and the output node OUT is at a low level , after the two-stage inverter, the output of the level conversion circuit is low level. At this time, regardless of whether the input node IN is high level or low level, the output signal is always low level; when the enable signal EN is high level When the level is turned off, the seventh PMOS transistor P7 is turned off and does not work, and cannot shield the input signal of the input node IN. At this time, the level conversion circuit works normally.

As shown in FIG. 4 , the level conversion circuit provided by the embodiment of the present application includes a level conversion unit, a duty cycle unit, a feedback unit, an enabling unit, a second inverter, and a third inverter;

The level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, an adjustment input node A and an adjustment output node B.

The input terminal of the second inverter is connected to the output node OUT, and the output terminal of the second inverter is connected to the input terminal of the third inverter. By adding two-stage inverters, the output signal can be shaped to further improve the output signal quality.

The second inverter I2 includes a fifth PMOS transistor P5 and a third NMOS transistor N3. The gate of the fifth PMOS transistor P5 and the gate of the third NMOS transistor N3 are connected as the input terminal of the second inverter I2 and the The output node OUT is connected, and the drain of the fifth PMOS transistor P5 and the drain of the third NMOS transistor N3 are connected as the output end of the second inverter I2 is connected to the input end of the third inverter I3; The source of the transistor P5 is connected to the first power supply VDDH, and the source of the third NMOS transistor N3 is connected to the ground terminal GND.

The third inverter I3 includes a sixth PMOS transistor P6 and a fourth NMOS transistor N4. The gate of the sixth PMOS transistor P6 and the gate of the fourth NMOS transistor N4 are connected as the input end of the third inverter I3 and the The output terminal of the second inverter I2 is connected, the drain of the sixth PMOS transistor P6 is connected to the drain of the fourth NMOS transistor N4 as the output terminal of the third inverter I3; the source of the sixth PMOS transistor P6 is connected to the A power supply VDDH, the source of the fourth NMOS transistor N4 is connected to the ground terminal GND.

Wherein, the output terminal of the third inverter I3 is the total output node OUT' of the level conversion circuit.

The working project of the level conversion unit of the embodiment of the present application:

When the input signal of the input node IN is at a low level, the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off; The level turns off the second PMOS transistor P2 and turns on the second NMOS transistor N2, so the drain of the second NMOS transistor N2 is at a low level (pulled down), and then the third PMOS transistor P3 is turned on, and the third PMOS transistor N2 is turned on. The drain of P3 is at a high level (pulled high), and the fourth PMOS transistor P4 is turned off after passing through the first buffer BUF1, which further ensures that the drain of the second NMOS transistor N2 is at a low level, and passes through the two-stage inverter (I2 , I3), the total output node OUT' is low.

When the input signal of the input node IN is at a high level, the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on; the input signal (high level) is at a low level after passing through the first inverter I1, the low level The level turns on the second PMOS transistor P2 and turns off the second NMOS transistor N2; the first NMOS transistor N1 is turned on, the drain of the first NMOS transistor N1 is low level (pulled down), and then the fifth NMOS transistor N5 is turned on. is turned off, and the fourth PMOS transistor P4 is turned on through the first buffer BUF1, so the drain of the fourth PMOS transistor P4 is at a high level (pulled high), which in turn turns off the third PMOS transistor P3, and Ensure that the drain of the first NMOS transistor N1 is at a low level (pulled low); after the high level of the drain of the fourth PMOS transistor P4 passes through the two-stage inverters (I2, I3), the total output node OUT' is at a high level flat.

The first PMOS transistor P1, the third PMOS transistor P3, and the first NMOS transistor N1 of the level conversion unit are symmetrical with the second PMOS transistor P2, the fourth PMOS transistor P4, and the second NMOS transistor N2, that is, the first NMOS transistor N1 The drain level of the second NMOS transistor N2 is opposite to the drain level of the second NMOS transistor N2. When the power-on or power-off sequence is not synchronized in the multi-power supply, the feedback unit will perform feedback compensation on the output signal, so that the output node OUT Output the level signal determined by the high and low state.

When the input node IN is at a high level, the first NMOS transistor N1 is turned on, the drain of the first NMOS transistor N1 is at a low level, and the low level turns on the fourth PMOS transistor P4 through the first buffer BUF1; in addition, The high level of the input node IN is reversed by the first inverter I1 (the reverse input node is low level), and the second PMOS transistor P2 is turned on. Since the input signal reaches the gate signal transmission of the second PMOS transistor P2 The path is shorter than the gate signal transmission path of the input signal reaching the fourth PMOS transistor P4, so the gate low level signal of the second PMOS transistor P2 will arrive earlier than the gate low level signal of the fourth PMOS transistor P4, so the output The rising edge time of the output signal of the node OUT will be controlled by the delay of the first buffer BUF1. The rising edge time of the output signal directly affects the duty cycle, so as to achieve the purpose of adjusting the duty cycle of the output signal without changing the level conversion unit. In the case of transistor size, the output signal quality is improved.

The above are only the embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the inventive concept of the present application, but these belong to the present application. scope of protection.

Claims

A level conversion circuit, comprising a level conversion unit and a duty cycle unit;

The level conversion unit includes: an input node, an output node for outputting an output signal having a desired level, an adjustment input node, and an adjustment output node for adjusting the duty ratio of the output signal;

the duty cycle unit is coupled between the adjustment input node and the adjustment output node;

The duty cycle unit is used to adjust the duty cycle of the output signal.
The level conversion circuit according to claim 1, further comprising a feedback unit, the feedback unit is coupled between the adjustment input node and the output node;

The feedback unit is used for feedback compensation for the output signal.
The level conversion circuit according to claim 2, further comprising an enabling unit, an output end of the enabling unit is connected to the adjustment input node;

the enabling unit for controlling the level conversion unit to work;

Wherein, the level conversion unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter;

The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the input node, the source of the first PMOS transistor is connected to the first power supply, and the drain of the first PMOS transistor is connected to the first power supply. The source of the three PMOS transistors, the gate of the third PMOS transistor is connected to the output node, the drain of the third PMOS transistor and the drain of the first NMOS transistor are connected to the adjustment input node, and the first NMOS transistor is connected to the adjustment input node. The source of an NMOS transistor is connected to the ground terminal;

The gate of the second PMOS tube and the gate of the second NMOS tube are connected to the reverse input node, the source of the second PMOS tube is connected to the first power supply, and the drain of the second PMOS tube is connected to the first power supply. The source of four PMOS transistors, the gate of the fourth PMOS transistor is connected to the adjustment output node, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are connected to the output node, and the fourth PMOS transistor is connected to the output node. The sources of the two NMOS tubes are connected to the ground terminal;

The first inverter is connected in series between the input node and the reverse input node, and the first inverter is powered by a second power supply.
The level conversion circuit according to any one of claims 1, 2 or 3, further comprising a second inverter and a third inverter; the input end of the second inverter is connected to the The output node is connected, and the output end of the second inverter is connected with the input end of the third inverter.
The level conversion circuit according to claim 4, wherein the feedback unit comprises a fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the adjustment input node; the source of the fifth NMOS transistor is connected to the ground terminal; the drain of the fifth NMOS transistor is connected to the output node.
The level shifting circuit according to claim 4, wherein the enabling unit comprises a seventh PMOS transistor, a gate of the seventh PMOS transistor is connected to an enable signal of the level shifting circuit, and the seventh PMOS transistor The source of the PMOS is connected to the first power supply, and the drain of the seventh PMOS transistor is connected to the adjustment input node.
The level conversion circuit according to claim 4, wherein the second inverter and the third inverter both comprise a PMOS transistor and an NMOS transistor connected in series between the first power supply and the ground; in,

The second inverter includes a fifth PMOS transistor and a third NMOS transistor connected in series between the first power supply and the ground terminal, the gate of the fifth PMOS transistor and the gate of the third NMOS transistor The input terminal of the second inverter is connected to the output node, and the drain of the fifth PMOS transistor and the drain of the third NMOS transistor are connected as the output terminal of the second inverter to the output node of the second inverter. The input terminal of the three-inverter is connected; the source of the fifth PMOS transistor is connected to the first power supply, and the source of the third NMOS transistor is connected to the ground terminal;

The third inverter includes a sixth PMOS transistor and a fourth NMOS transistor connected in series between the first power supply and the ground terminal, and the gate of the sixth PMOS transistor and the gate of the fourth NMOS transistor The input terminal of the third inverter is connected to the output terminal of the second inverter, and the drain of the sixth PMOS transistor and the drain of the fourth NMOS transistor are connected as the output terminal of the third inverter. an output terminal; the source of the sixth PMOS transistor is connected to the first power supply, and the source of the fourth NMOS transistor is connected to the ground terminal.