JP4640788B2 - Level conversion circuit - Google Patents

Description

  The present invention relates to a level conversion circuit that converts a low amplitude signal into a high amplitude signal and outputs the converted signal.

  FIG. 7 shows an example of a conventional level conversion circuit. As described in FIG. 6 of Patent Document 1, this level conversion circuit is a conventionally known circuit that converts an input signal Si having a low voltage VL into a signal So having a high voltage VH and outputs the signal So. Two PMOS transistors 12 and 14, two NMOS transistors 16 and 18, and a CMOS inverter 20 that operates with a power source of a low voltage VL are provided.

  Here, the PMOS transistor 12 and the NMOS transistor 16 are connected in series between the power supply and the ground of the high voltage VH via the node A, and similarly, the PMOS transistor 14 and the NMOS transistor 18 are connected to the high voltage via the node B. It is connected in series between the VH power supply and ground. The gate of the PMOS transistor 12 is connected to the node B, the gate of the PMOS transistor 14 is connected to the node A, and the node B is connected to the output terminal OUT.

  The gate of the NMOS transistor 16 is connected to the input terminal IN of the input signal Si having the amplitude of the low voltage VL, and the gate of the NMOS transistor 18 is connected to the input terminal IN via the inverter 20. The sources and substrates of the PMOS transistors 12 and 14 are both connected to the power source of the high voltage VH, and the sources and substrates of the NMOS transistors 16 and 18 are both connected to the ground.

  Note that the low voltage VL and the high voltage VH have a relationship of VL <VH. The high level of the input signal Si is the low voltage VL, and the high level of the output signal So is the high voltage VH.

In this level conversion circuit, when a low level (ground level) is input as the input signal Si, the NMOS transistor 16 is in an off state, the output of the inverter 20 is at a high level (VL), and the NMOS transistor 18 is in an on state. . Accordingly, the node B (output signal So) is at the low level, the PMOS transistor 12 is in the on state, the node A is at the high level (VH), and the PMOS transistor 14 is in the off state.
Japanese Patent Laid-Open No. 9-200020

  In the level conversion circuit of FIG. 7, when the input signal Si transitions from the low level to the high level, the PMOS transistor 14 is driven via the NMOS transistor 16 and the NMOS transistor 18 is driven via the inverter 20. That is, since both the PMOS transistor 14 and the NMOS transistor 18 until the output signal So is determined to be at a high level are driven through a single-stage transistor, the operations are simultaneous.

  However, when the input signal Si transitions from the high level to the low level, the NMOS transistor 18 is driven only through the inverter 20, but the PMOS transistor 14 has a high impedance when the NMOS transistor 16 is turned off. When the node B transitions to the low level, the PMOS transistor 12 is turned on and the node A becomes the high level, and the PMOS transistor 14 is driven off. Therefore, the node B is driven through the multistage transistor. Therefore, it takes a long time for the output signal So to be fixed at the low level.

  From the above, the delay time from when the input signal Si changes from the low level to the high level until the output signal So similarly changes until the output signal So similarly changes after the transition from the high level to the low level. The delay time will be longer.

  As described above, the conventional level conversion circuit can be regarded as a differential circuit having the gates of the NMOS transistors 16 and 18 as input terminals. However, the delay time varies depending on the transition direction, and the symmetry is poor.

  This difference in delay time can be reduced to some extent by adjusting the circuit constants, but it cannot be dealt with when conditions such as changes in the slope of the input signal Si (rise / fall slope) change. .

  For example, when the rising / falling of the input signal Si becomes gentle, the falling / rising timing of the output of the inverter 20 may be earlier than the timing at which the NMOS transistor 16 is turned on / off. The NMOS transistor 18 is turned off / on earlier than the transistor 16 is turned on / off, and the operation symmetry is further deteriorated.

  The object of the present invention is that there is no need to adjust circuit constants, and even if the slope of the input signal varies, the delay time from the transition of the input signal to the transition of the output signal is not greatly dependent on the transition direction. An object of the present invention is to provide a level conversion circuit.

In order to solve the above problems, the present invention provides a first PMOS transistor and a first NMOS transistor connected in series via a first node between a high voltage power source and ground, a high voltage power source and ground. A second PMOS transistor and a second NMOS transistor connected in series via a second node, and a first inverter that operates with a low-voltage power supply, and an input terminal of the first NMOS transistor The gate of the transistor is connected to the input of the first inverter, the output terminal is connected to the second node and the gate of the first PMOS transistor, and the gate of the second PMOS transistor is connected to the first node. connected, the gate of the second NMOS transistor is connected to the output of the first inverter, Rourebe the input terminal from a high level Wherein when transitioning second NMOS transistor receives the delayed only by the first inverter in the level conversion circuit according to the ON state, the first NMOS transistor, a drain and a source connected in common and in total The fifth NMOS transistor is replaced with the fifth NMOS transistor equivalent to the second NMOS transistor, the gate of the fifth NMOS transistor is used as the input terminal, and the gate of the sixth NMOS transistor is used as the output of the first inverter. Is connected to the output of the second inverter that inverts the signal, and when the input terminal transitions from the low level to the high level, the potential of the first node is reduced by the delay caused by the first and second inverters. It was made to become .

Here, instead of the second inverter, a third inverter having an input connected to the input terminal, an input connected to the output of the third inverter, and an output connected to the gate of the sixth NMOS transistor Using a connected fourth inverter, when the input terminal transitions from a low level to a high level, the potential of the first node becomes a low level due to a delay caused by the first and second inverters. Instead of this, when the input terminal transitions from the low level to the high level, the potential of the first node may be set to the low level in response to the delay by the third and fourth inverters .

  It is preferable that a seventh NMOS transistor having a source and a drain connected between the first node and the gate of the second NMOS transistor and having a gate connected to the low voltage power source is provided. .

  According to the present invention, the NMOS transistors on both sides acting as the input differential circuit operate at almost the same timing, so that the delay time from the transition of the input signal to the transition of the output signal can be reduced without fine adjustment of the circuit constant. The transition from the low level to the high level and the transition from the high level to the low level can be made substantially the same, and good transition direction symmetry can be ensured. Further, even when the rising / falling slope of the input signal varies, it is possible to ensure a good transition direction symmetry.

  In the present invention, the NMOS transistor 16 shown in FIG. 7 is replaced with two NMOS transistors connected in parallel. The two NMOS transistors connected in parallel are generally equivalent to the conventional NMOS transistor 16 (also equivalent to the NMOS transistor 18). That is, when all the NMOS transistors connected in parallel are turned on / off, it is equivalent to turning on / off the NMOS transistor 16. Then, by applying an input signal or a signal obtained by delaying the input signal to each gate of the plurality of NMOS transistors, the operating characteristics of the NMOS transistors on both sides of the input differential circuit are made equal, The delay time from the transition of the input signal to the transition of the output signal is prevented from causing a large difference depending on the transition direction. This will be described in detail below.

  1 is a circuit diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention. This level conversion circuit includes two PMOS transistors 12 and 14, three NMOS transistors 46, 47 and 18, and two CMOS inverters 20 and 40. In the circuit shown in FIG. 7, the NMOS transistor 16 is replaced with NMOS transistors 46 and 47, and an inverter 40 is newly added.

  Here, the NMOS transistors 46 and 47 have their sources and drains connected in common, and the two NMOS transistors 46 and 47 are equivalent to the NMOS transistor 16 (also equivalent to the NMOS transistor 18). The gate of the NMOS transistor 46 is connected to the input terminal IN, and the gate of the NMOS transistor 47 is connected to the output of the inverter 40. The input of the inverter 40 is connected to the output of the inverter 20.

  As a result, the input signal Si of the input terminal IN is inputted as it is to the gate of the NMOS transistor 46, but the input signal Si of the input terminal IN is inputted to the gate of the NMOS transistor 47 via the inverters 20 and 40. It will be.

  Now, when the input signal Si transitions from the high level to the low level, the NMOS transistor 46 is immediately turned off, but the NMOS transistor 47 is turned off in response to the delay by the two-stage inverters 20 and 40, so that the node The potential of A changes depending on the timing at which the NMOS transistor 47 is turned off. The NMOS transistor 18 is turned on in response to a delay by the inverter 20 in one stage. When the node B transitions in the low level direction and the PMOS transistor 12 is turned on, the node A becomes high level and the PMOS transistor 14 is turned off. The low level of node B is determined. The delay time from the transition of the input signal Si at this time to the low level to the transition of the node B to the low level is the same as in the circuit of FIG.

  On the other hand, when the input signal Si transitions from the low level to the high level, the NMOS transistor 46 is turned on, but the NMOS transistor 47 is turned on in response to the delay by the two-stage inverters 20 and 40, so that the node A Is completely at a low level when the NMOS transistor 47 is turned on. That is, the timing at which the potential of the node A becomes low level is delayed by the inverters 20 and 40. Further, the NMOS transistor 18 is turned off in response to the delay by the one-stage inverter 20. Therefore, the timing at which the potential of the node B is determined at the high level is determined by the delay of the inverters 20 and 40, and is delayed from the conventional level shift circuit shown in FIG.

  From the above, when the input signal Si changes from the high level to the low level, the output signal So changes from the high level to the low level with the same delay as the conventional circuit of FIG. 7, but the input signal Si changes from the low level to the high level. When the output signal So transitions from a low level to a high level with a delay greater than that of the conventional circuit of FIG. 7, the delay time from the transition of the input signal Si to the transition of the output signal So is determined in any direction. The same time is also applied to the transitions of, and the symmetry of the differential circuit can be maintained.

  In this level conversion circuit, since the input signal Si is amplified in two stages of the inverters 20 and 40 and input to the gate of the NMOS transistor 47, the rising / falling of the input signal Si is slow. Even when the timing at which the output of the inverter 20 changes to the low level / high level becomes faster than the on / off timing of the transistor 46, the NMOS transistor 47 is turned on / off at a fast timing, and the NMOS transistor 18 and the NMOS transistor 46 and 47 can be controlled at the same time, and the symmetry of the differential circuit can be maintained.

  FIG. 2 is a circuit diagram showing the configuration of the level conversion circuit according to the second embodiment of the present invention. In the level conversion circuit of FIG. 2, the path for applying the input signal Si to the gate of the NMOS transistor 47 is constituted by two independent CMOS inverters 40 and 41, and the inverter 20 only drives the NMOS transistor 18. It is.

  The operation of this level conversion circuit is exactly the same as that of the level conversion circuit of FIG. 1, but since the inverters 40 and 41 for driving the NMOS transistor 47 are made independent, the adjustment can be performed independently, and the optimum adjustment is possible. It becomes easy to do. This also applies to the inverter 20.

  FIG. 3 is a circuit diagram showing the configuration of the level conversion circuit according to the third embodiment of the present invention. The level conversion circuit of FIG. 3 is the same as the level conversion circuit of FIG. 1 except that an NMOS transistor 22 is connected between the node A and the output of the inverter 20, and its gate is connected to the power supply of the low voltage VL.

  In this level conversion circuit, when the input signal Si is at high level, the node A is at low level and the output of the inverter 20 is also at low level, so the NMOS transistor 22 is on.

  When the input signal Si transits from high level to low level, the output of the inverter 20 transits from low level to high level. However, since the NMOS transistor 22 is on, the node A changes when the output of the inverter 20 transits in the high level direction. Is instantaneously charged to a voltage level of “VL−Vth” (Vth is the threshold voltage of the MOS transistor 22) via the MOS transistor 22. The MOS transistor 22 is turned off when the node A exceeds the voltage level of “VL−Vth”. As a result, the off timing of the transistor 14 is advanced, and the delay time from the transition of the output signal So from the high level to the low level when the input signal Si transitions from the high level to the low level can be shortened.

  In the conventional level conversion circuit of FIG. 7, the delay when the input signal Si transitions from the high level to the low level is longer than the delay when the input signal Si transitions from the low level to the high level. This can be shortened in the conversion circuit. Therefore, in the level conversion circuit of FIG. 3, the delay is made longer than that of the conventional circuit of FIG. 7 when the input signal Si transitions from the low level to the high level as in the level conversion circuit of FIGS. Since the delay can be shortened compared with the conventional circuit of FIG. 7 when the signal transits from the high level to the low level, the symmetry of the delay time can be further improved.

Delay characteristics comparison

  4 is a simulation result of delay characteristics of the conventional level conversion circuit shown in FIG. 7, FIG. 5 is a simulation result of delay characteristics of the level conversion circuit of FIG. 1, and FIG. 6 is a simulation of delay characteristics of the level conversion circuit of FIG. In the graph, Tr on the horizontal axis represents the rise time of the input signal Si, Tf represents the fall time, Tplh on the vertical axis represents the delay time from the low level to the high level, and Tph1 represents the high level to the low level. The delay time of transition to Tplh-Tphl shows the difference.

  As is apparent from FIGS. 4 to 6, the delay times Tplh and Tph1 of the transition become larger as the Tr and Tf of the input signal become larger and show dependency. The difference is a characteristic of the conventional characteristic. FIG. 5 which is the characteristic of the first embodiment is less than 4 and the symmetry is improved, and in FIG. 6 which is the characteristic of the third embodiment, there is almost no difference and the symmetry is further improved. I understand.

It is a circuit diagram which shows the structure of the level conversion circuit of Example 1 of this invention. It is a circuit diagram which shows the structure of the level conversion circuit of Example 2 of this invention. It is a circuit diagram which shows the structure of the level conversion circuit of Example 3 of this invention. It is a delay characteristic figure of the conventional level conversion circuit. FIG. 3 is a delay characteristic diagram of the level conversion circuit according to the first embodiment. FIG. 10 is a delay characteristic diagram of the level conversion circuit according to the third embodiment. It is a circuit diagram which shows the structure of the conventional level conversion circuit.

Claims (3)

A first PMOS transistor and a first NMOS transistor connected in series via a first node between a high voltage power supply and ground, and a series connected via a second node between the high voltage power supply and ground. A second PMOS transistor and a second NMOS transistor connected to each other; and a first inverter that operates with a low-voltage power supply; and an input terminal connected to a gate of the first NMOS transistor and an input of the first inverter. An output terminal connected to the second node and the gate of the first PMOS transistor; a gate of the second PMOS transistor connected to the first node; and a gate of the second NMOS transistor connected to the output of the first inverter, the second NMOS when the input terminal changes from a high level to the low level Transistors in the level converter circuit according to the on state by receiving the delay only by the first inverter,
The first NMOS transistor is replaced with fifth and sixth NMOS transistors whose drain and source are connected in common and equivalent to the second NMOS transistor in total, and the gate of the fifth NMOS transistor is the input terminal In addition, by connecting the gate of the sixth NMOS transistor to the output of the second inverter that inverts the output of the first inverter, the first and the second NMOS transistors are switched when the input terminal changes from low level to high level. A level conversion circuit characterized in that a potential of the first node is set to a low level in response to a delay by a second inverter . The level conversion circuit according to claim 1, wherein instead of the second inverter, a third inverter having an input connected to the input terminal, an input connected to an output of the third inverter, and an output being the output Using a fourth inverter connected to the gate of the sixth NMOS transistor ;
Instead of the delay of the first and second inverters causing the potential of the first node to become low level when the input terminal transitions from low level to high level,
A level conversion circuit characterized in that when the input terminal transitions from a low level to a high level, the potential of the first node is set to a low level in response to a delay by the third and fourth inverters . In the level conversion circuit according to claim 1 or 2,
A level conversion circuit comprising a seventh NMOS transistor having a source and a drain connected between the first node and the gate of the second NMOS transistor, and a gate connected to the low voltage power source. .

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