JPH05129849A - If limiter amplifier circuit - Google Patents

If limiter amplifier circuit

Info

Publication number
JPH05129849A
JPH05129849A JP3311841A JP31184191A JPH05129849A JP H05129849 A JPH05129849 A JP H05129849A JP 3311841 A JP3311841 A JP 3311841A JP 31184191 A JP31184191 A JP 31184191A JP H05129849 A JPH05129849 A JP H05129849A
Authority
JP
Japan
Prior art keywords
current
circuit
differential
signal
inverter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3311841A
Other languages
Japanese (ja)
Inventor
Katsuharu Kimura
克治 木村
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP3311841A priority Critical patent/JPH05129849A/en
Publication of JPH05129849A publication Critical patent/JPH05129849A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G11/00Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
    • H03G11/002Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general without controlling loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Abstract

(57) [Summary] [Object] To provide a C-MOS type IF limiter amplifier circuit capable of reducing a drive current and obtaining an excellent limiting characteristic. [Structure] The MOS transistors (M1, M2) are differential amplifiers driven by a constant current source I 0 , and receive an IF signal (voltage V IF ). MOS transistor (M3, M
4) and (M5, M6) (M7, M8) respectively form a current mirror circuit, generate a differential current of the differential current of the differential amplifier composed of (M1, M2), and use the MOS transistors (M9, M10). ) Drive the inverter circuit. The MOS transistors (M11, M12) are also inverter circuits, and a signal (voltage V OUT ) in which the IF signal is sufficiently limited is output from this second-stage inverter circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IF limiter amplifier circuit formed in a C-MOS integrated circuit.

[0002]

2. Description of the Related Art IF using a conventional MOS transistor
The limiter amplifier circuit has a configuration in which differential amplifiers are cascade-connected in multiple stages as in the IF limiter amplifier circuit using bipolar transistors.

[0003]

DISCLOSURE OF THE INVENTION The conventional MOS described above
In the IF limiter amplifier circuit using transistors, when the load of the differential amplifier is made to be a resistance, the MOS transistor has a lower mutual conductance and a lower driving capability than the bipolar transistor, so that the value of the constant current source for driving the circuit is increased. There is a problem that needs to be done.

Further, when the load of the differential amplifier is an active load, the load becomes lighter, so that the drive current of the circuit can be reduced. However, since the output amplitude fluctuates almost from the power supply voltage to the voltage of the common source of the differential pair, it is difficult to fix the voltage of the common source, and there is also a problem that good limiting characteristics cannot be obtained.

It is an object of the present invention to provide a C-MOS type IF limiter amplifier circuit which can reduce the drive current and obtain good limiting characteristics.

[0006]

In order to achieve the above object, the IF limiter amplifier circuit of the present invention has the following configuration. That is, the IF limiter amplifier circuit of the present invention is a CM
An IF limiter amplifier circuit formed in an OS integrated circuit; the IF limiter amplifier circuit includes a differential amplifier to which an IF signal is input; and a current mirror circuit that generates a differential current of a differential current of the differential amplifier. And one or more inverter circuits driven by the difference current generated by the current mirror circuit.

[0007]

Next, the operation of the IF limiter amplifier circuit of the present invention constructed as described above will be described. In the present invention, since the inverter circuit is driven by the difference current of the differential current of the differential amplifier to which the IF signal is input, the output amplitude of the inverter circuit, which changes depending on whether the IF signal is positive or negative, is set to the power supply voltage level. Can be limited to the ground voltage level. Moreover, this limiting characteristic is not affected by manufacturing variations and temperature fluctuations, and maintains stable characteristics. Further, since the load of the differential amplifier is light and the subsequent stage is an inverter circuit which operates at the IF frequency, the circuit current can be greatly reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an IF limiter amplifier circuit according to an embodiment of the present invention. In FIG. 1, a MOS transistor (M
1, M2) are differential amplifiers driven by a constant current source I 0 , and have an IF signal (voltage V IF ) as an input. MOS transistors (M3, M4), same (M5, M6) and same (M
7, M8) respectively constitute a current mirror circuit,
The differential current of the differential current of the differential amplifier including the MOS transistors (M1, M2) is generated, and the
9, M10) to drive the inverter circuit. MO
The S transistors (M11, M12) are also inverter circuits, and a signal (voltage V OUT ) obtained by sufficiently limiting the IF signal is obtained from this second-stage inverter circuit. The details will be described below.

If the ratio (W / L) of the gate width W and the gate length L is the same in the MOS transistors M1 and M2,
The drain currents I d1 and I d2 of the respective drain currents are represented by Formulas 1 and 2 respectively.
Therefore, the constant current source I 0 is given by Equation 3, and the input voltage (V IF ) is given by Equation 4. Note that β in Equations 1 and 2 is expressed as Equation 5 by the electron mobility μ n and the oxide film capacitance C OX per unit gate.

[0010]

[Equation 1]

[0011]

[Equation 2]

[0012]

[Equation 3]

[0013]

[Equation 4]

[0014]

[Equation 5]

Then, when the difference current ΔI d between the drain currents is obtained from the equations 1 to 4, the equation 6 is obtained.

[0016]

[Equation 6]

Therefore, from the equations 3 and 6, the drain current I d1 is obtained as the equation 7 and the drain current I d2 is obtained as the equation 8.

[0018]

[Equation 7]

[0019]

[Equation 8]

In summary, the MOS transistor (M
3, M4), the same (M5, M6) and the same (M7, M8), in the current mirror circuit, the differential current (I d1 ,
Generating a difference current [Delta] I d of I d2), this difference current [Delta] I d
Serves as a common drain of M4 and M8, and the inverter circuit composed of MOS transistors (M9, M10) is driven by the common drain current.

Therefore, from Equation 6, when the input voltage V IF is positive, ΔI d > 0, and the MOS transistor (M
9, the current is discharged to the common gate of the first inverter circuit composed of M10), so that in the first inverter circuit, the common gate becomes high level and the output becomes low level. As a result, in the second inverter circuit including the MOS transistors (M11, M12), the common gate is at the low level, and therefore the output (V OUT ) is at the high level. That is,
It becomes the level of the power supply voltage.

Next, in the opposite case, that is, when the input voltage V IF is negative, ΔI d <0, and the current is drawn from the common gate of the first inverter circuit. Goes low and the output goes high. As a result, in the second inverter circuit, the common gate is at a high level, so that the output (V OUT ) is at a low level. That is, it becomes the level of the ground voltage.

Here, since each inverter circuit has a high current gain, when the input voltage V IF changes and the difference current ΔI d changes from positive to negative or from negative to positive, the second inverter circuit. The output V OUT of the circuit immediately changes from the power supply voltage to the ground voltage or from the ground voltage to the power supply voltage. In other words, the output amplitude of the second inverter circuit is set so that the driving capability of the second inverter circuit is set high or
If the load of the inverter circuit is lightened, it is possible to form a rectangular wave in which the power supply voltage and the ground voltage are limited.

Therefore, as an IF limiter amplifier circuit,
Gate length L of MOS transistor due to manufacturing variations
Even if the variation occurs or the size of the constant current source I 0 varies, the limiting operation is determined by the power supply voltage.
The characteristics will hardly change.

Further, the change in characteristics also becomes small with respect to the temperature change. Further, the load of the differential amplifier becomes lighter, and since the subsequent stage is the inverter circuit which operates at the IF frequency, the circuit current also becomes small.

[0026]

As described above, according to the IF limiter amplifier circuit of the present invention, the inverter circuit is driven by the differential current of the differential current of the differential amplifier to which the IF signal is input. It is possible to limit the output amplitude of the inverter circuit, which changes depending on whether the signal is positive or negative, to the power supply voltage level and the ground voltage level. Moreover, this limiting characteristic is not affected by manufacturing variations and temperature fluctuations, and maintains stable characteristics. Further, since the load of the differential amplifier is light and the subsequent stage is an inverter circuit which operates at the IF frequency, there is an effect that the circuit current can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an IF limiter amplifier circuit according to an embodiment of the present invention.

[Explanation of symbols]

I 0 constant current source M1 MOS transistor M2 MOS transistor M3 MOS transistor M4 MOS transistor M5 MOS transistor M6 MOS transistor M7 MOS transistor M8 MOS transistor M9 MOS transistor M10 MOS transistor M11 MOS transistor M12 MOS transistor V IF input voltage V OUT output voltage ΔI d Difference current

Claims (1)

[Claims]
1. An IF limiter amplifier circuit formed in a C-MOS integrated circuit, wherein the IF limiter amplifier circuit is a differential amplifier to which an IF signal is input; and a difference between differential currents of the differential amplifier. An IF limiter amplifier circuit, comprising: a current mirror circuit that generates a current; and one or more inverter circuits that are driven by the difference current generated by the current mirror circuit.
JP3311841A 1991-10-30 1991-10-30 If limiter amplifier circuit Pending JPH05129849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3311841A JPH05129849A (en) 1991-10-30 1991-10-30 If limiter amplifier circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3311841A JPH05129849A (en) 1991-10-30 1991-10-30 If limiter amplifier circuit
GB9222906A GB2261338B (en) 1991-10-30 1992-10-30 Amplitude limiting amplifier and method of amplitude limiting

Publications (1)

Publication Number Publication Date
JPH05129849A true JPH05129849A (en) 1993-05-25

Family

ID=18022051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3311841A Pending JPH05129849A (en) 1991-10-30 1991-10-30 If limiter amplifier circuit

Country Status (2)

Country Link
JP (1) JPH05129849A (en)
GB (1) GB2261338B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167050B2 (en) 1999-08-10 2007-01-23 Oki Electric Industry Co., Ltd. Operational amplifier having large output current with low supply voltage

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61281715A (en) * 1985-06-07 1986-12-12 Matsushita Electric Ind Co Ltd Inverter circuit
JPS62260422A (en) * 1986-05-06 1987-11-12 Rohm Co Ltd Interface circuit
JPS6465921A (en) * 1987-09-04 1989-03-13 Nec Corp Waveform shaping circuit
JPH0529847A (en) * 1991-07-10 1993-02-05 Fujitsu Ltd Active load circuit and differential amplifier circuit using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0111230B1 (en) * 1982-11-26 1987-03-11 Nec Corporation Voltage comparator circuit
US4598215A (en) * 1983-11-03 1986-07-01 Motorola, Inc. Wide common mode range analog CMOS voltage comparator
US4670671A (en) * 1986-02-19 1987-06-02 Advanced Micro Devices, Inc. High speed comparator having controlled hysteresis
US4937476A (en) * 1988-06-16 1990-06-26 Intel Corporation Self-biased, high-gain differential amplifier with feedback

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61281715A (en) * 1985-06-07 1986-12-12 Matsushita Electric Ind Co Ltd Inverter circuit
JPS62260422A (en) * 1986-05-06 1987-11-12 Rohm Co Ltd Interface circuit
JPS6465921A (en) * 1987-09-04 1989-03-13 Nec Corp Waveform shaping circuit
JPH0529847A (en) * 1991-07-10 1993-02-05 Fujitsu Ltd Active load circuit and differential amplifier circuit using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167050B2 (en) 1999-08-10 2007-01-23 Oki Electric Industry Co., Ltd. Operational amplifier having large output current with low supply voltage

Also Published As

Publication number Publication date
GB2261338A (en) 1993-05-12
GB9222906D0 (en) 1992-12-16
GB2261338B (en) 1995-07-05

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