JP3171518B2 - BIMOS circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BIMOS circuit having a bipolar transistor and a MOS transistor.

[0002]

2. Description of the Related Art Generally, bipolar transistors and MOS transistors are used.
A BIMOS circuit including a transistor has high load driving capability by a bipolar transistor, low power consumption by forming a MOS transistor in a CMOS configuration, and high integration by a MOS transistor. LS with low power and fast operation speed
I can be realized at low cost, and DRAM and SRA
Memory LSI such as M, logic LSI such as gate array
Widely used for

A conventional configuration of such a BIMOS circuit will be described with reference to an inverter circuit shown in FIG. This inverter circuit is a P-channel MOS transistor M1
, An N-channel MOS transistor M2, an NPN-type bipolar transistor Q1, and an N-channel MOS transistor M3.

The transistors M1 and M2 form a CMOS inverter, each of which has an input terminal V _IN connected to its gate, a drive power supply V _CC connected to the source of the transistor M1, and a ground power supply V _SS connected to the source of the transistor M2. Is connected. The drains of the transistors M1 and M2 are commonly connected at a node N _A , and this node N A
_A is connected to the base of transistor Q1.

On the other hand, the collector of the transistor Q1 is connected to the drive power supply _Vcc , and the emitter is connected to the output terminal _Vout . The source of the transistor M3 is the ground power supply V.
_ss , gate to input terminal V _IN , drain to output terminal V _IN
out is connected to each.

In the inverter circuit configured as described above, when charging a load capacitance (not shown) such as a wiring connected to the output terminal _Vout or an input capacitance of a gate at the next stage, the transistor M1 and the transistor Q1 are charged. And the transistor M3 is used to discharge the load capacitance. Hereinafter, this will be described.

When the potential of the input terminal V _IN becomes low level (ground potential V _SS level, for example, zero V), the P-channel MO
S transistor M1 is turned on, and N channel MOS transistors M2 and M3 are turned off. As a result, the potential of node N _A is charged to power supply voltage V _CC , so that the base potential of bipolar transistor Q1 also rises, and the base-emitter potential rises to forward rising voltage V _F (about 0.7 V) of bipolar transistor Q1. Is exceeded, bipolar transistor Q1 conducts, and current flows from the collector to the emitter. At this time, since the transistor M3 is non-conductive, the load capacitance connected to the output terminal _Vout is charged. When the potential of the output terminal V _out is higher than V _CC -V _F, since the base-emitter voltage of the bipolar transistor Q1 is smaller than V _F, the bipolar transistor Q1 becomes non-conductive.

On the other hand, when the input terminal V _IN is at a high level (V _CC −
At V _F ), the P-channel MOS transistor M1 is turned off and the N-channel MOS transistors M2 and M3 are turned on, so that the potential of the node N _A becomes zero. As a result, bipolar transistor Q1 is turned off. However, at this time, since the transistor M3 is conducting, the load capacitance connected to the output terminal _Vout is discharged, and its potential becomes zero volt.

By the way, the above operation of the inverter circuit shown in FIG. 6 is based on the _{assumption that} the absolute value | V _TP | of the threshold voltage V _TP of the P-channel MOS transistor is
The case 1 is greater than the forward rise voltage V _F was assumed. Generally, when MOS transistors are miniaturized,
Since the withstand voltage is reduced, it is necessary to lower the drive power supply voltage. For example, if the gate length of the MOS transistor is 0.35
In μm, the driving power supply voltage is 3.3 V and the gate length is 0.25
2.5 V for μm, 1.5 V for gate length 0.15 μm
It is expected to be about V. Accordingly, it is necessary to lower the absolute value of the threshold voltage accordingly. MOS
Although the threshold voltage of the transistor can be easily adjusted by ion implantation, the forward threshold voltage V _F of the bipolar transistor is to be determined by the barrier of the PN junction, the adjustment is not easy. Therefore, in a BIMOS circuit using fine transistors, the MOS
This means that the absolute value of the threshold voltage of the transistor may be smaller than the forward rising voltage of the bipolar transistor.

In the inverter circuit shown in FIG.
V _TP | | absolute value of the threshold voltage of the S transistor M1 and the operation waveforms when less than the forward rise voltage V _F of the bipolar transistor Q1 shown in FIG. Here, the reason why the amplitude of the signal at the input terminal V _IN is V _CC -V _F is that it is assumed that a BIMOS inverter circuit having an output amplitude of V _CC -V _F is cascaded.

[0011] Now, consider the case where the input voltage V _IN is changed from zero V to V _CC -V _F. As mentioned above | V _TP | is V when _F is greater than the node N _A potential is zero from V _CC V
, And the potential of the output terminal V _out also changes from V _CC -V _F to zero V. However, | V _TP | and is V _F smaller, MOS transistors M when the potential of the input terminal V _IN is V _CC -V _F
1 does not become non-conductive. At this time, the MOS transistor M
2 is also conducting, a through current flows from the source of MOS transistor M1 (potential V _CC ) to the source of MOS transistor M2 (potential zero V). Further, the potential of the node N _A becomes higher than zero V due to the through current. The potential of the node N _A at this time is the level of V1 shown in FIG.
When the potential V1 is greater than V _F, the bipolar transistor Q1 is conductive. At this time, since the MOS transistor M3 is also conductive, the MOS transistor M3 is connected to the collector (potential V _CC ) of the bipolar transistor Q1.
3, a through current flows through the source (potential zero V), and the potential of the output terminal _Vout does not become zero V (period T in FIG. 7).
1).

[0012]

As described above, in the conventional BIMOS type inverter circuit, the P-channel M
If the absolute value of the threshold voltage of the OS transistor M1 is smaller than the forward rising voltage of the bipolar transistor Q1, reliability problems such as an increase in current consumption due to a through current and a malfunction of a circuit due to each node being at an intermediate potential will occur. is there. Further, if the absolute value of the threshold voltage of the P-channel MOS transistor M1 is increased to prevent such a problem from occurring, the driving capability of the MOS transistor is reduced, and the operating speed is reduced. .

The present invention has been made in view of the above circumstances, and a through current is generated even when the absolute value of the threshold voltage of a MOS transistor driving a bipolar transistor is smaller than the forward rising voltage of the bipolar transistor. BIMOS that can prevent as much as possible
It is intended to provide a circuit.

[0014]

SUMMARY OF THE INVENTION BIMOS according to the present invention
The circuit includes a first N-channel MOS transistor having a source connected to the input terminal and a gate connected to the drive power supply, a first N-channel MOS transistor having a source connected to the drive power supply, and a gate connected via the first node. A first P-channel MOS transistor connected to the drain of the MOS transistor; and a second P-channel MOS transistor having a source connected to the ground power supply and a drain connected to the drain of the first P-channel MOS transistor via the second node. An N-channel MOS transistor, an N-channel MOS transistor having a collector connected to the drive power supply, a base connected to the second node, and an emitter connected to the output terminal.
A third N-type bipolar transistor having a PN-type bipolar transistor, a source connected to the ground power supply, and a drain connected to the output terminal;
A channel MOS transistor, a source connected to the drive power supply, a gate connected to the output terminal, and a drain connected to the first
A second P-channel MOS transistor connected to the third node, the gate of the second N-channel MOS transistor is connected to either the input terminal or the first node, and the second N-channel MOS transistor The gate is connected to either the input terminal or the first node.

[0015]

According to the BIMOS circuit of the present invention configured as described above, the first PMOS driving the bipolar transistor can be used.
When a first N-channel MOS transistor serving as a transfer gate is provided between the gate of the channel MOS transistor and the input terminal and the potential of the input terminal becomes V _CC -V _F , that is, the output terminal becomes 0V The first node, ie, the first P-channel M
Second to make the gate of OS transistor _Vcc
Are provided. Thereby, even when the absolute value of the threshold voltage of the first P-channel MOS transistor is lower than the forward rising voltage of the bipolar transistor, the source of the second P-channel MOS transistor is switched from the source of the first P-channel MOS transistor. Can be prevented from flowing.

[0016]

FIG. 1 shows the configuration of a first embodiment of a BIMOS circuit according to the present invention. The BIMOS circuit of this embodiment is an inverter, and is different from the conventional inverter circuit shown in FIG. 6 in that an N-channel MOS transistor M4 and a P-channel MOS transistor M5 are newly provided. The source of N-channel MOS transistor M4 is connected to the input terminal V _IN, the gate is connected to a driving power source V _CC, the drain is connected to the gate of the P-channel MOS transistor M1 through the node N _B. The source of the P-channel MOS transistor M5 is connected to a driving power source V _CC, its gate connected to the output terminal V _out, a drain connected to the node N _B.

Next, the operation of the first embodiment will be described with reference to the operation waveforms shown in FIG. When the potential of the input terminal V _IN is low level (= 0 V), the MOS transistor M4
Is conducting, the potential at the node N _B becomes 0V equal to the potential of the input terminal V _IN (see time t1 in FIG. 2). As a result the MOS transistor M1 is conducting, the MOS transistor M2 becomes non-conductive, the potential of the node N _A driving power source potential V _CC becomes (see time t1 in FIG. 2), thereby the bipolar transistor Q1 is conductive. On the other hand, at this time, since the MOS transistor M3 is non-conductive, the output terminal V
The potential of _out is charged to V _CC -V _F (where V _F is the forward rising voltage of the bipolar transistor).
The gate of the MOS transistor M5 is connected to the output terminal V _out
If the absolute value of the threshold voltage of the transistor M5 is equal to or higher than V _F , the transistor M5
Becomes non-conductive.

Next, consider the case where the input terminal V _IN changes from a low level to a high level (= V _CC -V _F ). Now MO
The threshold voltage of the S transistor M4 to V _CC -V _TN when the potential at the node N _B When V _TN of V _TN ≧ V _F, V _TN
Become V _CC -V _F when ≦ V _F. In any case MOS
Since the transistor M2 is turned on, the potential of the node N _A drops, and the bipolar transistor Q1 is turned off.
On the other hand, since the MOS transistor M3 conducts, the output becomes 0V. Then the MOS transistor M5 is turned on, the potential of the node N _B becomes V _CC, MOS transistor M1 is rendered non-conductive (see time t2 in FIG. 2).

The above when the potential of the input terminal V _IN as described is V _CC -V _F, since the potential at the node N _B to be finally V _CC, MOS transistor M1 is an absolute value of the threshold voltage Is less than V _F , it remains non-conductive and M
No through current flows from the source of the OS transistor M1 to the source of the MOS transistor M2. Therefore, the potential of node N _A becomes 0 V, and bipolar transistor Q1
Does not flow from the collector of the MOS transistor M3 to the source of the MOS transistor M3. Further, since the absolute value of the threshold voltage of the MOS transistor M1 can be made smaller than the absolute value of the threshold voltage of the other MOS transistors, the driving capability can be increased, and high-speed operation can be performed. Can be.

Next, FIG. 3 shows the configuration of a second embodiment of the BIMOS circuit according to the present invention. In BIMOS circuit of the BIMOS circuit of embodiment the first embodiment shown in FIG. 1, which are connected to the node N _B, instead of connecting the gate of N-channel MOS transistor M2 to the input terminal V _IN. Since the second embodiment operates in the same manner as the first embodiment, it goes without saying that the second embodiment has the same effect as the first embodiment.

Next, the configuration of a third embodiment of the BIMOS circuit according to the present invention is shown in FIG. The BIMOS circuit of this embodiment is different from the BIMOS circuit of the first embodiment shown in FIG. 1 in that an N channel M for discharging the potential of the output terminal _Vout is used.
Which are connected to the node N _B, instead of connecting the gate of the OS transistor M3 to the input terminal V _IN. This third
This embodiment also performs the same operation as the first embodiment, so that it is needless to say that the same effect as in the first embodiment is obtained.

Next, the configuration of a fourth embodiment of the BIMOS circuit according to the present invention is shown in FIG. BIM of this fourth embodiment
OS circuit in BIMOS circuit of the second embodiment shown in FIG. 2, which are connected, instead of connecting the gate of N-channel MOS transistor M3 to the input terminal V _IN to the node N _B. Since the operation of the fourth embodiment is the same as that of the second embodiment, it goes without saying that the fourth embodiment has the same effect as that of the second embodiment.

[0023]

As described above, according to the present invention, even if the absolute value of the threshold voltage of the bipolar transistor is smaller than the forward rising voltage of the bipolar transistor, it is possible to minimize the occurrence of a through current. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of the circuit of the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional BIMOS circuit.

FIG. 7 is a waveform chart showing the operation of a conventional BIMOS circuit.

[Explanation of symbols]

M1 P-channel MOS transistor M2 N-channel MOS transistor M3 N-channel MOS transistor M4 N-channel MOS transistor M5 P-channel MOS transistor N _A node N _B Node VIN input terminal V _out output terminal Q1 bipolar transistor

Claims (1)

(57) [Claims] A first N-channel MOS transistor having a source connected to the input terminal and a gate connected to the drive power supply; a source connected to the drive power supply; and a gate connected via the first node to the first N-channel MOS transistor. A first P-channel MOS transistor connected to the drain of the N-channel MOS transistor, a source connected to the ground power supply, and a drain connected to the drain of the first P-channel MOS transistor via a second node Second N-channel MOS
A transistor, an NPN-type bipolar transistor having a collector connected to the driving power supply, a base connected to the second node, and an emitter connected to the output terminal; a source connected to the ground power supply; and a drain connected to the output terminal. And a second N-channel MOS transistor having a source connected to the drive power supply, a gate connected to the output terminal, and a drain connected to the first node.
A gate of the second N-channel MOS transistor is connected to either the input terminal or the first node, and a gate of the third N-channel MOS transistor is connected to the input terminal. A BIMOS circuit connected to one of a terminal and the first node.