JP2621248B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a CMOS integrated circuit device.
The present invention relates to a high-speed and low-power-consumption semiconductor integrated circuit device including a FET and a bipolar transistor.

[Conventional technology]

The biggest feature of CMOS devices is their low power consumption.Operating power consumption is only a small static power consumption due to the charge / discharge current of the load capacitance of the internal CMOS circuit, the through current flowing in the transition state, and the leakage current. is there.

As a logic circuit using CMOS, N-channel type MOS F
ET (NMOS / FET) load drive capability is P-channel type M
Since the NAND circuit operates at the highest speed because it is larger than that of OS-FET (hereinafter, PMOS-FET), the NAND gate is frequently used, but the basic gate is an inverter circuit.

A BiCMOS logic circuit combining a CMOS FET and a bipolar transistor is known as one that operates at a higher speed than an inverter circuit using only a CMOS EFT.
Japanese Patent Application Laid-Open No. 59-84 discloses this technology.
No. 31, JP-A-59-11034, or JP-A-60-1
No. 30216 and the like.

FIG. 2 is a configuration diagram illustrating an example of a conventional semiconductor integrated circuit including a CMOS FET and a bipolar transistor.

In the inverter circuit of FIG. 2, the PMOS FET 100 drives the NPN bipolar transistor 104, and the NMOS FET 102
Driving bipolar transistor 105 and these NPN
By driving the load connected to the output terminal 2 by the bipolar transistors 104 and 105, a high-speed and low-power-consumption device is realized. Here, NMOS ・ FET101,103
When the NPN bipolar transistors 104 and 105 are operated in a complementary manner, the base charge of the OFF-side NPN bipolar transistor is extracted and the NPN bipolar transistor 10
This is for suppressing a through current flowing through 4,105. Therefore, these NMOS FETs 101 and 103 are indispensable components for the high speed and low power consumption operation of the circuit of FIG.

[Problems to be solved by the invention]

By the way, in recent years, the performance of these devices has been improved due to miniaturization, that is, scaling, of devices such as CMOS FETs and bipolar transistors. As a result, the performance of devices including MOS FETs and bipolar transistors, especially speed, has been reduced. It is improving accordingly.

However, with the miniaturization of elements, MOS / FETs have a device withstand voltage of 5 V or less, which is the power supply voltage of a conventional LSI, due to so-called hot carrier injection and development. It is necessary to increase the breakdown voltage of the circuit so that only a voltage lower than the breakdown voltage is applied to the element.

In the circuit shown in FIG. 2, the power supply voltage Vcc is applied between the source and drain of the PMOS / FET 100 and the NMOS / FET 101, and the NMOS / FET 10
A high level voltage of the output terminal 2 (for example, a power supply voltage of 5 V, 4.6 V at the time) is applied between the source and the drain of 2,103.

Also, if the NPN bipolar transistor 105 is driven by the NMOS / FET 102, the source voltage of the NMOS / FET 102 rises above the ground (GND) potential by the forward voltage V _BE between the base and emitter of the NPN bipolar transistor. When the voltage and low-amplitude operation is performed, there is a problem that the output falling operation speed is reduced and the power supply voltage cannot be reduced much.

The purpose of the present invention is to solve these conventional problems and to provide a CMOS
In a logic circuit consisting of a FET and a bipolar transistor, a semiconductor integrated circuit device capable of reducing the voltage applied between the source and drain of the MOS / FET to achieve a high breakdown voltage of the circuit and operating at high speed with a low power supply voltage Is to provide.

[Means for solving the problem]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention (1) controls the flow of base current of bipolar transistors 166 and 170 by opening and closing between a drain and a source based on an input signal to a gate.
P-channel or N-channel driving MOS-FETs 163 and 168 for controlling on / off of 166 and 170
Bipolar transistor 166,170 by OS ・ FET163,168
When the state changes from on to off, the through current suppressing means (MOS-FETs 164 and 169) for extracting the charge of the bases of the bipolar transistors 166 and 170, and the bipolar transistor 16
When the MOS transistor 6,170 is turned off, a forward bias voltage V _O which does not reach the operating point of the bipolar transistor 166,170 is applied to the base of the bipolar transistor 166,170 via the through current suppressing means (MOS FET 164,169), and the driving MOS transistor turned off.・ F
The ET 163, 168 is characterized by having at least bias means (on-chip voltage generation circuit 202) for reducing the voltage between the drain and the source.

(2) In the semiconductor integrated circuit device according to the above (1), the through current suppressing means may be a driving MOS-FET 163,16.
8 turns on when the bipolar transistors 166 and 170 change from the on state to the off state.
It consists of N-channel type MOS-FETs 164 and 169 for extracting the base charge of 6,170 to the source side, which suppresses the forward bias voltage V _O from the bias means.
It is characterized in that it is added to the sources of the MOS FETs 164 and 169.

(3) In the semiconductor integrated circuit device according to (2), if the driving MOS-FET is a P-channel type,
It is characterized in that the absolute value of the threshold voltage of the channel type through-current control MOS-FETs 107, 109, 164 is lower than the absolute value of the threshold voltage of the driving MOS-FETs 106, 163.

(4) In the semiconductor integrated circuit device described in the above (2), if the driving MOS-FET is an N-channel type, the absolute value of the threshold voltage of the driving MOS-FET 108 is determined by the N-channel type It is characterized in that the threshold voltage of the current-suppressing MOS FETs 107 and 109 is lower than the absolute value of the threshold voltage.

(5) In the semiconductor integrated circuit device according to any one of (2) to (4), the bias means connects the sources of the through-current suppressing MOS FETs 164 and 169 to a predetermined positive voltage power supply V _O. Then, a forward bias voltage V _O of the bipolar transistors 166 and 170 is applied.

(6) In the semiconductor integrated circuit device according to any one of the above (2) to (4), the biasing means includes a semiconductor element connected between the source of the through-current control MOS FETs 164 and 169 and the ground. Schottky barrier diode 137,
138).

(7) In the semiconductor integrated circuit device according to any one of the above (2) to (4), the bias means includes a base for the bipolar transistors 166 and 170 and a through current suppressing M.
It is characterized by comprising a semiconductor element (Schottky barrier diodes 159, 160) connected between the drains of the OS-FETs 164, 169.

(8) In the semiconductor integrated circuit device according to any one of the above (1) to (7), the bias means includes at least a Schottky barrier diode 137, 138, 154, 159,
160 is provided.

(9) In the semiconductor integrated circuit device according to any one of the above (2) to (8), the NPN-type bipolar transistor 110, the P-channel type driving MOS-FET 106, the through current suppressing MOS-FET 107, And bias means (V _O )
And the collector of the bipolar transistor 110 is P
The source of the channel type driving MOS-FET 106 is connected,
The drain of the P-channel type driving MOS-FET 106 and the MOS for suppressing the through current at the base of the bipolar transistor 110
A first semiconductor integrated circuit to which the drain of the FET 107 is connected, an NPN-type bipolar transistor 111, an N-channel type driving MOS-FET 108, a through-current suppressing MOS-FET 109, and bias means (V _O ) N-channel type driving MOS-FET 108 at the collector of bipolar transistor 111
And a second semiconductor integrated circuit in which the base of the bipolar transistor 111 is connected to the source of the N-channel type driving MOS-FET 108 and the drain of the through-current suppressing MOS-FET 109. The emitter of the bipolar transistor 110 of the first semiconductor integrated circuit and the output terminal 5 are connected to the collector of the bipolar transistor 111 of the semiconductor integrated circuit, and the output terminal 5 or
One of the bases of the bipolar transistor 110 of the first semiconductor integrated circuit is connected to the gate of the through-current suppressing MOS-FET 109 of the second semiconductor integrated circuit, and the P-channel driving of the first semiconductor integrated circuit is performed. The gate of the MOS-FET 106 and the gate of the MOS-FET 107 for through current suppression, and
N-channel type driving MOS-FET of the second semiconductor integrated circuit
The gate of 108 is connected to input terminal 4 and this input terminal 4
And outputs the NOT logical operation result of the signal to the output terminal 5.

(10) In the semiconductor integrated circuit device according to the above (9), the forward bias voltage (V _O ) by the biasing means of the first semiconductor integrated circuit is changed to the emitter of the bipolar transistor 110 of the first semiconductor integrated circuit. It is characterized in that it is equal to the sum of the allowable value of the current in a steady state and the low level value of the output terminal 5.

(11) In the semiconductor integrated circuit device described in the above (9), the bias means connects the source of the through-current suppressing MOS FET 107 (119) of the first semiconductor integrated circuit to the source of the second semiconductor integrated circuit. It is characterized in that it is connected to the base of the bipolar transistor 111 (124).

(12) In the semiconductor integrated circuit device according to the above (9), the biasing means may include the semiconductor element 1 between the source of the through-current suppressing MOS-FET 107 of the first semiconductor circuit and the ground.
Two MOS transistors are provided for suppressing through current in the second semiconductor circuit.
-The feature is that the source of the FET 136 is connected to the middle of the two semiconductor elements 137.

(13) In the semiconductor integrated circuit device described in the above (9), the base of the bipolar transistor 110 (116) of the first semiconductor integrated circuit and the driving MOS FET 108 (113) of the second semiconductor integrated circuit are connected. It is characterized in that it is connected to the domain by an impedance element 114, and the through current suppressing MOS-FET 107 and bias means (V _O ) of the first semiconductor integrated circuit are not required.

(14) In the semiconductor integrated circuit device described in the above (13), the driving MOS-FET 108 of the second semiconductor integrated circuit is provided.
It is characterized in that the source of (113) and the bias means (V _O ) are connected by an impedance element 115, and the through-current suppressing MOS-FET 109 of the second semiconductor integrated circuit is not required.

(15) In the semiconductor integrated circuit device according to any one of the above (13) and (14), a path between the drain of the driving MOSFET 113 of the second semiconductor integrated circuit and the collector of the bipolar transistor 117 is established. , Connected by a diode whose forward direction is from the collector to the first direction.
A short circuit is made between the base of the bipolar transistor 116 of the semiconductor integrated circuit and the domain of the driving MOSFET 112 of the second semiconductor integrated circuit and the domain of the driving MOSFET 113 of the second semiconductor integrated circuit. 11
4 is unnecessary.

(16) In the semiconductor integrated circuit device according to any one of (9) to (15), the absolute value of the threshold voltage Vt of the N-channel type driving MOS-FET 108 of the second semiconductor integrated circuit is defined as Other MOS FETs (106,107,109,112,113,118-121,1
25 to 128, 130, 133 to 136, 141 to 148, 156 to 158).

(17) In the semiconductor integrated circuit device according to any one of (9) to (15), an N-channel MOS transistor including at least an N-channel driving MOS FET 108 of the second semiconductor integrated circuit. FET (107,109,113,119,120,121,12
The absolute value of the threshold voltage Vt of 6 to 128, 130, 134 to 136, 142 to 144, 146 to 148, 156 to 158) is set to the P-channel type driving MOS-FET (106, 112, 118, 125, 133, 141, 14) of the first semiconductor integrated circuit.
It is characterized in that it is lower than the absolute value of the threshold voltage of 5).

[Action]

In the present invention, the circuit shown in FIG.
By making the source potential of T101 or NMOS / FET103 higher than the ground potential and lowering the threshold voltage of NMOS / FET102 below the threshold voltage of conventional circuits, it enables low power supply voltage operation and enables high-speed operation. To That is, first, in the conventional circuit shown in FIG. 2, the source potential of the NMOS FET 101 and / or 103 is set to + V.
By increasing the voltage by ₀ (V), PMOS / FET100 and NMOS
・ The voltage applied to the source and drain of FET101,103 is V
₀ (V), and compared with the conventional circuit, V
₀ (V) High breakdown voltage. Also, by setting the source potential of the NMOS-FET 103 to + V ₀ (V), the NMOS-FET 103
Are conducting and 102 is non-conducting, the source potential of the NMOS • FET 103 is increased by V ₀ (V) as compared with the conventional ground potential. As a result, even if the threshold voltage V _T of the NMOS FET 102 is set lower than V ₀ (V) as compared with the conventional circuit, the sub-threshold current of the NMOS FET 102 does not increase, and V Operation at a low power supply voltage by ₀ (V) becomes possible.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing one embodiment of the present invention.

In the inverter circuit shown in FIG.
S-FET 107-109, and NPN bipolar transistor 110,
111 is the PMOS FET 100, NMOS FET 101 to
The operation is the same as that of the 103 and the NPN bipolar transistors 104 and 105, and the detailed description is omitted. Although the gate of the NMOS FET 109 is connected to the output terminal 5 in FIG. 1, it is needless to say that the gate may be connected to the base of the NPN bipolar transistor 110.

In FIG. 1, terminal 4 is a signal input terminal, terminal 5 is a signal output terminal, and terminal 6 is a terminal for applying a positive power supply voltage (V _CC ). The feature of this circuit is that a voltage of + V ₀ (V) higher than the ground potential is applied to the source terminals of the NMOS FETs 107 and 109, as is apparent from comparison with the circuit of FIG.

Now, the voltage input to the signal input terminal 4 is low level V _IL
(V), the PMOS / FET 106 is conductive, and the NMOS / FE
T107,108 are non-conductive, NPN bipolar transistors 110,111
Become conductive and nonconductive, respectively, so that the output terminal 5
Becomes high level V _OH (V), and the NMOS FET 109 becomes conductive. Therefore, the base potential of the NPN bipolar transistor 110 is the power supply potential V _CC , the base potential of the NPN bipolar transistor 111 is + V ₀ , and the NMOS FETs 107 and 1
The voltage between the source and the drain 08 is lower than the circuit of FIG. 2 by + V ₀ (V), that is, V _CC −V ₀ , V _OH −V
Only a voltage of ₀ is applied.

Next, when the input voltage is at a high level V _IH (V), the PMO
S · FET 106 is non-conductive, NMOS · FET107,108 is conductive, NPN bipolar transistors 110 and 111 nonconductive, respectively, so a conducting, the output voltage is low V _OL becomes, NMOS · FET 10
9 is non-conductive. Therefore, NPN bipolar transistor
110 has a base potential of + V ₀ , NPN bipolar transistor 11
1 of the base potential V _OL next, PMOS · FET106 and NMOS ·
Between the source and drain of FET109, it is V _CC -V _0, V _OL
Are merely applied.

As a result, the circuit of FIG. 1 can have a higher withstand voltage by + V ₀ (V) than the circuit of FIG.
The allowable upper limit of + V ₀ depends on the steady state allowable value of the emitter current flowing through the NPN bipolar transistor. For example, in the case of the NPN bipolar transistor 111, in the experiment, a current of about 2 nA flows at V _RE = V ₀ = 0.5 V. If this value is the maximum steady-state current allowable as a circuit inside the LSI, it is possible to increase the V ₀ to V ₀ = 0.5V.

In the circuit of FIG. 1, the source of the NMOS FET 107 is also
Although the same + V ₀ (V) voltage as that of the source of the NMOS FET 109 is applied, the above voltages are not necessarily the same. In the case of NPN bipolar transistor 110, V ₀ = V
V ₀ can be set large up to _OL + V _BE .

In FIG. 1 or FIG. 2, the value of _VOL of the circuit is the value described below. That is, when the output voltage changes from the high level to the low level, the base charge is injected into the NPN bipolar transistor 111 by the NMOS FET 108,
A collector current corresponding to this charge flows, and the output potential quickly goes to a low level. The injection of the base charge, to the source-drain voltage of the NMOS-FET 108 is zero, that is, the output voltage is continued until the V _BE. At this time, since the base charge remains in the base, the collector current continues to flow in accordance with the amount of the base charge, and as a result, the output potential continues to decrease beyond V _BE . At the same time as the output potential drops beyond V _BE ,
Since 108 operates in a direction opposite to the normal direction, the base charge is extracted by the NMOS FET 108, and when the base charge becomes zero, the collector current stops flowing and the output potential becomes the level _VOL at the output potential. In experiments, this voltage was about 0.4V. Normally, the _VOL is the value of _VBE determined by the leakage current of the circuit system shown in FIG. Target LSI now
Internally, the low level potential V _OL of the circuit of FIG.
, The V _{BE of} NPN bipolar transistor 110
Is set to, for example, 0.4 V, and the source voltage V ₀ of the NMOS FET 107 is
V ₀ = V _OL + V _BE = 0.8V can be set. Also, for example, the steady-state current flowing through the NPN bipolar transistor is 2
If up to nA can be tolerated and this allows V _OL = 0.5V, then V ₀ is replaced by V ₀ = V _OL + V _BE = 0.5. +
0.5 = 1.0V can be set.

As described above, when the voltages applied between the source and drain of the NMOS FETs 107 and 108 are V _CC −V ₀ and V _IH −V ₀ , respectively, the voltage applied between the source and drain is made the same, and the circuit is implemented. From the viewpoint of uniformly increasing the breakdown voltage, V _CC −V _IH =
At 0.4 V, the source potential of the NMOS FET 107 is set to V ₀ ≧ 0.9
V, It is desirable to set the source potential of the NMOS FET 109 to V ₀ = 0.5.

Thus, in the circuit of FIG.
By setting the source potential of 7,109 to a potential higher than the ground potential, it is possible to increase the breakdown voltage of the circuit as compared with the conventional circuit shown in FIG. Further, the circuit of FIG. 1 has an advantage that it operates at a higher speed than the circuit of FIG.

Next, the high-speed operation of the circuit of FIG. 1 will be described in detail.
The delay time of the circuit shown in FIG.
・ FET108 is NPN bipolar transistor 110,111 respectively
And the delay time until the NPN bipolar transistor 110 or 111 drives the load of the next stage connected to the output terminal 5 is given. As will be described later, the circuit of FIG. 1 operates at a higher speed than the circuit of FIG. 2 because the former one of the delay times is smaller.

That is, in the circuit of FIG. 2, the base-emitter voltage V _BE of the NPN bipolar transistor 104 or 105 is zero in the non-conductive state, the input voltage is switched, and the MOSFET drives the NPN bipolar transistor. In this case, it is necessary to drive V _BE from zero to, for example, 1.0 V. In contrast, in the circuit of FIG. 1, V ₀ = 0.
Assuming 5V, NPN bipolar transistor 110 or 11
The base-emitter voltage V _{BE of 1} is 0 when not conducting.
Since it is 5V, the MOSFET needs only to drive the NPN bipolar transistor from 0.5V to 1.0V. Therefore, the first
The circuit shown in the figure has the advantages that it has a higher breakdown voltage and operates at a higher speed than the conventional circuit shown in FIG. In experiments, the circuit of FIG. 1 was about 10 times less than the circuit of FIG.
% Was faster.

Next, in the circuit of FIG. 1, the threshold voltage V _T of the NMOS FET is
By setting it lower than the NMOS FET of the circuit of FIG. 2, the circuit operates at a higher speed than the circuit of FIG. 2 and operates at a lower power supply voltage. Hereinafter, an example in which set low threshold voltage V _T of NMOS · FET, is described in detail.

FIG. 3 is a characteristic diagram showing an example of a sub-threshold characteristic of an NMOS FET.

A straight line A shown in FIG. 3 indicates a sub-threshold characteristic of the NMOS FET in the CMOS circuit. In FIG. 3, the gate-source voltage V _GS when the drain current is 1 is shown.
When a is defined as the threshold voltage V _T, first consider a CMOS circuit, CMOS
Drain current 1 when input low level voltage V _IL = OV of the circuit
If 0 ^-6 is acceptable, the threshold voltage of the NMOS / FET in this case
The V _T can be set to 0.6V.

The straight line B is the NMOS / FE of the conventional BiCMOS circuit shown in FIG.
9 shows a sub-threshold characteristic of T. In the conventional circuit, when the former stage is the same circuit as FIG. 1 and V _IL = 0.4 V, in order to make the drain current at this time 10 ₋₆ , as shown by a straight line B in FIG. , the threshold voltage V _T 0.6 + 0.4
= 1.0V must be set.

The straight line C represents the NMOS • of the BiCMOS circuit of the present invention shown in FIG.
This shows the sub-threshold characteristics of FET. In the circuit of the present invention, as shown in FIG. 1, since the source potential of the NMOS-FET is set to V ₀ = 0.5, even when V _IL = 0.4 V, the gate-source of the NMOS-FET is The inter-voltage V _GS = −0.1V. Therefore, when V _GS = −0.1 V, the drain current is 10 ^−6.
In order to make the threshold voltage V _T = 1.0 as shown by the straight line C,
-0.5 = 0.5V can be set.

The input voltage V in the circuits shown in FIGS.
For _IL = 0V, the threshold voltage V _T of the straight line of FIG. 3 for B to 0.6V the same value as the straight line A, to the straight line V _T of C to 0.1 V, and the other input voltage V _IL Of course, the same applies to the case.

As described above, in the circuit of the present invention, as shown in FIG. 1, the source potentials of the NMOS FETs 107 and 109 are set higher than the ground potential. it has become possible to set a low threshold voltage V _T. By setting the threshold voltage low, the current for driving the NPN bipolar transistor increases,
High-speed circuit operation has become possible.

In the embodiment, carried out with respect to all the NMOS · FET107~109, is performed a low voltage of the threshold voltage V _T, only the NMOS · FET 108 that require a part, in particular drivability Of course, it does not matter.

Next, in the circuit of the present invention, since the operating power supply voltage range is widened by lowering the threshold voltage as described above, lower voltage operation is possible as compared with the conventional circuit. This will be described in detail below.

FIG. 4 is a comparison diagram of the power supply voltage dependence of the delay time in the circuit of the present invention shown in FIG. 1 and the conventional circuit shown in FIG. B and C in FIG. 4 respectively correspond to the straight lines B and C of the sub-threshold characteristic in FIG. In FIG. 4, t _PLH and t _PLH are delay times of the rise and _fall of the output, respectively.

As is apparent from FIG. 4, the delay time of the output rise
Since _tPLH is the same curve for both B and C, and the slope of the curve is small, the dependency of the power supply voltage is small. On the other hand, the delay time t _PHL of the _fall of the output is a curve in which B and C are different from each other, and both rise sharply from a power supply voltage having a slope. The reason for this rapid increase is based on the following reasons.

That is, as shown in FIG.
The drive of the load that determines the _PLH is determined by the PMOS FET 100 and the NPN bipolar transistor 104.
The source of 100 is the V _CC potential and the input voltage low level V _IL −V
The voltage of _CC is applied between the gate and source. On the contrary,
The drive of the load that determines the _fall delay time t _PHL is NMOS / FE
Determined by T102, NPN bipolar transistor 105,
Since the source potential of the NMOS FET 102 is V _BE during driving, only the input voltage high level V _IH −V _BE is applied between the gate and the source. In other words, since the source potential of the NMOS FET 102 is not the ground potential but is floating only by the potential of V _BE , the voltage applied between the gate and the source is smaller by V _BE .
Therefore, the _fall delay time t _PHL of the NMOS / FET drive can operate only up to a voltage higher by V _BE than the rise delay time t _PLH .

The lower limit of the power supply voltage at which the _fall delay time t _PHL can operate is:
It is determined by the value of V _BE + V _T. Therefore, by lowering the threshold voltage V _T of NMOS · FET by the circuit of the present invention shown in FIG. 1, as shown in FIG. 4, by the amount of lowering the V _T (in FIG. 4, 0.5V) operation The power supply voltage can be extended.

FIG. 5 is a diagram showing the configuration of a semiconductor integrated circuit device according to another embodiment of the present invention.
1 shows the connection of an inverter circuit composed of transistors.

In the circuit of FIG. 5, the PMOS FET 112 and the NMOS FET 11
3. Since the NPN bipolar transistors 116 and 117 perform the same operations as the PMOS / FET 106, NMOS / FET 108 and NPN bipolar transistors 110 and 111 in FIG. Terminal 36 is a signal input terminal,
Terminal 37 is the signal output terminal, and terminal 38 is the positive power supply voltage (V _CC )
The terminal 39 has + V ₀ as in FIG.
By applying the positive voltage (V), the same effect as in FIG. 1 can be expected.

The elements 114 and 115 are resistors or impedance elements such as MOS-FETs, and all conventionally known combinations can be used. For example, the impedance element 114 is a resistance element, the element 115 has a gate as an output terminal 37, and a drain as an NMOS / FE.
It is possible to obtain V _OH = V _CC by using the source and the source of T113 as an NMOS FET connected to the terminal 39 of the positive voltage + V ₀ . Also, without connecting the drain terminal of the NMOS FET 113 to the output terminal, insert a diode between the drain terminal and the output terminal, and short-circuit the location of the impedance element 114, so that the drain terminals of the PMOS FET 112 and the NMOS FET 113 Can be connected.

FIG. 6 is a block diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention, and shows an inverter circuit having another connection.

In FIG. 6, PMOS FET 118, NMOS FETs 120 and 121,
The NPN bipolar transistors 123 and 124 perform the same operations as the PMOS FET 106, the NMOS FETs 108 and 109, and the NPN bipolar transistors 110 and 111 in FIG. In FIG. 6, terminal 10 is a signal input terminal, terminal 11 is a signal output terminal, terminal 12 is a terminal for applying a positive power supply voltage (V _CC ), and terminal 13 is a terminal.
By applying a positive voltage of + V ₀ (V) as in FIG. 1, the same effect as in FIG. 1 can be expected.

FIG. 6 differs from the circuit of FIG. 1 in that the source terminal of the NMOS FET 119 is not connected to a positive voltage but is connected to the base terminal of the NPN bipolar transistor 124. In this way, during output fall operation, NM
Since the through current flowing through the OS • FET 119 flows to the base of the NPN bipolar transistor 124, the operation speed can be increased. Since the source potential of the NMOS FET 119 is + V ₀ (V) when the NMOS FET 119 is off, the NMOS FETs 107 and 1 in FIG.
This is exactly the same as the case where the same source voltage + V ₀ is added to 09.

In the conventional circuit, the source of the NMOS
The method of connecting the base of the NPN bipolar transistor 124 is a well-known technique (for example, a method described in the literature "IEEE Transaction On Electron Devices").
VICES VOL.ED-16, NO.11, PP945-951 1969 Fig.10).

FIG. 7 is a configuration diagram of a semiconductor integrated circuit device according to still another embodiment of the present invention, showing connections of inverter circuits.

In FIG. 7, PMOS FET 125, NMOS FET 126 to 12
8. The NPN bipolar transistors 131 and 132 perform the same operations as the PMOS FET 106, the NMOS FETs 107 to 109, and the NPN bipolar transistors 110 and 111 in FIG. Also, the terminal in FIG.
14 is a signal input terminal, terminal 15 is a signal output terminal, terminals 16, 17
Is a positive power supply voltage (V _CC ) application terminal. By applying a positive voltage of + V ₀ (V) to the terminals 18 and 19 as in FIG. 1, the same effect as in FIG. 1 can be expected. .

In FIG. 7, the first point is that a CMOS circuit (inverter circuit) having the same logic function is connected in parallel with an inverter circuit composed of a MOS FET and a bipolar transistor.
It is different from the figure. That is, the PMOS FET 129 of FIG.
The NMOS FET 130 forms the inverter circuit.
By adding this CMOS circuit, V _OL = OV, V _OH , V _CC
An output signal having a power supply voltage amplitude can be obtained in the range of.
Therefore, in this case, if the preceding stage is a circuit of the same type as that of FIG. 7, V _IL = 0 V, so that the threshold value is further increased as compared with the case of V _IL = 0.4 V described in FIG. it will be possible to reduce the voltage of the voltage V _T. Further, a two-stage CMOS inverter circuit using the output signal of the terminal 15 as an input signal may be configured, and the output signal may be connected to the terminal 15 so that V _OL = 0 V and V _OH = V _CC. .

FIG. 8 shows a configuration of a semiconductor integrated circuit device according to still another embodiment of the present invention, showing a connection of an inverter circuit.

In FIG. 8, PMOS FET 133, NMOS FETs 134 to 13
6. Since the NPN bipolar transistors 139 and 140 perform the same operations as the PMOS FET 106, NMOS FETs 107 to 109 and NPN bipolar transistors 110 and 111 in FIG. 1, the description of the operation is omitted.

In FIG. 8, terminal 20 is a signal input terminal, terminal 21 is a signal output terminal, and terminal 42 is a terminal for applying a positive power supply voltage (V _CC ). In this embodiment, the source bias voltage + V ₀ of the circuit of FIG.
That it is applied by using the forward bias voltage V _F of abbreviated as SBD) 137, 138 are different. This makes it possible to obtain easily the bias voltage + V _F within basic gates in LSI, it is not necessary to wired power supply wiring for the bias voltage. Depending on the value of the SBD of V _F, may be of course connected to SBD series a plurality. In addition, SBD137 and 138 are shared, and NMOS
The configuration may be such that the sources of 134 and 136 are connected to the anode of one SBD.

Further, as described with reference to FIG.
Source potential of + 2V _F , source potential of NMOS ・ FET136 + V
_In order to obtain _F , two SBDs may be inserted between the source of the NMOS FET 134 and the ground, and the source terminal of the NMOS FET 136 may be connected to an intermediate terminal.

FIG. 9 is a block diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention. The circuit comprises a plurality of MOS-FETs and bipolar transistors, and the source bias shown in FIG. It shows a circuit to supply.

That is, in FIG. 9, a plurality of inverter circuits 200,
When the arrays 201 are arranged, an on-chip voltage generating circuit 202 for supplying a source bias voltage to them is connected. SBD of on-chip voltage generation circuit 202
154 is a source bias supply diode shared by circuits such as 200 and 201. Signal input terminal 22, signal output terminal 24,
Positive power supply voltage terminal 26, PMOS FET141, NMOS FET142 to 14
4.Inverter circuit 200 composed of NPN bipolar transistors 149 and 150, and signal input terminal 23, signal output terminal 25, positive power supply voltage terminal 27, PMOS / FET 145, NMOS /
The operation of the inverter circuit 201 including the FETs 146 to 148 and the NPN bipolar transistors 151 and 152 is the same as the operation of the inverter circuit shown in FIG.

In the circuit of FIG. 9, the point that the source bias voltage is supplied from the circuit 202 to the plurality of circuits 200 and 201 in common is the eighth circuit.
It is different from the circuit in the figure. Source bias voltage circuit 202
, Like the circuit of Figure 8, is constituted by SBD154, it supplies a source biased by the forward bias voltage V _F. As a method of supplying the source bias voltage by the SBD, it is needless to say that the configuration described in FIG. 8 can be used as it is, such as connecting a plurality of SBDs in series. Current source 15
Reference numeral 3 is for supplying a bias current to the SBD 154, and this may be omitted. In this way, by arranging the source bias voltage source 202 in common between adjacent basic gates, the number of SBDs used can be reduced without increasing the wiring area of the power supply wiring for the bias voltage, It is possible to reduce the area occupied by the SBD.

FIG. 10 is a block diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention, and shows a modification of FIG.

In FIG. 10, SBDs 137 and 138 in FIG.
The difference is that the SBDs 159 and 160 are inserted between the drains of the NMOS FETs 156 and 158 and the bases of the NPN bipolar transistors 161 and 162, respectively, while being inserted between the source of the OS • FETs 134 and 136 and the ground. . In the FIG. 10, the source-drain voltage of the NMOS-FET156,158 that lowered by V _F by V _F of the SBD, in the FIG. 8, the gate-source V _GS
It has become the only down configuration V _F also. Therefore, pull-out NMOS
・ For the driving capability of the FET, the NMOS
Are larger than the NMOS FETs 134 and 136 in FIG. However, the gate-source voltage V _GS of the NMOS FETs 156 and 158 is
Since no decrease similarly by insertion of the SBD and the conventional circuit of FIG. 2, it is impossible to lower the voltage the threshold voltage V _T of NMOS · FET156,158. Of course, the effect of the SBD for NMOS · FET157, PMOS · FET155 is identical to the circuit both in Fig. 8 and Fig. 10, the voltage applied between the source and the drain of the NMOS · FET157, PMOS · FET155 is reduced by V _F Te, along with attained a high withstand voltage of the circuit, it is possible to lower the threshold voltage V _T of NMOS · FET157 only V _F. In the circuit of FIG. 10, the NMOS FETs 156, 1
The SBDs 159 and 160 can be formed compactly using the 58 drain diffusion layers.

FIG. 11 is a block diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention, and is a connection diagram of a BiCMOS circuit composed of a CMOS circuit and one bipolar transistor.

In the circuit of FIG. 11, the PMOS FET 163 and the NMOS FET 16
4. Since the NPN bipolar transistor 166 operates in the same manner as the PMOS / FET 106, NMOS / FET 107, and NPN bipolar transistor 110 in the circuit of FIG. 1, the description of the operation is omitted. In FIG. 11, terminal 50 is a signal input terminal, terminal 51 is a signal output terminal, and terminal 52 is a positive power supply voltage (V
_CC ), and +53 is applied to terminal 53 as in Fig. 1.
By applying a positive voltage of ₀ (V), the same effect as in FIG. 1 can be expected.

11 is different from the circuit of FIG. 1 in that the load is driven by an NMOS FET 165 instead of the NPN bipolar transistor 111. As described with reference to FIG. 1, the delay time of the circuit of FIG.
NMOS and FET108 are NPN bipolar transistors 11 respectively
It is given by the sum of the delay time before driving 0,111 and the delay time for driving the next stage load connected to the output terminal by the NPN bipolar transistor 110 or 111. On the other hand, in the circuit of FIG. 11, when the load is driven by the NMOS FET 165, there is no delay time of the former. Therefore, when the load is light, the circuit of FIG. 11 operates faster than the circuit of FIG. Also, as described in FIG.
Since the source potential of OS • FET164 is + V ₀ , PMOS • FET1
The delay time when the 63 drives the NPN bipolar transistor 166 is reduced. As a result, the circuit of FIG. 11 can drive a light load at a high speed.

FIG. 12 is a configuration diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention, and there is a modification of FIG.

In FIG. 12, the NMOS FETs 168 and 169 and the NPN bipolar transistor 170 correspond to the NMOS F
Since the same operations as those of the ETs 108 and 109 and the NPN bipolar transistor 111 are performed, the description of the operations is omitted. In FIG. 12, terminal 60 is a signal input terminal, terminal 61 is a signal output terminal, terminal 62 is a positive power supply voltage application terminal, and terminal 63 has a positive voltage of + V ₀ (V) as in FIG. The same effect can be expected by applying. In FIG. 12, compared to the circuit of FIG. 1, a PMOS is used instead of the NPN bipolar transistor 110.
-The difference is that the load is driven by the FET167.
The delay time for driving the load is exactly the same as in the case of FIG. 11, and the circuit of FIG. 12 operates faster when the load is lighter than the circuit of FIG.

In the embodiment, an inverter circuit is shown as an example of a circuit including a MOS FET and a bipolar transistor. However, a multi-input NAND circuit and a multi-input
The present invention can be applied to a NOR circuit and the like.
There is an effect of speeding up.

As described above, in each embodiment of the present invention, the voltage applied between the source and the drain of the MOS / FET constituting the BiCMOS circuit is reduced, and the speed is improved without deteriorating the speed performance of the circuit. At the same time, the withstand voltage of the circuit can be increased. In addition, the threshold voltage V _T of the MOSFET that constitutes the BiCMOS circuit
Can be set lower than before, so that speed performance can be improved and low power supply voltage operation is possible.

〔The invention's effect〕

As described above, according to the present invention, in a BiCMOS circuit including a MOS FET and a bipolar transistor, a voltage applied between the source and the drain of the MOS FET is reduced, so that a high breakdown voltage of the circuit is achieved. In addition, since the threshold voltage of the MOS-FET is lowered, the operation at a low power supply voltage becomes possible, and the high-speed operation becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing one embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional inverter circuit, and FIG.
FIG. 4 is a characteristic diagram showing the reduction of the threshold voltage of the NMOS / FET in the circuit of FIG. 1, FIG. 4 is a characteristic diagram of the output signal fall / rise delay time of the circuit of FIG. 1, and FIG. FIG. 6 is a block diagram of an inverter circuit showing another embodiment of the present invention, FIG. 6 is a block diagram of an inverter circuit showing still another embodiment of the present invention, and FIGS.
FIG. 13 is a configuration diagram of an inverter circuit showing still another embodiment of the present invention. 1,4,10,14,20,22,23,29,36,50,60: Signal input terminal, 2,5,11,15,21,24,25,30,37,51,61: Signal output Terminal, 3,6,12,16,17,42,26,27,28,31,38,52,62: Positive power supply voltage application terminal, 7,8,13,18,19,39,53,63 : Positive bias voltage application terminal, 100, 106, 112, 118, 125, 129, 133, 141, 145, 155, 163, 167: P
Channel MOS / FET, 101-103,107-109,113,119-121,126-128,130,134-1
36,142 to 144,146 to 148,156 to 158,164,165,168,169: N-channel type MOSFETs, 104,105,110,111,116,117,123,124,131,132,139,140,14
9 to 152,161,162,166,170: NPN bipolar transistor, 114,115: impedance element, 137,138,154,159,160: Schottky barrier diode (SBD), 153: current source.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toshiaki Masuhara 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-130216 (JP, A) JP-A-61 -198817 (JP, A)

Claims (17)

(57) [Claims] 1. A P-channel or N-channel drive MOS for controlling the flow of a base current of a bipolar transistor by opening and closing a drain and a source based on an input signal to a gate, and performing on / off control of the bipolar transistor. An FET; a through-current suppressing means for extracting a charge of the base of the bipolar transistor when the state of the bipolar transistor is changed from on to off by the driving MOS FET; and when the bipolar transistor is off, Through the through current suppressing means on the base,
A semiconductor integrated circuit device, comprising: at least bias means for applying a forward bias voltage that does not reach the operating point of the bipolar transistor to reduce the voltage between the drain and the source of the driving MOSFET that has been turned off. 2. The semiconductor integrated circuit device according to claim 1, wherein said through current suppressing means is turned on when said bipolar transistor is changed from on to off by said driving MOSFET. , To extract the electric charge at the base of the bipolar transistor to the source side.
A semiconductor integrated circuit device comprising a channel-type through-current suppressing MOS-FET, wherein a forward bias voltage from the bias means is applied to a source of the through-current suppressing MOS-FET. 3. The semiconductor integrated circuit device according to claim 2, wherein the N-channel type MOS-FET for suppressing a through current is provided if the driving MOSFET is a P-channel type.
Wherein the absolute value of the threshold voltage is lower than the absolute value of the threshold voltage of the driving MOSFET. 4. The semiconductor integrated circuit device according to claim 2, wherein if the driving MOS-FET is an N-channel type, the absolute value of the threshold voltage of the driving MOS-FET is set to A semiconductor integrated circuit device wherein the threshold voltage of an N-channel type through current suppressing MOS-FET is lower than the absolute value of the threshold voltage. 5. The semiconductor integrated circuit device according to claim 2, wherein said bias means switches a source of said through current suppressing MOS-FET to a predetermined positive voltage power supply. A semiconductor integrated circuit device connected to the bipolar transistor and applying the forward bias voltage to the bipolar transistor. 6. The semiconductor integrated circuit device according to claim 2, wherein said bias means is connected between a source of said through current suppressing MOS-FET and ground. A semiconductor integrated circuit device comprising a semiconductor element. 7. A semiconductor integrated circuit device according to claim 2, wherein said bias means is provided between a base of said bipolar transistor and a drain of said through-current suppressing MOS-FET. A semiconductor integrated circuit device comprising a semiconductor element connected to a semiconductor device. 8. The semiconductor integrated circuit device according to claim 1, wherein said bias means comprises at least a Schottky barrier diode. Circuit device. 9. The semiconductor integrated circuit device according to claim 2, wherein the NPN-type bipolar transistor, the P-channel-type driving MOS-FET, and the through-current suppression. MOS-FET and the bias means, and the P-channel drive MOS-FET is connected to the collector of the bipolar transistor.
A first semiconductor integrated circuit in which a drain of the P-channel type driving MOS-FET and a drain of the through-current suppressing MOS-FET are connected to a base of the bipolar transistor; The bipolar transistor, the N-channel type driving MOS-FET, the through-current suppressing MOS-FET, and the bias means; and the collector of the bipolar transistor includes the N-channel type driving MOS-FET.
A second semiconductor integrated circuit connected to a source of the N-channel type driving MOS-FET and a drain of the through-current suppressing MOS-FET at a base of the bipolar transistor; An emitter and an output terminal of the bipolar transistor of the first semiconductor integrated circuit are connected to a collector of the bipolar transistor of the second semiconductor integrated circuit. The output terminal or the bipolar transistor of the first semiconductor integrated circuit is connected to the collector of the bipolar transistor of the first semiconductor integrated circuit. In one of the bases of the bipolar transistor,
The through-current suppressing MOS-F of the second semiconductor integrated circuit
The gate of the ET is connected, for driving the P-channel type of the first semiconductor integrated circuit;
A gate of the MOS-FET, a gate of the through-current suppressing MOS-FET, and a gate of the N-channel type driving MOS-FET of the second semiconductor integrated circuit are connected to an input terminal;
A semiconductor integrated circuit device, which outputs a NOT logical operation result of a signal of the input terminal to the output terminal. 10. The semiconductor integrated circuit device according to claim 9, wherein said forward bias voltage by said bias means of said first semiconductor integrated circuit is applied to said bipolar voltage of said first semiconductor integrated circuit. A semiconductor integrated circuit device wherein a sum of a steady state allowable value of an emitter current of a transistor and a low level value of the output terminal is set. 11. The semiconductor integrated circuit device according to claim 9, wherein said bias means connects a source of said through current suppressing MOS-FET of said first semiconductor integrated circuit to said second semiconductor integrated circuit. A semiconductor integrated circuit device connected to a base of the bipolar transistor of the semiconductor integrated circuit. 12. The semiconductor integrated circuit device according to claim 9, wherein said bias means comprises two semiconductors between a source of said through-current suppressing MOS-FET of said first semiconductor circuit and ground. A semiconductor integrated circuit device, comprising: an element provided in series; and a source of the through-current suppressing MOS-FET of the second semiconductor circuit connected between the two semiconductor elements. 13. The semiconductor integrated circuit device according to claim 9, wherein a base of said bipolar transistor of said first semiconductor integrated circuit and a base of said driving MOSFET of said second semiconductor integrated circuit are provided. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to a domain by an impedance element, and does not require the through-current suppressing MOS-FET and bias means of the first semiconductor integrated circuit. 14. A semiconductor integrated circuit device according to claim 13, wherein a source of said driving MOS-FET of said second semiconductor integrated circuit and said bias means are connected by an impedance element. A semiconductor integrated circuit device which does not require the through-current suppressing MOS-FET of the second semiconductor integrated circuit. (15) Claim 13 or (14)
In the semiconductor integrated circuit device according to any one of the above items, a direction between the drain of the driving MOS-FET of the second semiconductor integrated circuit and the collector of the bipolar transistor is the forward direction from the collector to the drain. Connected by a diode, the base of the bipolar transistor of the first semiconductor integrated circuit and the domain of the driving MOSFET, and the driving MOSFET of the second semiconductor integrated circuit.
A semiconductor integrated circuit device, wherein the first semiconductor integrated circuit does not require the impedance element, by short-circuiting the domain of the FET; 16. The semiconductor integrated circuit device according to claim 9, wherein a threshold voltage of said N-channel type driving MOS-FET of said second semiconductor integrated circuit is A semiconductor integrated circuit device having an absolute value lower than an absolute value of a threshold voltage of another MOS-FET. 17. The semiconductor integrated circuit device according to claim 9, wherein said N-channel type driving MOS-FET of said second semiconductor integrated circuit includes at least said N-channel type driving MOS-FET. A semiconductor integrated circuit, wherein the absolute value of the threshold voltage of the channel type MOS-FET is lower than the absolute value of the threshold voltage of the P-channel type driving MOS-FET of the first semiconductor integrated circuit. apparatus.