JP2788890B2 - Level shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit such as a CMOS circuit, and more particularly to a level shift circuit for converting a signal voltage between a low voltage power supply circuit and a high voltage power supply circuit of a CMOS circuit.

[0002]

2. Description of the Related Art Conventionally, this type of level shift circuit is generally known, for example, as disclosed in Japanese Patent Application Laid-Open No. 60-51322.

FIG. 4 is a level shift circuit diagram showing an example of such a prior art. As shown in FIG. 4, the level shift circuit includes an N-channel MOS transistor T1 (hereinafter, referred to as NMOST1) and a P-channel MOS transistor T1 connected in series between a low-voltage power supply (ground) VSS and a first high-voltage power supply VDD1. A channel MOS transistor T2 (hereinafter referred to as PMOST2), a capacitor C connected between the gates (nodes a and b) of these MOST1 and T2, and a second high-voltage power supply different from the first high-voltage power supply VDD1 A step-down circuit 1 consisting of a diode D1 connected between VDD2 and the gate of PMOST2, and a gate of PMOST2 and VDD
And a diode D4 connected between the input voltage VI
Is supplied to the gate (node a) of the NMOS T1 and the output voltage VO is taken out from the connection point (node e) between the MOST1 and T2, thereby providing a connection between the low voltage drive circuit (not shown) and the high voltage drive circuit (not shown). This is to adjust the voltage level. Here, the capacitance of the capacitor C is PMOST2
Has a capacitance larger than that of the gate capacitance.

A diode D1 as a step-down circuit 1
The same applies to the case where the NMOS transistor whose gate and drain are short-circuited is replaced or a plurality of such NMOS transistors are connected in series. In that case, the gate,
The side where the drain is short-circuited is connected to the second high-voltage power supply VDD2.
Alternatively, it can be realized by connecting the source side to the gate of the PMOST2.

FIGS. 5A and 5B are input voltage and gate voltage characteristic diagrams according to an input state for explaining the circuit operation in FIG. As shown in FIG. 5A, Vtp represents the threshold voltage of the PMOST2, Vf represents the forward voltage of the diodes D1 and D4, VB represents the voltage of the node b, and [VDD1- | Vtp |] represents the ON state of the PMOST2. / OFF voltage, [VDD2-Vf] represents the lowest voltage that can be taken by the node b. After power-on, until the input voltage VI changes once, the NMOST1, P2
In some cases, both MOSTs 2 are off. At this time, the output voltage VO is in a HiZ (high impedance) output state in which the state of the node e is normally prohibited. Next, when the input voltage VI rises after this period, the gate voltage VB of the node b also rises, and in that state, the voltages at the respective points including the output voltage VO are stabilized.

As shown in FIG. 5B, during the period from when the power is turned on to when a high voltage is supplied to the input voltage VI and the voltage once changes, the NMOST1 and the PMT1
Both OST2 may be on. At this time, the output voltage VO outputs an intermediate voltage (X) between VDD1 and VSS. Thereafter, the input voltage VI
Falls, and when a predetermined difference is formed between the voltage and the voltage VB at the node b, the voltage at each node is also stabilized.

However, regardless of the input state, in both the states, until the input voltage VI changes,
The gate voltage VB of PMOST2 cannot be changed.

FIG. 6 is a level shift circuit diagram showing another conventional example. As shown in FIG. 6, a PMOST having a gate and a drain short-circuited is used as a diode as a step-down circuit.
6, the source of T7 is connected to VDD2, and the gate and drain of T6 are connected to PMOST2.
Connected to the respective gates. In short, PMOS
Since there is a parasitic diode at the drain of T6, PMOS
The diode D4 between the gate and the drain of T2 becomes unnecessary. Note that this circuit operates in the same manner as the circuit of FIG. 4 described above.

[0009]

The above-mentioned conventional level shift circuit has a PMOST2 as an output transistor.
Is connected to the input node a via the capacitor C, and is connected to the high voltage power supplies VDD1 and VDD2 via a diode or a MOS transistor whose gate and drain are short-circuited, so that a large amount of electric charge is stored in the gate of the PMOST2. It is stored and becomes a high potential. Moreover, when the power is turned on while the input node a is at a low potential,
When both MOST1 and T2 are off (inactive), the output voltage VO is in the HiZ state. When the electric charge stored in the gate of the PMOST2 is low and the potential is low, and the power is turned on while the input node a is at the high potential, both the MOST1 and T2 are turned on (activated state) to pass through. A current flows, and the output voltage VO becomes an intermediate voltage output.

As described above, in any state, there is no activated current path between the gate of the PMOST2 as an output transistor and any of the power supplies.
The gate will maintain the initial potential.

Therefore, such a conventional level shift circuit has a drawback that after power is turned on, a HiZ state or an intermediate voltage output state which is normally prohibited may occur until the potential of the input node changes once.

The level shift circuit is connected to high voltage power supplies (VDD1 and VDD2) via a diode or a MOS transistor whose gate and drain are short-circuited, so that a leak current flows through one of these high voltage power supplies. When the input node is at a low potential, the PMOS
The gate potential of T2 cannot be held at a low potential, and the output voltage VO
Becomes HiZ state output. As a result, the conventional level shift circuit has a drawback that the correct output voltage VO may not be maintained when a low potential level such as a low frequency operation is input.

An object of the present invention is to obtain a correct output voltage even if the voltage of an input node does not change after the power is turned on as described above, and to reduce the current consumption and operate at a low frequency. It is an object of the present invention to provide a level shift circuit which can hold a correct output voltage even when a low potential level is input.

[0014]

A level shift circuit according to the present invention is connected in series between a ground and a first power supply, supplies an input voltage to one of the gates, and extracts an output voltage from the connection point. Type and reverse conductivity type MOS transistor pair, a capacitor connected between the gates of the MOS transistor pair, and between the gate and the second power supply of the MOS transistor of the MOS transistor pair connected to the first power supply side. Control MOS connected in series
A transistor and a first step-down circuit, and a second step-down circuit and an input-stage MOS transistor connected in series between a gate and a ground of a MOS transistor connected to the first power supply side of the MOS transistor pair, The input voltage is supplied to the gate of the input-stage MOS transistor, and the output voltage is supplied to the gate of the control MOS transistor. It is configured to activate one or the other.

The level shift circuit according to the present invention is connected in series between the ground and the first power supply, supplies an input voltage to one of the gates, and takes out an output voltage from the connection point. MOS transistor pair, a capacitor connected between the gates of the MOS transistor pair, and a control transistor connected between the gate of the MOS transistor connected to the first power supply side of the MOS transistor pair and a second power supply An inverter connected between a connection point of the pair of MOS transistors and a gate of the control transistor for inverting and supplying the output voltage; and a MOS transistor connected to the first power supply side of the pair of MOS transistors. Step-down circuit and input stage transistor connected in series between the gate and ground And, supplying the input voltage to the gate of said input stage transistors, configured to activate one of the step-down circuit and the control transistor by the input voltage at power-on.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a level shift circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, the level shift circuit according to the present embodiment is supplied with an output voltage of a low-voltage circuit (not shown) as an input voltage VI, performs level adjustment to obtain an output voltage VO, and thereby obtains a high voltage. It drives a voltage system circuit (not shown). Therefore, in this level shift circuit, NMOST1 and PMOST2 which are connected in series between the low voltage power supply VSS and the first high voltage power supply VDD1 and take out the output voltage VO from the connection point (node e), and the MOST1, T2 A capacitor C connected between the gates (nodes a and b), and a diode D connected on the anode side to the second high-voltage power supply VDD2
1 and a source connected to a cathode of a diode D1 and the like forming the step-down circuit 1, a drain is connected to a gate of a PMOST2, and a gate is connected to a connection node e of the MOST1 and T2. A connected control PMOS transistor T3 and a diode D whose anode side is connected in series with the drain of the PMOST3.
2, a voltage step-down circuit 2 comprising D2, etc., and a source and a drain connected to the cathode and the ground VSS of a diode D3 forming the second voltage step-down circuit 2, respectively, and an input node to which an input voltage VI is supplied. a having an input-stage MOS transistor T4 having a gate connected to a. As in the above-described conventional example, the capacitance of the capacitor C is set to be sufficiently larger than the gate capacitance of the PMOST2.

For this reason, the level shift circuit according to the present embodiment comprises a step-down circuit between the gate of the POMST2 connected to the input node a via the capacitor C and the low-voltage power supply VSS and the second high-voltage power supply VDD2. By connecting them by 1 and 2, control is performed such that one of the step-down circuits 1 and 2 is activated by the input voltage VI.
That is, by activating one of the step-down circuits 1 and 2, the voltage VB of the gate of the PMOST2 becomes a potential according to the input voltage VI, and the output voltage VO is prevented from being in the HiZ state or the intermediate voltage state due to the through current. doing.

FIGS. 2A and 2B are input voltage and gate voltage characteristic diagrams according to input states for explaining the circuit operation in FIG. As shown in FIGS. 2A and 2B, VI is the input voltage, VB is the voltage of the node b, and V
O is an output voltage, Vtp is a threshold voltage of the PMOS T2, T3, T4, and Vf is a forward voltage per one of the diodes D1 to D3. Although not shown, NMO
The threshold voltage of ST1 is Vtn, and the step-down voltages of the first and second step-down circuits 1 and 2 are Vc1 (= Vf) and Vc2, respectively.
(= 2 × Vf), the voltage when the input node a is at a high level is Vcc. In addition, the following conditional expression is satisfied from the viewpoint of stably operating the PMOST2. In this conditional expression, the left side is the voltage VB of the node b, and the right side is PM
It represents the ON voltage of OST2.

VDD2-Vc1> VDD1- | Vtp | Vc2 + | Vtp | <VDD1- | Vtp | Vc2 + Vcc + | Vtp |> VDD1- | Vtp | First, as shown in FIG. 2A, the input voltage VI = 0V
(Ie, VSS) and the initial voltage at node b is VB> V
If DD1- | Vtp |, NMOST1, PMOS
Both T2 are off, and the output voltage VO becomes VO = HiZ. However, the voltage VB at the node b is lower than the input stage PMOST.
4 is ON, if the control PMOST3 is ON, the through current flowing through the path of the first step-down circuit 1, the control PMOST3, the second step-down circuit 2, and the input stage PMOST4, that is, between VDD2 and VSS. When the control PMOST3 is turned off, the voltage decreases due to the path of the second step-down circuit 2 and the input stage PMOST4, that is, decreases due to the current flowing between the node b and the VSS, and VB ≦ VDD1- | Vtp |. When the voltage VB of the node b changes to ≤VDD1- | Vtp |, the PMOST2 turns on, and the output voltage VO becomes VO.
= VDD1. Further, when the output voltage VO = VDD1, the control PMOST3 is completely turned off, and the voltage VB of the node b becomes VB = Vc2 + | Vtp |
<VDD1-│Vtp│.

Next, as shown in FIG. 2B, the input voltage VI = Vcc, and the initial voltage of the node b is VB ≦ VDD1.
−│Vtp│, both the NMOST1 and the PMOST2 are on, and the output voltage VO is VD
VO <VDD1- | Vtp | due to the partial voltage generated from the through current flowing between D1 and VSS, and the control PMO
ST3 is turned on. Therefore, the voltage VB of the node b is
Rises by the path of the first step-down circuit 1 and the control PMOST3, that is, by the current flowing from VDD2 to the node b, and VB ≧ VDD2-Vc2> VDD1- | Vt
p |, the PMOST2 is turned off, and the output voltage VO = VS
It becomes S. At this time, at this time, VB> Vc2 + Vcc
+ | Vtp |, the second step-down circuit 2, the input stage PM
Since a current flows through OST4, the potential V of node b
Although B decreases, as described above, VB becomes VDD1 due to the design condition of the step-down voltage Vc2 by the second step-down circuit 2.
It does not fall below-| Vtp |. Therefore, PM
OST2 is off and stable.

Also, the case where the input voltage VI = 0V, the initial voltage VB ≦ VDD1- | Vtp | of the node b, and the input voltage V
Initial voltage VB of node b at I = VCC> VDD1- | V
The case of tp | is the same as the stable state in the case described above, and therefore the description is omitted.

In short, when the input voltage VI is 0 V, the input stage PMOST4 is turned on and the control PMOST3 is turned off, so that the second step-down circuit 2 is activated and the first step-down circuit 1 is deactivated. Further, when the input voltage VI is Vcc, the input stage PMOST4 is turned off and the control PMOST3 is turned on, so that the second step-down circuit 2 is inactivated and the first
Step-down circuit 1 is activated. However, the connection node b
Is a potential at which the potential difference from the reference power supply is equal to or less than a value determined by the activated voltage down converter. When VI is 0 V and MOST1 is off, MOST
2 is turned on, VDD1- | Vtp |
When I is Vcc and MOST1 is on, MOST2
Turns off or more than VDD1- | Vtp |.

As described above, when voltage VB at node b is in a stable state, step-down circuits 1 and 2 are in an extremely high impedance state, and a transient state in which input voltage VI changes from 0V to Vcc, and from Vcc to 0V. In the changing transient state, the voltage VB of the node b changes in a state where the potential difference between VI and VB in the initial operation is almost maintained due to the coupling effect of the capacitor C. After the change, the operation converges to the stable state or maintains the stable state by the above-described operation.

The step-down voltage Vc1 of the first step-down circuit 1
Are designed so that VDD1−Vc1> VDD1- | Vtp |, the same effect can be obtained even if the second high-voltage power supply VDD2 is the same as the first high-voltage power supply VDD1.

In the present embodiment, the first step-down circuit 1 and the control MOST3 are connected between the second high-voltage power supply VDD2 and the node b, but the first step-down circuit 1 and the control MOST3 are connected. It goes without saying that the same result can be obtained even if the connection positions are switched, that is, even if the control MOST3 is connected to the VDD2 side and the first step-down circuit 1 is connected to the node b side.

Further, in the present embodiment, an example has been described in which the first and second step-down circuits 1 and 2 use diodes D1, D2 and D3. However, these diodes D1 to D3 are respectively NMOS or PMOS. The same result can be obtained by replacing the gate and drain or source by short-circuiting. In this case, it is only necessary to match the threshold voltage of the MOS transistor with the forward voltage of the diode.

Further, in this embodiment, a positive power supply is used for the first and second high-voltage power supplies VDD1 and VDD2, but a negative power supply can be used similarly. When such a negative power supply is used, it can be easily achieved by changing the conductivity type of the MOS transistor used.

In the above-described embodiment, one diode is connected as the step-down circuit 1 and two diodes are connected as the step-down circuit 2. At this time, the number of connected diodes is equal to the input voltage VI and the power supply voltage VSS. , VDD1, VD
It is designed by D2 and the threshold voltage of the MOS transistor or the forward voltage of the diode. For this reason, the connection number n of the diodes and the like used as the step-down circuit 1 is VDD2-n × Vf> VDD1- | Vtp |,
Connection number m of diodes used as step-down circuit 2
Is Vcc + m × Vf + | Vtp |> VDD1- | Vt
p |, m × Vf + | Vtp | <VDD1− | Vtp |, and if n × Vf <| Vtp |, the first high-voltage power supply VDD2 is used instead of the second high-voltage power supply VDD2. Similar results can be obtained by using the high-voltage power supply VDD1.

FIG. 3 is a level shift circuit diagram showing another embodiment of the present invention. As shown in FIG. 3, also in the level shift circuit of the present embodiment, the output voltage of the low-voltage circuit is supplied as the input voltage VI, and the level shift is performed to obtain the output voltage VO. It is driven. For this purpose, this level shift circuit comprises NMOST1 and PMOST2 connected in series between the low voltage power supply VSS and the first high voltage power supply VDD1,
An output stage transistor circuit 3 for extracting an output voltage VO from the connection point (node e), and a capacitor C connected between the gates (nodes a and b) of these MOST1 and T2.
And a control NMOS having a drain connected to the second high-voltage power supply VDD2 and a source connected to the gate of the MOST2.
A transistor T3, an inverting amplifier circuit (inverter) INV connected between the node e and the gate of the NMOS T3 for inverting and supplying the output voltage VO;
Diodes D2 and D3 connected in series to the source of OST3
A voltage step-down circuit 2 comprising a source and a drain connected to a cathode and a ground VSS of a diode D3 forming the voltage step-down circuit 2, and a gate connected to an input node (a) supplied with an input voltage VI. MOS transistor T4. Also in this case, the capacitance of the capacitor C is equal to the PMOST2
Is set so as to be sufficiently larger than the gate capacitance.

First, in the circuit of FIG. 3, the threshold voltage of the NMOS is Vtn, and the threshold voltage of the PMOS is Vtn.
p, the step-down voltage of the step-down circuit 2 composed of the diodes D1 and D2 is represented by Vc3, the voltage at the node b is represented by VB, the voltage when the input voltage VI at the input node a is at a high level is represented by Vcc, and the voltage at the output node e is represented by VO. . The step-down circuit 2 has a step-down voltage Vc3 of Vc3 + | Vtp | <VDD1-
| Vtp | and Vc3 + Vcc + | Vtp |> VDD
1− | Vtp |
V is set so that its inverted potential level is higher than the output voltage VO at which both the MOST1 and T2 are turned on.

Next, when the input voltage VI is VI = 0 V and the MO
When ST1 is off, the input stage MOST4 is turned on, and the voltage VB of the node b at that time is VB <Vc3 + | Vtp | due to the current flowing through the step-down circuit 2 and the MOST4 when the control MOST5 is off. <VDD1- | Vt
p |, the MOST of the output stage transistor circuit 3
2 is turned on, and the output voltage VO becomes VDD1. At this time, on the contrary, if the control MOST5 is on, the MOST5
5, an intermediate potential by a voltage division generated by a through current flowing between VDD2 and VSS via the step-down circuit 2, MOST4,
That is, VB <VDD1- | Vtp |, and MOST
2 turns on, the output voltage VO becomes VDD1.
Therefore, the output of the inverting amplifier circuit INV becomes 0 V,
Since the MOST 5 changes from on to off, the through current that has flowed first is also cut off.

On the other hand, when the input voltage VI is Vcc and MOST1
Is on, the initial voltage VB of the node b becomes VDD1- |
If Vtp | or lower, the output voltage VO becomes an intermediate voltage when the MOST2 is turned on.
Since the voltage is equal to or lower than the inversion voltage of NV, the output of INV is VDD
It is one. Therefore, MOST5 is turned on, and VB becomes VB.
≧ VDD2-Vtn. Therefore, V
By designing so that DD2-Vtn> VDD1- | Vtp |, the MOST2 can be turned off.

The initial voltage VB of the node b is VDD1
If −│Vtp│ or more, the MOST2 is turned off and the output voltage VO becomes 0V. As a result, the output of INV becomes VDD
1 and the MOST5 is turned on.
, The voltage VB at node b is
VB ≧ VDD2-Vtn. Therefore, MOST2 is turned off if it is designed in advance so that VDD2-Vtn> VDD1- | Vtp |. At this time,
If VB> Vc3 + Vcc + | Vtp |, a current flows through the step-down circuit 2 and the MOST4, and VB decreases.
As described above, since VB does not fall below VDD1− | Vtp | from the design condition of the step-down voltage Vc3 of the step-down circuit 2, the MOST2 is turned off and stabilized.

In short, when the input voltage VI is 0 V, M
The OST 4 is turned on, the step-down circuit 2 is activated, the MOST 5 also serving as the step-down circuit is turned off, and the voltage VB of the node b is turned off.
Is a voltage VDD1- | Vtp for turning on the MOST2.
| And when the input voltage VI is Vcc, M
The OST 4 is turned off, the step-down circuit 2 is inactivated, the MOST 5 also serving as the step-down circuit is turned on, and the voltage V
B is a voltage VDD1- | Vt for turning off the MOST2.
p | or more.

The above-described voltage step-down circuit 2 operates at the voltage V at the node b.
In a transient state in which the input voltage VI changes from 0 V to VCC or from VCC to 0 V in a stable state when B is in a stable state, the voltage VB of the node b changes due to the coupling effect of the capacitor C. potential difference between a and b, ie, V
It changes while maintaining the I · VB potential difference. After this input voltage change, the operation converges to the stable state or maintains the stable state by the same operation as the output stabilization in each input voltage state described above.

If the design is made so that Vtn <| Vtp |, the same result can be obtained even if the second high-voltage power supply VDD2 is the same as the first high-voltage power supply VDD1.

Further, in this embodiment, the diodes D2 and D3 of the step-down circuit 2 may be replaced by MOS transistors having a gate and a drain or a source connected to each other. Can be realized.

[0039]

As described above, the level shift circuit according to the present invention is a PMOS transistor in the output stage transistor circuit.
The gate of T2 and the low-voltage power supply and the gate of PMOST2 and the second high-voltage power supply are connected via a step-down circuit and a MOS transistor controlled by an input / output voltage, respectively. By activating either one, the voltage level of the gate of the PMOST2 connected to the input node via a capacitor can be determined, and the output node becomes HiZ state or becomes an intermediate voltage due to a through current. Therefore, there is an effect that a correct output voltage can be obtained even if the input voltage does not change once after the power is turned on.

Further, the level shift circuit of the present invention includes a step-down circuit and a MOS transistor controlled by an input / output voltage, so that the PMO of the output stage transistor circuit is provided.
Even if a leak current flows between the gate of ST2 and one of the power supplies, the potential change due to the leak can be ignored by the operation of the first or second step-down circuit, so that the consumption current does not need to be increased. There is an effect that a correct output potential can be maintained even at the time of inputting a low potential level such as a low frequency operation.

[Brief description of the drawings]

FIG. 1 is a level shift circuit diagram showing one embodiment of the present invention.

FIG. 2 is an input voltage and gate voltage characteristic diagram according to an input state for explaining a circuit operation in FIG. 1;

FIG. 3 is a level shift circuit diagram showing another embodiment of the present invention.

FIG. 4 is a level shift circuit diagram showing an example of the related art.

5 is an input voltage and gate voltage characteristic diagram according to an input state for explaining the circuit operation in FIG. 4;

FIG. 6 is a level shift circuit diagram showing another conventional example.

[Explanation of symbols]

 1, 2 step-down circuit T3, T5 control transistor T4 input stage transistor D1 to D3 diode INV inverter C capacitor VDD1, VDD2 high voltage power supply VSS low voltage power supply VI input voltage VO output voltage

Claims (15)

(57) [Claims] A pair of one-conductivity-type and reverse-conduction-type MOS transistors which are connected in series between ground and a first power supply, supply an input voltage to one gate, and take out an output voltage from the connection point; A capacitor connected between the gates of a pair of MOS transistors, a control MOS transistor connected in series between a gate of the MOS transistor connected to the first power supply side of the pair of MOS transistors and a second power supply, and a first step-down converter A circuit and the M
A second step-down circuit and an input stage MOS transistor connected in series between the gate of the MOS transistor connected to the first power supply side and the ground in the OS transistor pair, and the gate of the input stage MOS transistor Supplying the output voltage to the gate of the control MOS transistor and activating one of the first and second step-down circuits by the input voltage when power is turned on. Level shift circuit. 2. The level shift circuit according to claim 1, wherein each of said first and second step-down circuits is formed by connecting one or more diodes in series. 3. The level shift circuit according to claim 1, wherein each of said first and second step-down circuits has one or more MOS transistors connected in series and a gate and a drain or a source are short-circuited. 4. The first step-down circuit includes:
One or more in series, and the second step-down circuit comprises:
2. The level shift circuit according to claim 1, wherein a plurality of MOS transistors are connected in series and each gate and drain or source are short-circuited. 5. The level shift circuit according to claim 1, wherein said control MOS transistor and said input stage MOS transistor are formed of MOS transistors of the same conductivity type. 6. The level shift circuit according to claim 1, wherein said second power supply is replaced by said first power supply. 7. The level shift circuit according to claim 1, wherein said capacitor is larger than a gate capacitance of a MOS transistor connected to said first power supply side of said MOS transistor pair. 8. The control transistor and the first step-down circuit are connected in reverse order, connect the control transistor to the second power supply side, and connect to the first power supply side of the MOS transistor pair. 2. The level shift circuit according to claim 1, wherein said first step-down circuit is connected to a gate side of a MOS transistor to be operated. 9. A one-conductivity-type and reverse-conductivity-type MOS transistor pair connected in series between ground and a first power supply and supplying an input voltage to one of the gates and extracting an output voltage from the connection point. A capacitor connected between the gates of a pair of MOS transistors, a control transistor connected between the gate of the MOS transistor connected to the first power supply side and a second power supply of the pair of MOS transistors; An inverter connected between a connection point of the pair of MOS transistors and a gate of the control transistor, and
MO connected to the first power supply side of the transistor pair
A step-down circuit and an input stage transistor connected in series between the gate of the S transistor and the ground, supplying the input voltage to the gate of the input stage transistor, and the step-down circuit and the control by the input voltage at power-on A level shift circuit for activating one of the transistors. 10. The level shift circuit according to claim 9, wherein said step-down circuit is formed by connecting one or more diodes in series. 11. The level shift circuit according to claim 9, wherein said step-down circuit has one or more MOS transistors connected in series and a gate and a drain or a source are short-circuited. 12. The level shift circuit according to claim 9, wherein said control MOS transistor and said input stage MOS transistor are formed of MOS transistors of opposite conductivity types. 13. The level shift circuit according to claim 9, wherein said second power supply is replaced with said first power supply. 14. The level shift circuit according to claim 9, wherein said capacitor is larger than a gate capacitance of a MOS transistor connected to said first power supply side of said MOS transistor pair. 15. The control MOS transistor according to claim 15, wherein
A channel MOS transistor and the input stage MO
10. The level shift circuit according to claim 9, wherein the S transistor is a P-channel MOS transistor, and the control MOS transistor has a step-down function.