JP2672023B2 - Substrate voltage generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a substrate voltage generating circuit for generating a voltage to be applied to a semiconductor substrate in a semiconductor device such as an integrated circuit.

[Conventional technology]

In general, in a dynamic RAM which is a semiconductor device using a P-type semiconductor substrate, malfunction is prevented due to undershoot of an input signal, latch-up resistance is improved, and a junction capacitance between a diffusion region and a semiconductor substrate is reduced to increase speed. For these reasons, a negative voltage is applied to the substrate, and for this purpose, a substrate voltage generating circuit for generating a negative voltage is provided in the chip.

FIG. 6 is a connection diagram of a conventional substrate voltage generation circuit having an NMOS structure. In the figure, 1 is a ring oscillator which is an oscillator, 2 is a driver, C ₀ is a capacitor, Q ₁ and Q ₂ are capacitors C ₀ together with An N-channel MOSFET constituting the charge pump circuit 3, V ₀ is a node connecting the N-channel MOSFETs Q ₁ and Q ₂ , and 4 is an output terminal for outputting the main substrate voltage V _BB .

By the way, as shown in FIG. 7, the ring oscillator 1 includes a P-channel MOSFET 6 connected in series between the positive power source 5 and the ground.
And an N-channel MOSFET 7 are connected to form an inverter 8, and a connection point of both FETs 6 and 7 which are output terminals of the inverter 8 is connected to gates of both FETs 6 and 7 which are input terminals of the next-stage inverter 8. An odd number of inverters 3 of 3 or more is connected in cascade, and the output terminal of the final stage inverter 8 is connected to the input terminal of the first stage inverter 8.

8 is a cross-sectional view of the charge pump circuit 3, in which the P well 10 formed in the P type substrate 9 has an N ⁺ diffusion layer 11a,
11b and 11c are formed, the diffusion layer 11c is grounded, the diffusion layers 11a and 11b serving as drains and sources, and the gate 12a constitute the FET Q ₁ , and the diffusion layers 11b and 11c serving as drains and sources and the gate 12b, respectively. FETQ ₂ is configured,
The diffusion layer 11a, which is the gate 12a and drain of the FET Q ₁ corresponding to the output terminal 4, is the P ⁺ diffusion layer 14 for electron injection in the P well 13.
, The gate 12b is connected to the diffusion layer 11B, and the node
V ₀ is connected to capacitor C ₀ . However, 15 is an isolation oxide film.

 Next, the operation of FIG. 6 will be described.

Now, as shown in FIG. 9, the drive signal φ which is the output of the driver 2 synchronized with the periodic pulse of the ring oscillator 1.
When the voltage of ₀ rises from 0 to V _P, due to capacity coupling by the capacitor C ₀ voltage node V _0, increases from 0 to V _P, FETs Q ₂ is turned on, the threshold of the FETs Q ₂ Voltage to V _TH2
When, drop to the voltage V _TH2 of the nodes V _0, the subsequent drive signal phi ₀ falls to 0 V _P, due to capacity coupling by the capacitor C _0, the voltage at node V ₀ from the V _TH2 ( V
_TH2 falls -V _P).

At this time, the FET Q ₂ is in the off state, but the FET Q ₁ is in the on state, so that the substrate voltage V _BB decreases.

When the threshold voltage of FET Q ₁ is set to V _TH1 by repeating such operations, the substrate voltage V _BB finally becomes (V
_TH1 + V _TH2 -V _P) and made to be stable.

On the other hand, the conventional substrate generating circuit having the PMOS structure has the structure shown in FIG. 10, except that the charge pump circuit 3 shown in FIG. 6 is replaced by the charge pump circuit 3'comprising P-channel MOSFETs Q ₃ and Q ₄ . The configuration is the same as in FIG. However,
V ₀ ′ is a node that connects FETs Q ₃ and Q ₄ .

And, FIG. 11 is a sectional view of the charge pump circuit 3 ′, which is different from FIG. 8 in that the N well formed in the P type substrate 9 is formed.
P ⁺ diffusion layers 17a, 17b, 17c are formed in 16 and the diffusion layer 17c is grounded, and the diffusion layers 17a, 17b become the source and the drain, respectively.
FET Q ₃ is composed of the gate 18a and the diffusion layers 17b and 17c serving as the source and drain, respectively, and the gate 18b.
The FET Q ₄ is constituted, and the diffusion layer 17a, which is the source of the FET Q ₃ corresponding to the output terminal 4, is the P ⁺ diffusion layer 2 for electron injection in the P well 19.
Gates 18a and 18b are connected to the diffusion layers 17b and 17c, respectively.
, And node V ₀ ′ is connected to capacitor C ₀ .

However, 21 is an N ⁺ diffusion layer formed in the N well 16 and is connected to the power supply 22.

At this time, the operation of the substrate voltage generation circuit of the PMOS configuration shown in FIG. 10 is the same as that of the NMOS configuration shown in FIG.
When the threshold voltages V _TH3 and V _{TH4 of the} P-channel MOSFETs Q ₃ and Q ₄ are set, the substrate voltage V _BB finally becomes (V _TH3 + V _TH4 −V _P ) and becomes stable.

By the way, in the case of the NMOS configuration in FIG. 6, as described above, the substrate voltage V _BB in the steady state is (V _TH1 + V _TH2 −
V _P ), but the voltage of the node V ₀ periodically drops to a voltage (V _TH2 −V _P ) lower than the steady-state substrate voltage V _BB , and as a result, in FIG. 8, it is connected to the node V ₀ . N ⁺ diffusion layer 11
A forward bias is periodically applied to the PN junction between b and the p well 10 thereunder, and electrons are periodically injected from the diffusion layer 11b to the substrate 9 through the p well 10. become.

Here, the period of injection of electrons into the substrate 9 is equal to the period of the drive signal φ ₀ of the driver 2, that is, the oscillation period of the ring oscillator 1.

When the power supply voltage of the ring oscillator 1 is V _CC , the higher the power supply voltage V _CC is, the higher the oscillation frequency thereof is, the shorter the oscillation cycle is, the more frequently electrons are injected into the substrate 9, and, for example, the dynamic frequency is increased. In the case of RAM, if this frequency becomes high, electrons injected into the substrate 9 may reach the memory cell portion and destroy the information stored in the memory cell portion. In the dynamic RAM employing the generation circuit, there is a possibility that the electrons injected into the substrate 9 may cause malfunctions, especially when the power supply voltage V _CC is high.

On the other hand, in the case of the substrate voltage generation circuit having the PMOS configuration, as described above, the substrate voltage V _BB in the steady state is (V _TH3 + V _TH4
Whereas a -V _P), the node V ₀ 'voltage drops to periodically lower than the substrate voltage V _BB in a steady state (V _TH4 -V _P), the node V _0' periodic voltage of Substrate voltage V _BB during steady state
It is similar to the NMOS substrate voltage generation circuit in that the voltage is reduced to a lower voltage.

However, as shown in FIG. 11, unlike the case of the NMOS structure, the node V ₀ ′ is connected to the P ⁺ diffusion layer 17b, and the PN junction between the node V ₀ ′ and the N well 16 is in the reverse direction to the node V ₀ ′. As a result, a bias is applied, and as a result, electrons are not injected into the substrate 9 as in the substrate voltage generating circuit having the NMOS structure, and the stored information in the memory cell portion is not destroyed in the case of dynamic RAM. The substrate voltage generation circuit of the PMOS configuration is superior to the NMOS configuration only when the power supply voltage V _CC is high.

By the way, in the case of the substrate voltage generation circuit having the NMOS configuration, the substrate voltage V _BB is ideally (V _TH1 + V _TH2 −
Stable at V _P), but in general when the semiconductor device is in an operative state with the various circuit operations of the board occurs injection of holes into the substrate 9, the substrate voltage V so-called substrate current flows
_{Since BB} is pulled in the positive direction, the substrate voltage V _BB is actually larger than (V _TH1 + V _TH2 −V _P ).

The same applies to the substrate voltage generation circuit having the PMOS structure.

However, when the substrate voltage V _BB is greatly affected by the substrate current and the absolute value of the substrate voltage V _BB becomes smaller, electrons are injected into the substrate 9 due to the undershoot of the input signal of the semiconductor device, which causes a dynamic change. In the case of RAM, the stored information in the memory cell part is destroyed, the junction capacitance between the diffusion layer and the substrate increases, and the circuit operation speed deteriorates and the resistance to latch-up decreases. Occurs.

Therefore, in order to cancel the influence of the substrate current on the substrate voltage V _BB , it is necessary to increase the current driving force of the charge pump circuit. The current driving force of the charge pump circuit is the same as that shown in FIGS. 6 and 10. Then, the frequency of the ring oscillator 1, the drive signal, that is, the amplitude of the output voltage φ ₀ of the driver 2
V _P , the capacitor C _0, and the resistance of the transistors Q ₁ and Q ₂ or Q ₃ and Q ₄ forming the charge pump circuits 3 and 3 ′, respectively.

In addition, since the mobility of electrons is higher than the mobility of holes, if the charge pump circuit is composed of transistors of the same size, the NMOS configuration can have a smaller resistance than the PMOS configuration. It is possible to further increase the current driving force of.

Further, the voltage V _P is the amplitude of the output voltage of the driver 2, usually it is often equally designed to supply voltage V _CC, from these facts, the power supply voltage V _CC is the case high output voltage of the driver 2 Since the amplitude V _{P of} the charge pump circuit also increases and the current driving capability of the charge pump circuit increases, a sufficient level of substrate voltage can be obtained regardless of whether the charge pump circuit has an NMOS configuration or a PMOS configuration.

However, when the power supply voltage V _CC is low, the current driving capability of the charge pump circuit becomes considerably small, and the influence of the substrate current on the substrate voltage V _BB cannot be ignored.
_{When the CC} is low, the charge pump circuit that increases the current driving force is more advantageous in the NMOS configuration than in the PMOS configuration.

From the above, when the power supply voltage V _CC is high, electron injection into the substrate does not occur, so the substrate voltage generation circuit of the PMOS configuration is superior to the NMOS configuration, but when the power supply voltage V _CC is low Since the current driving capability of the charge pump circuit can be increased, the NMOS configuration is more advantageous than the PMOS configuration.

[Problems to be solved by the invention]

The conventional substrate voltage generation circuit is an NMOS as shown in FIG.
Since it has either the configuration or the PMOS configuration as shown in FIG. 10, the power supply voltage V _CC is required in the NMOS configuration as shown in FIG.
When the power supply voltage V _CC is low, a sufficient substrate voltage cannot be generated in the PMOS configuration as shown in Fig. 10.
There was a problem that it did not work well when _CC fluctuated between high and low.

By the way, as a specific prior art example as a substrate voltage generating circuit, Japanese Patent Publication No. 114712/1985, JP-A-60-54467.
JP-A No. 60-62147 and JP-A No. 60-62147 have the NMOS configuration shown in FIG. 6 or the PM shown in FIG.
Since it corresponds to any of the OS configurations, the above-mentioned inconvenience occurs.

The present invention has been made to solve the above-mentioned problems, and supplies a sufficient substrate voltage without causing a malfunction even when the power supply voltage V _CC fluctuates between high and low. The purpose is to ensure stable operation.

[Means for solving the problem]

A substrate voltage generating device according to the present invention is a substrate voltage generating circuit that generates a voltage applied to a substrate that constitutes a semiconductor device, and an oscillator that generates a periodic pulse, and a driver that outputs a drive signal using the periodic pulse as an input. A first charge pump circuit including the drive signal as an input and including a first capacitor and an N-channel MOS transistor; a second charge pump circuit including the drive signal as an input and including a second capacitor and a P-channel MOS transistor; A substrate voltage output terminal connected to the output terminal of the pump circuit, a detection means for detecting whether the power supply voltage of the oscillator and the driver is higher or lower than a set threshold voltage, and the power supply voltage operated by the output of the detection means. Is higher and lower than the set threshold voltage, respectively, the second,
And a control means for driving the first charge pump circuit.

[Action]

According to the present invention, the detection means detects whether the power supply voltage is higher or lower than the set threshold voltage, and the control means respectively controls the second and first charge pump circuits when the power supply voltage is higher or lower than the set threshold voltage. Therefore, when the power supply voltage is higher than the set threshold voltage, the second charge pump circuit composed of the P-channel MOS transistor operates, electron injection into the substrate does not occur, and the occurrence of malfunction is prevented. When the power supply voltage is lower than the set threshold voltage, the first charge pump circuit composed of N-channel MOS transistors operates to supply a sufficient substrate voltage.

[Embodiment] FIG. 1 is a connection diagram of an embodiment of a substrate voltage generating circuit of the present invention.

Referring to FIG. 1, a detection means 23 is provided for detecting whether the power supply voltage V _{CC of the} ring oscillator 1 and the driver 2 is higher or lower than a set threshold voltage.
Output φ ₁ , ₁ becomes high level (hereinafter referred to as H) and low level (hereinafter referred to as L) respectively, and when it is low, φ ₁ , ₁ becomes L and H respectively.

The transmission gate 24a which is turned on when the outputs φ ₁ and ₁ of the detection means 23 are L and H, and φ ₁ and
There is provided a control means 24 comprising a transmission gate 24b which is turned on when ₁ is H and L respectively, and a capacitor C _0a is provided via one transmission gate 24a.
And a first charge pump circuit 25 including N-channel MOSFETs Q _1a and Q _2a is connected to the driver 2, and a second charge pump circuit including a capacitor C _0b and P-channel MOSFETs Q _1b and Q _2b is connected via the other transmission gate 24b. 26
Is connected to the driver 2 and both charge pump circuits 25, 26
The output terminal of is a common board voltage output terminal of board voltage V _BB 27
It is connected to the.

By the way, the detecting means 23 is configured as shown in FIG. 2, for example, and three N-channel MOSFETs Q ₅ , Q ₆ , Q ₇ and the same positive power supply 5 as the positive power supply 5 of the ring oscillator 1 are connected to the ground. resistance of the sum is greater than the resistance value of the conduction resistance of each FETs Q ₅ to Q ₇ 28
Is connected in series and connects the FET Q ₇ and the resistor 28 to the node N.
₁ is connected to the φ ₁ output terminal via a series circuit of two inverters 29 and 30, and the inverter 29 is connected to the node N _1.
1 output terminal is connected via.

Here, assuming that the threshold voltages of the FETs Q ₅ , Q ₆ , and Q _{7 in} FIG. 2 are V _TA , V _TB , and V _TC , respectively, when V _CC ≤ (V _TA + V _TB + V _TC ), Since each FET Q ₅ , Q ₆ , and Q ₇ is turned off, node N
The voltage of node ₁ is 0V, and when V _CC > (V _TA + V _TB + V _TC ), each FET Q ₅ , Q ₆ , and Q ₇ is turned on, so the voltage of node N ₁ is {V _CC − (V _TA + V _TB + V _TC )}.

Therefore, the voltage of this node N ₁ {V _CC − (V _TA + V _TB +
V _TC )} becomes equal to the input threshold voltage of the inverter 29, the power supply voltage V _CC is the set threshold voltage V _S of the detection means 23.
When the power supply voltage V _CC is higher than the set threshold voltage V _S , the outputs φ ₁ and ₁ are H and L, respectively, and when the power source voltage V _CC is low, the outputs φ ₁ and ₁ are L and H, respectively.

For example, if the input threshold voltage of the inverter 29 is V _CC / 2, V _TA
= V _TB = V _TC = 0.9 V, V _CC − (V _TA + V _TB + V _TC ) =
V _CC is V _S becomes which satisfies V _CC 2, which than V _S = 5.4V is obtained, phi ₁ when V _CC> 5.4V, ₁ is respectively H, L, and the
When V _CC <5.4V, φ ₁ and ₁ are L and H, respectively.

When the power supply voltage V _CC is higher than the set threshold voltage V _S , the outputs φ ₁ and ₁ of the detection means 23 are H and L, respectively,
The transmission gates 24a and 24b are turned off and on, respectively, and the drive signal φ ₀ that is the output of the driver 2 is input to the second charge pump circuit 26 via the transmission gate 24b in the on state, and the second charge pump circuit 26
Works.

On the other hand, when the power supply voltage V _CC is lower than the set threshold voltage V _S , the outputs φ ₁ and ₁ of the detecting means 23 become L and H, respectively,
The transmission gates 24a and 24b are respectively turned on and off, and the drive signal φ ₀ which is the output of the driver 2 is input to the first charge pump circuit 25 via the transmission gate 24a in the on state, and the first charge pump circuit 25
Works.

Therefore, when V _CC > V _S , P-channel MOSFETs Q _1b , Q
_Since the second charge pump circuit 26 composed of _2b operates,
There is no electron injection into the substrate like in the substrate voltage generation circuit of the NMOS configuration, and in a dynamic RAM, for example, the stored information in the memory cell section is not destroyed by the electron injection, and a malfunction is prevented. be able to.

On the other hand, when V _CC <V _S , N-channel MOSFETs Q _1a , Q _2a
Since the first charge pump circuit 25 consisting of is operated, a sufficient substrate voltage V _BB can be supplied, and even if the power supply voltage V _CC is considerably low, the input signal To suppress the destruction of information stored in the memory cell section of the dynamic RAM caused by electrons injected into the substrate due to undershoot, deterioration of withstand capacity against latch-up, or deterioration of circuit operating speed due to increase in junction capacitance between the diffusion layer and the substrate. You can

Figure 3 is a wiring diagram of the detection means 23 'in another embodiment, is provided with a timer circuit utilizing the operation of the charge pump circuit 31 consisting of capacitor C _1, C ₂ and N-channel MOSFET Q _8, Q ₉ .

When the power supply voltage V _CC is higher than the set threshold voltage V _S , the FETs Q _{5 to} Q ₇ are turned on, the node N ₁ becomes H, and the output φ ₁ becomes H via the inverter 29 and the NAND gate 32.
Output ₁ becomes L through the inverter 33, and P channel
MOSFET Q ₁₀ is turned on by the L output of inverter 29, and N
Since the channel MOSFET Q ₁₁ is off, the capacitor C ₂ is charged by turning on the FET Q ₁₀ , the node N ₂ becomes H, the input of the inverter 34 becomes H, and its output becomes L.

Next, when the power supply voltage V _CC fluctuates to a value lower than the set threshold voltage V _S , the FETs Q _{5 to} Q ₇ are turned off and the node N ₁ becomes L and the output of the inverter 29 becomes H, but the inverter 34
Since the output of L remains L, the output φ ₁ is still H,
₁ remains L.

At this time, since the output of the inverter 29 is H as described above, one input of the AND gate 35 is the inverter 29.
Goes high, and the output level of the AND gate 35 is determined by the drive signal φ ₀ to the other input.

Then, the driving signal phi ₀ is to consist of voltage 0 V _P, the voltage of the node N ₃ rises from zero to the capacitive coupling of the capacitor C ₁ to V _P, FETs Q ₈ is turned on, the FETs Q ₈ If the threshold voltage is V _TH8 , the voltage of the node N ₃ is lowered to V _TH8 by turning on the _{FET Q 8} .

Next, when the drive signal φ ₀ drops from the voltage V _P to 0, the voltage of the node N ₃ further decreases from V _TH8 to (V _TH8 −V _P ) due to the capacitive coupling by the capacitor C _1. When FE
TQ ₈ turns off, but FETQ ₉ turns on,
Capacitor C ₂ is discharged through the gate of FETQ ₉ and node N
The voltage of ₂ drops, and immediately after that, the drive signal φ ₀ becomes 0
The same operation is repeated again by increasing from V _P to V _P.

Then, by repeating the above operation, the node N ₂
The voltage of is gradually changed from H to L, and in response to this change, the output of the inverter 34 is changed from L to H,
Φ ₁ which is the output of the NAND gate 32 changes from H to L,
₁ changes from L to H.

Further, when the power supply voltage fluctuates to a value higher than the set threshold voltage V _S , the FETs Q _{5 to} Q ₇ are turned on, the output of the inverter 29 becomes L, and the outputs φ ₁ and ₁ are immediately output via the NAND gate 32. Change to H and L.

That is, when the power supply voltage V _CC is changed to a high state from lower than the set threshold voltage V _S state, the output phi _{1, 1} is changed immediately in response to changes in the power supply voltage V _CC, the power supply voltage V _CC When the state changes from a state higher than the set threshold voltage V _S to a state lower than the set threshold voltage V _S, the voltage of the node N ₂ does not change from H to L immediately due to the operation of the charge pump circuit 31, and it takes some time. The change of the output φ ₁ , ₁ is delayed by the time.

Therefore, by using the detecting means 23 'having the configuration shown in FIG. 3, the operation of the charge pump circuits 25 and 26 can be performed even if the power supply voltage V _CC fluctuates frequently in a short time before and after the set threshold voltage V _S. Can be prevented from fluttering in a short time, and the operation of the substrate voltage generating circuit can be stabilized.

FIG. 4 is a connection diagram of still another embodiment of the present invention. What is different from FIG.
Instead of 24a and 24b, an AND gate 3 that constitutes the control means 36
6a and 36b are provided, and the operations of both charge pump circuits 25 and 26 are switched by both AND gates 36a and 36b.

By the way, the output of the driver 2 is input to one input of both AND gates 36a and 36b, the output _{1 of the} detecting means 23 is input to the other input of the AND gate 36a, and the other input of the AND gate 36b. The output φ ₁ of the detection means 23 is input.

As described above, by operating the AND gates 36a and 36b, both charge pumps 25 and 26 can be operated in accordance with the low and high levels of the power supply voltage V _CC , as in the case of FIG.

Next, FIG. 5 shows an embodiment in which two ring oscillators and two drivers are provided, and a NAND gate G _a , is provided at the stage subsequent to the last inverter of the ring oscillators 1a, 1b.
G _b is inserted into each of the ring oscillators 1a, 1 so that the NAND gates G _a and G _b of the ring oscillators 1a and ₁ are driven by the outputs ₁ and φ ₁ of the detection means 23, and the output pulses of the ring oscillators 1a and 1b are driven by the drivers 2a and 2b. The charge pump circuits 25 and 26 are respectively driven by drive signals from the drivers 2a and 2b.

At this time, the NAND gates G _a and G _b are connected to both charge pumps 25,
It corresponds to the control means for driving 26.

When the power supply voltage V _CC is higher than the set threshold voltage V _S , the outputs φ ₁ and ₁ of the detection circuit 23 become H and L, respectively, and only the ring oscillator 1b operates and the second charge pump circuit 26 operates. When it operates and the power supply voltage V _CC is lower than the set threshold value V _S , the outputs φ ₁ and ₁ of the detection circuit 23 are respectively
It becomes L and H, and only the ring oscillator 1a operates and the first charge pump circuit 25 operates, and the same effect as in the case of FIG. 1 can be obtained.

Of course, the detecting means 23 in FIGS. 4 and 5 may be the detecting means 23 'having the configuration shown in FIG.

Further, in the above embodiment, the case of the P-type substrate has been described, but the present invention can be similarly implemented even if the substrate is the N-type substrate. At this time, the substrate voltage generating circuit generates a positive voltage. Become.

〔The invention's effect〕

As described above, according to the present invention, when the power supply voltage is higher or lower than the set threshold voltage, the control means drives the second and first charge pump circuits. When the voltage is higher than the voltage, it is possible to prevent the occurrence of malfunction due to electron injection into the substrate as in the conventional case, and when it is low, it is possible to supply a sufficient substrate voltage and obtain stable operation.
It is extremely effective as a substrate voltage generation circuit in a semiconductor device such as a RAM.

[Brief description of the drawings]

1 is a connection diagram of an embodiment of the substrate voltage generating circuit of the present invention, FIG. 2 is a connection diagram of a portion of FIG. 1, FIG. 3 is a connection diagram of a portion of another embodiment, and FIG. FIG. 5 and FIG. 5 are wiring diagrams of other different embodiments, FIG. 6 is a wiring diagram of a conventional substrate voltage generating circuit, FIG. 7 is a partial wiring diagram of FIG. 6, and FIG. FIG. 9 is a sectional view of each signal for explaining the operation of FIG. 6, FIG. 10 is a wiring diagram of another conventional substrate voltage generating circuit, and FIG. 11 is a sectional view of FIG. is there. In the figure, 1,1a and 1b are ring oscillators, 2,2a and 2b are drivers, 5 is a positive power source, 23 and 23 'are detection means, 24 and 36 are control means, and 25 and 26 are first and second charge. A pump circuit, 27 is a substrate voltage output terminal, C _0a and C _0b are capacitors, Q _1a and Q _2a are N-channel MOSFETs, Q _1b and Q _2b are P-channel MOSFETs, and G _a and G _b are NAND gates. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A substrate voltage generating circuit for generating a voltage applied to a substrate constituting a semiconductor device, an oscillator for generating a periodic pulse, a driver for outputting a drive signal with the periodic pulse as an input, and a drive signal for the drive signal. First capacitor and N channel as input
A first charge pump circuit including a MOS transistor, a second capacitor and a P channel which receives the drive signal as an input
A second charge pump circuit composed of a MOS transistor, a substrate voltage output terminal connected to the output terminals of both charge pump circuits, and a detection for detecting whether the power supply voltage of the oscillator and driver is higher or lower than a set threshold voltage. And a control unit that operates according to the output of the detection unit and that drives the second and first charge pump circuits when the power supply voltage is higher and lower than the set threshold voltage, respectively. Substrate voltage generator circuit.