JPH03173465A - Substrate voltage generating circuit - Google Patents

Abstract

PURPOSE:To secure stable operation even when a power supply voltage changes high and low, by making a control circuit drive either one of two charge pump circuits, when the power supply voltage is higher and lower than a set threshold value. CONSTITUTION:When a power supply voltage Vcc is higher than a set threshold voltage Vs, the output voltage phi1 and -phi1 of a detecting means 23 turn to H and L, respectively; transmission gates 24a and 24b turn ON and OFF, respectively; a driving signal phi0 being the output of a driver 2 is inputted to a second charge pump circuit 26, via the gate 24b in the ON-state; thus the circuit 26 operates. In the case of Vcc<Vs, the outputs phi1 and -phi1 of the means 23 turn to L and H, respectively; the gates 24a and 24b turn ON and OFF, respectively; the output signal phi0 of the driver 2 is inputted to a first charge pump circuit 25, via the gate 24a in the ON-state, thus the circuit 25 operates. As a result, electrons are not injected into the substrate in the case of Vcc<Vs, and the destruction of stored data in a memory cell part is not caused in the case of Vcc>Vs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate voltage generation circuit that generates a voltage to be applied to a semiconductor substrate in a semiconductor device such as an integrated circuit.

[Conventional technology]

In general, dynamic RAM, which is a semiconductor device using a P-type semiconductor substrate, prevents malfunctions due to input signal undershoot, improves resistance to latch-up, and increases speed by reducing junction capacitance between the diffusion region and the semiconductor substrate. For these reasons, a negative voltage is applied to the substrate, and for this purpose a substrate voltage generation circuit that generates a negative voltage is provided on the chip.

FIG. 6 is a wiring diagram of a conventional substrate voltage generation circuit with an NMO3 configuration. In the figure, 1 is a ring oscillator which is an oscillator, 2 is a driver, C is a capacitor, Q, Q
is an N-channel MO3FET that constitutes the chain bomb circuit 3 together with the capacitor CO.
1vo is a node connecting this N-channel MO3FETQ1°Q, and 4 is an output terminal that outputs the main substrate voltage vI3B.

By the way, as shown in FIG. 7, the ring oscillator 1 has a P-channel MO3FE connected in series between the positive power supply 5 and the ground.
T6 and N-channel MO3FET7 are connected to form an inverter 8, and both FETs, which are the output terminals of the inverter 8,
The connection point of ET6, 7 is connected to the gate of both FET6.7 which is the input terminal of the next stage inverter 8, and an odd number of inverters 8 of 3 or more are connected in cascade, and the output of the final stage inverter 8 The terminal is connected to the input terminal of the first stage inverter 8.

Further, FIG. 8 is a cross-sectional view of the charge pump circuit 3,
An N diffusion layer 11 is formed in a P well 10 formed on a P type substrate 9.
a, 1 l b, 11 c are formed, the diffusion layer 11 c is grounded, and the FETQ is
The FETQ2 is composed of the diffusion layer 11b, IIC, and the gate 12b, which serve as the drain and source, respectively, and the gate 12 of the FETQl corresponds to the output terminal 4.
The diffusion layer 11a serving as the gate a and the drain is connected to the P diffusion layer 14 for electron injection in the P well 13, the gate 12b is connected to the diffusion layer 11b, and the node V is connected to the diffusion layer 11a. is the capacitor co
It is connected to the. However, 15 is an isolation oxide film.

Next, the operation shown in FIG. 6 will be explained.

Now, as shown in FIG. 9, the drive signal φ which is the output of the driver 2 synchronized with the periodic pulse of the ring oscillator 1
When the voltage of node Vo rises from 0 to Vp, the voltage of node Vo rises from 0 to Vp due to capacitive coupling by capacitor co, FETQ turns on, and if the threshold voltage of FETQ2 is V, The voltage at node V is V
TH20T112 goes down, and then when the drive signal φ0 falls from Vp to O,
Due to the capacitive coupling by the capacitor co, the voltage at the node V 2 drops from the above V 2 to (vT11□OTH2 VP).

At this time, FETQ2 is in the off state, but FETQ
is turned on, the substrate voltage vBB decreases by ■.

By repeating this operation, FETQ
If the threshold voltage is V, then the substrate type L
THI pressure V finally becomes (V + V - V) and B
Tll TlI2 P is stable.

On the other hand, the conventional substrate generation circuit with the PMO3 configuration has the configuration shown in FIG. 10, and the charge pump circuit 3 in FIG.
The configuration is the same as that in FIG. 6 except that the charge pump circuit 3' consisting of channel MO3FETQ and Q4 is replaced. However, V.

is a node connecting FETQ and Q4.

FIG. 11 is a sectional view of the charge pump circuit 3', and unlike FIG. 8, P2 diffusion layers 17a and 17b are formed in the N well 16 formed in the P type substrate 9.

17c is formed, the diffusion layer 17c is grounded, and the FETQ3 is constituted by the diffusion layers 17a, 17b and gate 18a, which become the source and drain, respectively, and the diffusion layers 17b, 17c and the gate 18, which become the source and drain, respectively.
FETQ4 is configured by b, and the diffusion layer 17a which is the source of FETQ3 corresponding to the output terminal 4 is connected to the N well 19.
P for electron injection inside is connected to the diffusion layer 20 and connected to the gate 18
a.

18b are connected to diffusion layers 17b and 17c, respectively, and node V is connected to capacitor Co.

However, 21 is an N+ diffusion layer formed in the N well 16, and is connected to a power supply 22.

At this time, the operation of the substrate voltage generation circuit with the PMOS configuration shown in FIG. 10 is similar to that of the NMO3 configuration shown in FIG. 6, and the P-channel MO5FETQ3. If the threshold voltages of Q are v and v, then 4
Tl13 TI+4 board voltage number final (" Tll3 TlI4 PBB
+v −■) and becomes stable.

By the way, in the case of the NMO3 configuration shown in FIG. 6, as mentioned above, the substrate voltage VBB in the steady state is (V + V
-V), but node V.

The voltage of Ti1l TlI2 P is periodically lower than the steady state substrate voltage vBB (V - V
), and as a result, in FIG. 8, the N diffusion layer 11 connected to the node VO
A forward bias is periodically applied to the PN junction between the p-well 10 and the p-well 10 below the diffusion layer 11.
Electrons are periodically injected into the substrate 9 from the p-well 10 from the p-well 10.

Here, the period of injection of electrons into the substrate 9 is equal to the period of the drive signal φ0 of the driver 2, that is, the oscillation period of the ring oscillator 1.

Also, the power supply voltage of ring oscillator 1 is V. When set to 0, the power supply voltage V. As 0 becomes higher, the oscillation frequency becomes higher and the oscillation period becomes shorter, and the frequency with which electrons are injected into the substrate 9 also increases. For example, in the case of a dynamic RAM, when this frequency increases, the electrons injected into the substrate 9 become more A phenomenon may occur in which the voltage reaches the cell section and destroys the information stored in the memory cell section.In a dynamic RAM that employs a substrate voltage generation circuit with an NMO8 configuration, especially when the power supply voltage Vcc is high, There is a risk that malfunctions may occur due to electrons injected into the substrate 9.

On the other hand, in the case of a substrate voltage generation circuit with PMO8 configuration, as mentioned above, the substrate voltage "BB" in the steady state is (V
+V −V), whereas ノTH3Tl4
The voltage of P-do V' periodically decreases to (V-V) lower than the steady state substrate voltage, and the voltage of No.
This circuit is similar to the substrate voltage generation circuit having the NMO3 configuration in that the voltage of Tl4P-doV periodically decreases to a voltage lower than the substrate voltage vBB during steady state.

However, as shown in FIG. 11, unlike in the case of the NMO3 configuration, the node ■ is connected to the P diffusion layer 17b, and a reverse bias is applied to the PN junction between it and the N well 16 below. As a result, electrons are not injected into the substrate 9 unlike in a substrate voltage generation circuit with an NMO5 configuration, and in the case of a dynamic RAM, the stored information in the memory cell section is not destroyed, and the power supply voltage . As long as 0 is high, the substrate voltage generation circuit with PMO3 configuration is N
Superior to MO5 configuration.

By the way, in the case of a substrate voltage generation circuit having an NMO5 configuration, the substrate voltage vI3B is ideally (V
+V -VP), but generally Tl1l
TlI2 When the semiconductor device is in operation, holes are injected into the substrate 9 due to various circuit operations on the substrate, and a so-called substrate current flows and the substrate voltage VI3B is pulled in the positive direction, so that the substrate voltage ■BB is actually (V +
Tl1l TlI to a value larger than V - V)
2 P becomes.

The same can be said of the substrate voltage generation circuit having the PMO3 configuration.

However, when the substrate voltage VBB is greatly influenced by the substrate current and the absolute value of the substrate voltage vBB becomes small, electron injection into the substrate 9 occurs due to the undershoot of the input signal of the semiconductor device, which causes the dynamic RAM to In some cases, the information stored in the memory cell section may be destroyed, or the junction capacitance between the diffusion layer and the substrate may increase, resulting in disadvantages such as deterioration of circuit operation speed and reduced resistance to latch-up. .

Therefore, in order to cancel the influence of the substrate current on the substrate voltage vBB, it is necessary to increase the current driving power of the charge pump circuit, and the current driving power of the charge pump circuit is , the frequency of the ring oscillator 1, the amplitude V of the drive signal, that is, the output voltage φ of the driver 2, the capacitor P, the transistors Q, Q, or Q, Q41 constituting each of the capacitor C6 and the charge pump circuit 3.9.
It is determined by the resistance of 2 3.

Also, since the mobility of electrons is greater than that of holes,
When a charge pump circuit is constructed using transistors of the same size, the resistance of the NMO8 configuration can be lower than that of the PMO8 configuration, and the current driving power of the charge pump circuit can be increased.

Furthermore, the voltage Vp is the amplitude of the output voltage of the driver 2, and is usually the power supply voltage V. For these reasons, the power supply voltage vc is often designed to be equal to 0.

When Vp is high, the amplitude Vp of the output voltage of driver 2 also becomes large, and the current driving power of the charge pump circuit becomes large. Therefore, whether the charge pump circuit has an NMOS configuration or a PMO3 configuration, the substrate voltage can be maintained at a sufficient level. can be obtained.

However, when the power supply voltage Vcc is low, the current driving power of the charge pump circuit becomes considerably small, and the influence of the substrate current on the substrate voltage VBB cannot be ignored. When 0 is low, the NMO3 configuration is more advantageous than the 2MO8 configuration for a charge pump circuit that increases the current driving force.

From the above, when the power supply voltage vcc is high, electron injection into the substrate does not occur, so the substrate voltage generation circuit with the PMOS configuration is superior to the NMO8 configuration.
When CC is low, the current driving power of the charge pump circuit can be increased, so the NMO8 configuration is more advantageous than the PMO5 configuration.

[Problem to be solved by the invention]

The conventional substrate voltage generation circuit has N M as shown in FIG.
Since it is either an OS configuration or a PMO3 configuration as shown in FIG. 10, the power supply voltage is V in the NMO3 configuration as shown in FIG. 0 is high, malfunction may occur, and in the PMO'S configuration as shown in Figure 10, the power supply voltage V
. If C is low, sufficient substrate voltage cannot be generated, and both configurations have a power supply voltage of V. There is a problem in that it does not work well when 0 fluctuates between high and low.

By the way, as a specific prior art example of a substrate voltage generation circuit, Japanese Patent Publication No. 1-14712 is disclosed.

JP-A-60-54467, JP-A-60-6214
Although there are those described in Publication No. 7, these correspond to either the NMO3 configuration shown in FIG. 6 or the 2MO8 configuration shown in FIG. 10, and therefore the above-mentioned problems occur.

This invention was made to solve the above-mentioned problems, and the power supply voltage V. It is an object of the present invention to provide a sufficient substrate voltage to ensure stable operation without causing malfunction even when C fluctuates between high and low levels.

[Means to solve the problem]

A substrate voltage generation device according to the present invention includes, in a substrate voltage generation circuit that generates a voltage applied to a substrate constituting a semiconductor device, an oscillator that generates periodic pulses, and a driver that receives the periodic pulses as input and outputs a drive signal. , a first charge pump circuit that receives the drive signal as an input and includes a first capacitor and an N-channel MOS transistor; a second charge pump circuit that receives the drive signal as an input and includes a second capacitor and a P-channel MOS transistor;
a second charge pump circuit composed of a transistor, a substrate voltage output terminal connected to the output terminals of both charge pump circuits, and a detection means for detecting whether the power supply voltage of the oscillator and driver is higher or lower than a set threshold voltage. and when the power supply voltage is higher and lower than the set threshold voltage, the second. The charge pump circuit is characterized by comprising a control means for driving the first charge pump circuit.

[Effect]

According to this invention, the detection means detects whether the power supply voltage is higher or lower than the set threshold voltage, and when the power supply voltage is higher or lower than the set threshold voltage, the control means controls the second. Since the first charge pump circuit is driven, when the power supply voltage is higher than the set threshold voltage, the second charge pump circuit consisting of a P-channel MOS transistor operates, preventing electron injection into the substrate and causing malfunction. If the power supply voltage is lower than the set threshold voltage, the N-channel MO3! - The first charge pump circuit consisting of a transistor is activated and sufficient substrate voltage is supplied.

〔Example〕

FIG. 1 is a wiring diagram of an embodiment of the substrate voltage generating circuit of the present invention.

Referring to FIG. 1, ring oscillator 1 and driver 2
A detection means 23 is provided for detecting whether the power supply voltage vcc of each becomes H.

Control means 24 includes a transmission gate 24a that is turned on when the outputs φ and φ1 of the detection means 23 are H, respectively, and a transmission gate 24b that is turned on when the outputs φ and φ1 are H and L, respectively. are provided, and via one transmission gate 24a, a capacitor C and an N-channel MO8FET Q, Q or Oa are connected.
A first charge pump circuit 25 consisting of la 2a is connected to the driver 2, and is connected to the capacitors Cob and P via the other transmission gate 24b.
A second charge pump circuit 26 consisting of a channel MO3FET QQ is connected to the driver 2, and the output terminals of both charge pump circuits 25,26 are connected to a common substrate voltage output terminal 27 of the substrate voltage vBB.

By the way, the detection means 23 is configured, for example, as shown in FIG.
, Q, C7 and each FET6 Q -07 resistance value greater than the sum of the resistance 2
The φ1 output terminal is connected to the node N1 connecting the FETC 7 and the resistor 28 via a series circuit of two inverters 29 and 30, and the φ1 output terminal is connected to the node N1 via the inverter 29. Output terminal is connected.

Here, the threshold voltages of each FETQ, C6, and C7 in FIG. 2 are vTA, vlB, and ■, respectively. Then, Vc
If c≦(vTA+VTB+vTc), each F
Since ETQ, Q, and C7 are turned off, the voltage at node 6 Nl becomes Ov, and Vcc〉(vTA + vTB+
■If To), each FETQ5. Since Q6°C7 is turned on, the voltage at node N1 is (Vcc(vTA+
vTB+vTC month (!: t,; le.

Therefore, the voltage of this node N, "CC" T^+ V
The power supply voltage V when TB + V rc)l is equal to the input threshold voltage of the inverter 29. 0 is the set threshold voltage v8 of the detection means 23, which is the power supply voltage V. 0 is higher than this set threshold voltage Vs, the outputs φ and φ1 are H and L, respectively, and when it is lower, the outputs φ and φ1 are
Each becomes H.

■ For example, set the input threshold voltage of the inverter 29 to Vcc/
2.VTA””VrB-Vrc””
0,9 V, ■cc-(vTA+vTB
+vTc)-vco/2 is Vs, which gives Vs-5, 4V, and when V > 5.4V, φ and φ1 become CCI H and L, respectively, and V < 5.4V (7 ) when φ,
φl becomes H for each CC1.

When the power supply voltage V is higher than the set threshold voltage Vs, the outputs φ and φ1 of the detection means 23 become H and L, respectively, and the transmission gates 24a and 24
b are turned off and on, respectively, and the second charge pump circuit 2
6 is the drive signal φ which is the output of the driver 2. is entered,
The second charge pump circuit 26 operates.

On the other hand, when the power supply voltage ■ is CC lower than the set threshold voltage v8, the outputs φ and φ of the detection means 23 become H, respectively, and the transmission gate 24a,
24b are turned on and off, respectively, and the drive signal φ, which is the output of the driver 2, is sent to the first charge pump circuit 25 via the transmission gate 24a which is in the on state. is input, and the first charge pump circuit 25 operates.

Therefore, when V cc > V s, the second charge bomb lb' 2b circuit 26 consisting of the P-channel MO8FET Q Q operates, so that electron injection into the substrate does not occur as in the substrate voltage generation circuit with the NMO3 configuration. For example, in a dynamic RAM, stored information in a memory cell portion is not destroyed by electron injection, and malfunctions can be prevented.

On the other hand, when V cc < V s, N channel M
Since the first charge pump la 2a circuit 25 consisting of O3FETs Q and Q operates, a sufficient substrate voltage vBB can be supplied, and the power supply voltage V. Even if 0 is quite low, P
As in a substrate voltage generation circuit with a MOS structure, undershoot of the input signal causes destruction of stored information in the memory cell section of a dynamic RAM caused by electrons injected into the substrate, deterioration of resistance to latch-up, or damage to the relationship between the diffusion layer and the substrate. Deterioration in circuit operating speed due to an increase in junction capacitance can be suppressed.

FIG. 3 is a wiring diagram of the detection means 23' in another embodiment, in which a timer circuit is provided that utilizes the operation of a transistor amplifier circuit 31 consisting of capacitors C and C2 and N-channel MOSFETs Q and Q9.

Now, when the power supply voltage Vcc is higher than the set threshold voltage Vs, FETQ-Q7 is turned on and the node N1 becomes H, and the output φ1 becomes H through the two inverters and the Nandt gate 32, and the output φ1 becomes H through the inverter 33. Output φ1 is L
Therefore, P-channel MO8FETQ1o is inverter 2
It is turned on by the L output of 9, and the N-channel MO3FETQ
11 is off, the capacitor C is charged by turning on the FET Qlo, and the node N2 becomes H, the input of the inverter 34 becomes H, and its output becomes L.

Next, when the power supply voltage Vcc changes to a value lower than the set threshold voltage Vs, FETs Q5 to Q7 are turned off, the node N becomes L, and the output of the inverter 29 becomes H.
Since the output of the inverter 34 remains at L, the output φ1 remains at H1 and φ1 remains at L.

At this time, since the output of the inverter 29 is H as described above, one input of the ant game 35 is connected to the inverter 29.
9 becomes H, and the output level of the AND gate 35 is the drive signal φ to the other input. Determined by

Then, when the drive signal φ changes from voltage 0 to Vp, the voltage at node N rises from 0 to Vp due to capacitive coupling by capacitor CI, but FETQ turns on and the threshold voltage of FETQ8 becomes V. Then node N
The voltage of 3 drops to V by turning on FET Tl (8 Q).

8 Tl (8 Next, when the drive signal φ falls from the voltage Vp to 0, the voltage at the node N changes from the aforementioned V to (VTII83
TH8■), and at this time FETQ8 turns off, but FETQ9 turns on, so capacitor C2 is discharged through the gate of FETQ, the voltage at node N2 drops, and the voltage at node N2 is immediately turned off. The same operation is repeated again by increasing the signal φ from voltage 0 to ■.

By repeating the above operations, node N2
The voltage gradually changes from H to L, and in response to this change, the output of the inverter 34 changes from L to H, the output of the Nandt gate 32 changes from H to L, and φl changes from L to L. H■ stings.

Furthermore, when the power supply voltage fluctuates to a value higher than the set threshold voltage V8, FET Q """ Q7 is turned on and the output of the inverter 29 becomes L, and the outputs φ and φ1 are output through the Nandt gate 32. immediately change to H and L, respectively.

That is, when the power supply voltage V changes from a state lower than the set threshold voltage v8C to a state higher than the set threshold voltage v8C, the output φ
, φ is the power supply voltage V. The power supply voltage V changes quickly depending on the change in V. 0 is the set threshold voltage Vs
When changing from a higher state to a lower state, the voltage at the node N2 does not immediately change from H to L due to the operation of the charge pump circuit 31, but it takes some time, and the outputs φ and φ1 change during this time. Change■ will be delayed.

Therefore, by using the detection means 23' having the configuration shown in FIG.
．． 26 can be prevented from fluctuating in a short period of time, and the operation of the substrate voltage generation circuit can be stabilized.

FIG. 4 is a wiring diagram of still another embodiment of the present invention,
What is different from Fig. 1 is the transmission gate 24.
AND gates 36a and 36b constituting the control means 36 are provided in place of the charge pump circuits 25 and 24b.
．． 26 is switched by both AND gates 36a and 36b.

By the way, the output of the driver 2 is input to one input of both the AND gates 36a and 36b, and the AND gate 36H
The output φ1 of the detection means 23 is input to the other input of
The output φ1 of the detection means 23 is input to the other input of the AND gate 36b.

In this way, by the operation of the AND gates 35a and 36b, the power supply voltage V is increased as in the case of FIG. Both charge pumps 25 and 26 can be operated depending on whether 0 is low or high.

Next, FIG. 5 shows an embodiment in which two ring oscillators and two drivers are provided.
-G and Gb are inserted respectively, and both ring oscillators l
Detection means 23 for detecting G and G5 of a and lb, respectively.
Output φ1. φ1, and the output pulses of ring oscillators la and lb are set to dry/< 2 a
.

2b, and both charge pump circuits 25 and 26 are driven by drive signals from drivers 2a and 2b, respectively.

At this time, both charge pumps 2 (Nando game) G and Gb
This corresponds to the control means that drives the 5.26.

When the power supply voltage V is higher than the set threshold voltage Vs, the outputs φ and φ1 of the detection circuit 23 each become H, and only the ring oscillator 1b operates and the second charge pump circuit 26 When the power supply voltage V is lower than the set threshold voltage v8, the outputs φ and φ1 of the detection circuit 23 become H and L, respectively, and only the ring oscillator 1a operates and the first charge pump circuit 25 is activated. The same effect as in the case of FIG. 1 can be obtained.

It goes without saying that the detection means 23 in FIGS. 4 and 5 may be replaced by the detection means 23' having the configuration shown in FIG.

Further, in the above embodiments, the case of a P-type substrate has been described, but the present invention can be implemented in the same way even if the substrate is an N-type. In this case, the substrate voltage generation circuit is configured to generate a positive voltage. Become.

〔Effect of the invention〕

As described above, according to the present invention, when the power supply voltage is higher or lower than the set threshold voltage, the control means controls the second. By driving the first charge pump circuit, it is possible to prevent malfunctions caused by injection of electrons into the substrate when the power supply voltage is higher than the set threshold voltage, and when the power supply voltage is lower than the set threshold voltage. voltage can be supplied, stable operation can be obtained, and dynamic R
It is extremely effective as a substrate voltage generation circuit in semiconductor devices such as AM.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram of one embodiment of the substrate voltage generation circuit of the present invention, FIG. 2 is a partial wiring diagram of FIG. 1, FIG. 3 is a partial wiring diagram of another embodiment, and FIG. 5 and 5 are connection diagrams of other different embodiments, FIG. 6 is a connection diagram of a conventional substrate voltage generation circuit, FIG. 7 is a connection diagram of a part of FIG. 6, and FIG. 8 is a connection diagram of a conventional substrate voltage generation circuit. 9 is a waveform diagram of each signal for explaining the operation of FIG. 6, FIG. 10 is a wiring diagram of another conventional substrate voltage generation circuit, and FIG. 11 is a sectional view of FIG. 10. be. In the figure, 1+ la, lb are ring oscillators,
2.2a, 2b are drivers, 5 is positive power supply, 23.23'
is a detection means, 24.36 is a control means, and 25.26 is a first . A second charge pump circuit, 27 is a substrate voltage output terminal, C, C are capacitors, Oa Ob Q, Q are N-channel MOSFETs, Qlb. Ia 2a Q is P channel MO5FETSG, Gb is 2b

It is a gate. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A substrate voltage generation circuit that generates a voltage applied to a substrate constituting a semiconductor device, which includes an oscillator that generates periodic pulses, a driver that receives the periodic pulses as input and outputs a drive signal, and receives the drive signal as input. a first charge pump circuit consisting of a first capacitor and an N-channel MOS transistor; a second charge pump circuit receiving the drive signal and consisting of a second capacitor and a P-channel MOS transistor; and connected to the output terminals of both charge pump circuits. a detection means for detecting whether the power supply voltage of the oscillator and driver is higher or lower than the set threshold voltage; A substrate voltage generation circuit comprising control means for driving the second and first charge pump circuits when the voltage is high and when the voltage is low, respectively.