JP3092257B2 - BiCMOS circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS circuit, and more particularly to a BiC circuit suitable for a semiconductor integrated circuit used at a low power supply voltage.
It relates to a MOS circuit.

[0002]

2. Description of the Related Art The basic principle of a BiCMOS circuit is described in "Section 2.8 Bi-CMOS Circuit" on pages 24 to 37 of "Design of CMOS Ultra LSI, Baifukan, 1989". ing. The BiCMOS circuit is a circuit using both a bipolar transistor and a MOS transistor, and has the characteristics of the high speed and large current driving capability of the bipolar transistor and the features of high integration and low power consumption of the MOS transistor. FIG. 2 shows a basic circuit of the BiCMOS inverter. In the following, a plurality of types of BiCM
Since the OS circuit is handled, the circuit of FIG. 2 is hereinafter referred to as a conventional BiCMOS circuit. 201 and 202 are NPN type bipolar transistors. 203 is a P-channel MOS transistor (hereinafter abbreviated as PMOS). Reference numeral 204 denotes an N-channel MOS transistor (hereinafter abbreviated as NMOS). 211 is an input signal,
212 is an output signal.

A bipolar transistor 201 has three terminals: a base, a collector, and an emitter (indicated by B, C, and E in the figure, respectively).
04 is a gate, a source, and a drain (G,
S, D).

[0004] The use of the symbols and phrases in the present application relating to the potential will be summarized here. The power supply is a positive power supply, and its potential is set to V _CC . The potential V _CC is also called a potential H (high). On the other hand, the potential 0 is referred to as a potential L (low). Also 0.5
A high potential in a broad sense that is _{equal to} or higher than V _CC is referred to as high in the present application. Similarly, a low potential in a broad sense of 0.5 V _CC or less is referred to as low in this application.

In the BiCMOS circuit shown in FIG.
1 = Potential H, PMOS 203 is OFF, NM
The OS 204 is ON. Therefore, then the output signal 2
If the potential of the transistor 12 is higher than the potential L, a current flows between the source and the drain of the NMOS 204, and a current of h _FE times the current flows between the collector and the emitter of the bipolar transistor 202 due to the operation of the bipolar transistor 202. Drive signal 212 low.

When input signal 211 = potential L, PMO
S203 is ON, and NMOS 204 is OFF. Therefore, if the potential of the output signal 212 is
If the current is lower, the current flows between the source and the drain of the PMOS 203, and the current of h _FE times the current flows between the collector and the emitter of the bipolar transistor 201 by the action of the bipolar transistor 201. Drive.

Since h _FE is about 100 as a typical numerical example, the driving current of this bipolar transistor is MO
It is much larger than the drive current of the S transistors 203 and 204. As shown here, the BiCMOS circuit is a CMO
It is distributed in the S circuit and is excellent in load driving capability.

[0008] Another document, "IEE International Electron Devices Meeting, 1989, pp. 429-432"
(1989 IEEE International Electron Devices Meetin
g, pp. 429-432, 1989) show circuit diagrams of three types of BiCMOS inverters.
The signal delay time of the OS circuit is shown in a graph. The three types of BiCMOS circuits are conventional BiC
MOS circuit, CBiCMOS circuit, BiNMOS circuit. According to the graph of the delay time shown in the literature, when the power supply voltage is in the range of 4 to 5 V, the delay times of the three types of BiCMOS circuits are all at the same level and are smaller than the delay times of the CMOS circuit. However, it can be seen that the delay time of the conventional BiCMOS circuit rapidly increases in the range of the power supply voltage of 2.5 to 3 V, and becomes slower than that of the CMOS circuit at 2.5 V. On the other hand, CBiCMO
It can also be seen that the delay time of the S circuit and the BiNMOS circuit is smaller than the delay time of the CMOS circuit even in the range of 2.5-3V.

As shown in this document, when the power supply voltage becomes lower than 5 V, which is the standard value of the current logic integrated circuit, to a value of about 3 V, the conventional BiCMOS circuit becomes a CM.
It is not suitable for low voltage applications because it tends to lose its advantage over OS circuits. It is considered that a CBiCMOS circuit and a BiNMOS circuit are suitable for a low voltage application of about 3V.

[0010] Another document "IEE Custom Integrated Circuit Conference, 1991, pp. 123-124" (19)
91 IEEE Custom Integrated Circuits Conference, p
pp. 123-142, 1989) show that CBiC
A new BiCMOS circuit (QC-BiCMOS circuit) that operates faster than a MOS circuit and a BiNMOS circuit is described. The QC-
FIG. 8 shows a circuit diagram of a BiCMOS inverter circuit.
In FIG. 8, the input signal is 811 and the output signal is 81
2. Figure 8 shows a pull-up that drives the output high.
It comprises an NPN bipolar transistor 801, a pull-down NPN bipolar transistor 802 for driving the output low, PMOSs 803 and 805, an NMOS 804, and load elements (resistors or similar elements) 806 and 807. According to the article, bipolar transistor 80
2 and the PMOS 805, the QC-
It is stated that the BiCMOS circuit operates at high speed even with a low power supply voltage of about 3V.

[0011]

The circuits considered to be suitable for the conventional low power supply voltage operation are CBiCMOS circuits and B
It is an iNMOS circuit or a QC-BiCMOS circuit. Of these, the CBiCMOS circuit is an NPN bipolar
Both transistors and PNP bipolar transistors are required. This fact is a conventional BiCMO
As compared with the case where the S circuit requires only NPN bipolar transistors, there is a disadvantage that the manufacturing process becomes complicated and the manufacturing process cost increases.

In a conventional BiCMOS circuit, driving to both high and low is performed by a bipolar transistor, whereas in a BiNMOS circuit, driving of an output potential to low is performed by a MOS transistor. MOS transistors are more disadvantageous than bipolar transistors, particularly in terms of current driving capability, and their performance deteriorates greatly under use conditions where the load capacity is particularly large. This fact can be explained by considering the increase rate of the delay time with respect to the increase of the load capacitance in FIG. 12 of the literature of the IEEE International Electron Devices Meeting, which shows that the increase rate of the BiNMOS circuit is as follows. Conventional BiCMOS circuit, CB
This is also suggested from the fact that the rate is larger than the increase rate of the iCMOS circuit. Another disadvantage of the BiNMOS circuit is that BiNM
In the OS circuit, when the NMOS is connected in series like a NAND gate, the driving current to the row is reduced accordingly.

Further, the QC-BiCMOS circuit has a disadvantage that high-speed operation cannot be obtained depending on the potential condition during operation. Specifically, when the output value simply transitions from high to low, from low to high, or from a value close to an intermediate value to high, the QC-BiCMOS circuit operates at high speed. However, when driving from a value close to the intermediate value to low, the operation is not fast. The reason is that when the output value is close to the intermediate value, the driving current of the PMOS 805 in FIG. 8 is extremely small, and as a result, the current for driving the output signal 812 low by the bipolar transistor 802 is insufficient.

Accordingly, it is an object of the present invention to operate at a low power supply voltage, which is sufficiently faster than a conventional BiCMOS circuit, and eliminates the need for a PNP bipolar transistor required for realizing a conventional CBiCMOS circuit. It is an object to provide a logic circuit.

Another object of the present invention is to provide a conventional BiNMOS.
It is an object of the present invention to provide a logic circuit which does not have a drawback that a delay time when a load capacity is increased and a delay time when an NMOS is connected in series like a NAND is large as seen in a circuit.

Another object of the present invention is to provide a conventional QC-BiC
An object of the present invention is to provide a logic circuit which does not have a drawback that the operation is not fast when the output value is driven from a value close to the intermediate value to low as seen in the MOS circuit.

[0017]

SUMMARY OF THE INVENTION In order to achieve the objects set forth above, the novel BiCMOS circuit disclosed herein has a first NPN bipolar transistor driving the output high, and driving the output low. A second NPN bipolar transistor, a P-channel MOS transistor driving the base of the second NPN bipolar transistor high, and an N-channel MOS transistor driving the base of the second NPN bipolar transistor high. It is characterized by.

FIG. 1 shows a basic circuit diagram of a BiCMOS inverter according to the present invention. Note that a practical BiCMOS
Many of the circuits are provided with a circuit for discharging the base charge of the bipolar transistor, but FIG. 1 is an explanatory diagram and the base discharge circuit is omitted for clarity. In FIG. 1, the input signal is 111 and the output signal is 112
It is. FIG. 1 shows an NPN bipolar transistor 101 driving the output high, and an NPN driving the output low.
There are a bipolar transistor 102, an NMOS 104 and a PMOS 105 which control the current of a path connecting the base of the bipolar transistor 102 and the output signal 112. There is also a PMOS 103 for driving the base of the bipolar transistor 101 high. 106
Denotes an inverter, which outputs a logically inverted value of the input signal 111 to the signal line 113. Most simply, the inverter 106 can be realized by two MOS transistors. PMOS10
3. The gate of the NMOS 104 is controlled by the input signal 111, and the gate of the PMOS 105 is controlled by the signal 113 having the opposite polarity to the input signal.

[0019]

The present invention shows that the circuit operates at high speed even with a low power supply voltage of about 3V. For this purpose, the operation speed of each of the inverter of FIG. 1 and the inverter of FIG. 2 is analyzed.

FIG. 3 shows a conventional inverter of FIG.
This is a circuit in which the load capacitance 301 is connected to the final output 313 in a stage connection. 201A-204A, 201B-204B
Is the same as 201-204. At this time, the most problematic at the time of low power supply voltage operation is that the signal delay time of the second-stage inverter when the input 311 changes from the potential H to the potential L, that is, the signal transmission time at 312 and the signal transmission time at 313 Is the difference. Assume that the load capacity is 20 times greater than the input capacity of the inverter. The main part of the delay time is the time required to discharge the charge of the capacitor 301 from the potential H to the potential L. The time is inversely proportional to the drive current of the second-stage inverter. Discuss.

V _CC (power supply voltage) = 3.0 V, V _BE (base-emitter voltage of a bipolar transistor) = 0.8 V, V _TN (NMOS threshold voltage) = 0.6 V, V _TP (PMOS threshold voltage) = − 0.6 V, and the channel width of the NMOS 204B is 10 μm.

Considering the operation at that time in sequence: Operation 1: A signal is transmitted to the signal line 312 in response to the change of the input 311 from the potential H to the potential L,
Reference numeral 2 indicates a potential H of the potential V _CC -V _BE due to a drop in the V _BE voltage of the bipolar transistor 201A.

Operation 2: Therefore, NMOS 204B is ON
State. The gate of the NMOS 204B at that time (312)
The potential of the potential V _CC -V _BE, and the source (314), V _BE due to the voltage drop of the bipolar transistor 202B
It has become.

Operation 3: The output potential 313 immediately before being driven low is V _CC -V _BE . At that time, the output potential 3
13 is driven low by adding the current between the drain and source of the NMOS 204B to the bipolar transistor 202B.
_Is multiplied by the current amplification factor _hFE . NMOS 204B
Operates in the saturation region, so the drive current i is

[0025]

(Equation 1)

Here, β _{N is} a parameter proportional to the drive current per unit channel length of the NMOS, W _{N is} the channel width of the NMOS 204B, and V _{GS is} the gate-source voltage of the MOS transistor. V _CC = 3.0 V, V _BE = 0.8 V, V _TN = 0.
Substituting 6V, W _N = 10 into Equation 1

[0027]

I = 0.5 · h _FE · β _N · 10 (3.0-1.6-0.6) ² = A 3.2 h _FE β _N.

On the other hand, FIG. 4 shows a circuit similar to FIG. 3, which uses the inverter of FIG. 1 instead of the inverter of FIG. 101A-106A, 101B-106B are 10
It is the same as 1-106. The load capacity 401 is the same as the load capacity 301. The signal delay time of the second-stage inverter when the input 411 changes from the potential H to the potential L in the circuit of FIG. Note that N
The channel width of both the MOS 104B and the PMOS 105B is 5 μm.

Considering the operation at that time in sequence: Operation 1: A signal is transmitted to the signal line 412,
Because of the _{V BE} voltage drop of the bipolar transistor 101A, it has become potential V _CC -V _BE.

Operation 2: The signal 415 has the potential 0 due to the operation of the inverter 106B. Operation 3: The NMOS 104B is turned on. At this time, the potential of the gate (412) of the NMOS 104B is V _CC -V
The potential of _BE and the potential of the source (414) are set to V _BE due to the voltage drop of the bipolar transistor 102B.

Operation 4: The PMOS 105B is turned on. At this time, the potential of the gate (415) of the PMOS 105B is 0, and the potential of the source (413) is V _CC -V _BE because of the output potential immediately before being driven low.

At this time, the current for driving the output potential 413 to low is equal to the sum of the current flowing between the drain and source of the NMOS 104B and the current flowing between the drain and source of the PMOS 105B.
_Is multiplied by the current amplification factor _hFE . NMOS 104B
Operates in a saturation region and the PMOS 105B operates in a non-saturation region.

[0033]

(Equation 3)

Here, β _N : a parameter proportional to the drive current per unit channel length of the NMOS, β _P : a parameter proportional to the drive current per unit channel length of the PMOS, W _N : the channel width of the NMOS 104B, W _P : The channel width of the PMOS 105B, V _DS : a drain-source voltage of the MOS transistor. Assume that the relationship between β _P and β _N is β _P = 0.6β _N. This relational expression and V _CC = 3.0V, V _BE = 0.8V, V
_TN = 0.6 V, | V _TP | = 0.6 V, W _N = 5, W _P = 5
Is substituted into Equation 3.

[0035]

I = 2.5 · h _FE · β _N · (3.0-1.6-0.6) ² + 2.5 · h _FE · 0.6β _N · (3.0-1.6) · (3.0-1.2) ≒ (1.6 + 3.8) h _FE β _N = 5.4 h _FE β _N. Comparison of Equations 2 and 4 revealed that the inverter of FIG. 1 can exhibit about 1.7 times the current driving capability as compared with the inverter of FIG.

Focusing on the drive current in the analysis example of FIG.
Is dominant, that is, by the PMOS 105B, but the NMOS 104B is also required. The reason will be described.

Although the output potential 413 at the start of the operation is assumed to be V _CC -V _BE in the example of FIG. 4, it is also considered that the output potential 413 is lower than V _CC -V _BE in an application example in an actual logic system. There must be. For example, NAND and NOR
When multiple inputs of multi-input logic change at the same time, a logic hazard (short-time pulse) may occur, in which case the ability to quickly drive from a value close to the intermediate value to high or low is required. It is.

For various values of the output potential Vout,
FIG. 5 shows the current at which the NMOS 104 and the PMOS 105 of the same channel width drive the pull-down bipolar transistor (V _CC = 3.0 V, V _BE = 0.8).
V). In the region of Vout> 1.8V, P operates in the linear region.
MOS is advantageous, but in the region of 0.8V <Vout <1.8V, the driving current of the PMOS operating in the linear region is weak, and the NMOS operating in the saturation region is advantageous. If it becomes necessary to drive low at the output potential of this region,
The drive current by the PMOS is not always sufficient. Therefore, it is necessary to add an NMOS in an application example where a logic hazard can occur.

As described above, it has been shown that the circuit shown in the present invention operates stably at high speed even at a low voltage of about 3V.

The circuit of the present invention is a conventional CBiCMOS
Since the PNP bipolar transistor is not used unlike the circuit, the process cost for producing the PNP bipolar transistor does not increase. Also, since the circuit of the present invention is both driven high and low by bipolar transistors, M
The driving current can be increased as compared with the driving by the OS transistor, and the driving current when the NMOS is connected in series unlike the NAND gate does not decrease.

[0041]

FIG. 6 shows a BiCMOS inverter using the present invention. While the circuit of FIG. 1 is a circuit for explanation, the circuit of FIG. 6 is a practical circuit, and the power supply voltage V _CC indicated by a circle is set to a voltage lower than 5 volts, for example, 3 volts. I have. By setting the power supply voltage V _CC to a voltage lower than 5 volts as described above, the power consumption of the circuit can be reduced, and the MOS transistors 603 to 611 can be used for miniaturized devices having a gate length of 0.5 μm or less. It can be used, and the integration density of the semiconductor integrated circuit can be improved. The circuit of the embodiment of FIG. 6 is different from the circuit of FIG. 1 in that a base transistor discharging circuit of a bipolar transistor (hereinafter simply abbreviated as bipolar in the embodiment) is provided, A difference is that a circuit for making a full swing is provided.

The input signal of the inverter is 621 and the output signal is 622. Reference numerals 601 and 602 denote bipolars for driving the output signal 622 high and low, respectively. 603
Is P for driving the base of bipolar 601 high.
MOS. Reference numeral 604 denotes an NMOS for driving the base of the bipolar 602 to high. Similarly, 605 is a PMO for driving the base of the bipolar 602 high.
S.

The MOS circuit (603, PMOS 606, N
MOS 607, 608) basically function as an inverter, drive the bipolar 601 and set the input = potential H
Has the function of discharging the base charge of the bipolar 601 at the time,
It also has a function of controlling the gate potentials of the MOSs 605 and 611. The PMOS 609 whose gate is grounded and the NMOS 610 whose gate is supplied with the power supply voltage V _CC are always ON.
In this state, it is a MOS as a resistor for finally driving the output signal 622 to the full potential H or the full potential L. The NMOS 611 is for discharging the base charge of the bipolar 602.

The operation of the circuit shown in FIG. 6 when the input signal changes from the potential L to the potential H will be described below. Note that the output signal 622 at the start of the operation is high. Operation 1: By the MOS circuits 603, 606, 607, 608, the signal line 623 = low (| V _TP |), the signal line 624
= Potential L (ground potential).

Operation 2: 625 = potential H (power supply voltage V _CC ) by the MOS circuit (605, 611).

Operation 3: Bipolar 601 is turned off, bipolar 602 is turned on, and bipolar 6 is turned on.
02 drives output 622 low to V _BE .

Operation 4: The output 622 is driven to a complete potential L lower than V _BE via the MOS (610, 608).

Operation 5: After the driving is completed, the base charge of the bipolar 602 is discharged to the negative power supply via the MOS (604, 610, 608).

The operation of the circuit of FIG. 6 when the input signal changes from the potential H to the potential L will be described below. Note that the output signal 622 at the start of the operation is low. Operation 1: MOS circuit (603, 606, 607, 60
8), the signal line 623 = potential H and the signal line 624 = high (VCC-V _TN ).

Operation 2: 625 = potential L by the MOS circuit (605, 611).

Operation 3: Bipolar 601 is ON
The bipolar 602 is turned off, and the bipolar 60
1 drives output 622 high to V _CC -V _BE .

Operation 4: The output 622 is driven to a full potential H higher than V _CC -V _BE via the MOS (609, 603).

Based on the concept of the present invention, various gates other than the inverter that can be realized by input NAND, NOR gates, and other CMOS gates can be implemented.

FIG. 7 shows an embodiment of a two-input NAND using the present invention. 701 and 702 are NPN bipolar, 70
3, 704, 707, 708, 712 are PMOS, 70
5, 706, 709, 710, 711, 713, 714
Is an NMOS, 721 and 722 are input signals, and 723 is an output signal. The operation of the circuit of FIG. 7 is completely the same as that of the circuit of FIG. 6 except that only a function of performing a logical operation of an input signal is added, and thus the description is omitted.

[0055]

According to the present invention, even at a low voltage of about 3 V, the operation speed is sufficiently higher than that of the conventional BiCMOS circuit, and the circuit operates stably with respect to a logic hazard. In other words, the output value is driven from an intermediate value to a low value. In this case, a BiCMOS circuit operating at high speed can be obtained. Specifically, the transistor 105 operates at a high speed at a low power supply voltage due to the presence of the PMOS 105, and can be driven to a low speed at a high speed even in an intermediate value range of about 1-2 V due to the presence of the NMOS 104.

The circuit of the present invention is a conventional CBiCMOS
Since a PNP bipolar transistor is not used unlike a circuit, there is no increase in cost for producing a PNP bipolar transistor. Also, since the circuit of the present invention both drives the output high and low by bipolar transistors, the MO
The driving current can be increased as compared with the driving by the S transistor, and the driving current does not decrease because the NMOS is connected in series like the NAND gate.

[Brief description of the drawings]

FIG. 1 is a basic circuit of a BiCMOS inverter of the present invention.

FIG. 2 is a basic circuit of a conventional conventional BiCMOS inverter.

FIG. 3 is a circuit for analyzing the operation speed of a conventional BiCMOS inverter.

FIG. 4 is a circuit for analyzing the operating speed of the BiCMOS inverter of the present invention.

FIG. 5 shows how the output potential Vout changes. The drive current of the pull-down side bipolar drive MOS is PMOS, NMO
It is the figure shown about each of S.

FIG. 6 is a circuit diagram of a BiCMOS inverter according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of a BiCMOS 2-input NAND according to an embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional BiCMOS (QC-BiCMOS) inverter.

[Explanation of symbols]

101, 102... NPN bipolar transistors, 1
03, 105: PMOS, 104: NMOS, 106 ...
Inverter, 111 ... input signal, 112 ... output signal, 1
13: internal signal of circuit, 201, 202: NPN bipolar transistor, 203: PMOS, 204: NM
OS, 211 ... input signal, 212 ... output signal, 301 ...
Capacitor, 311 input signal, 313 output signal, 3
12, 314: internal signal of the circuit, 401: capacitor,
411 input signal, 413 output signal, 412, 41
4, 415... Circuit internal signals, 601, 602.
Bipolar transistors, 603, 605, 606,
609 ... PMOS, 604, 607, 608, 610,
611 NMOS, 621 input signal, 622 output signal, 623, 624, 625 internal circuit signal, 70
1, 702... NPN bipolar transistor, 70
3, 704, 707, 708, 712 ... PMOS, 70
5, 706, 709, 710, 711, 713, 714
... NMOS, 721, 722, input signal, 723, output signal, 801, 802, NPN bipolar transistor, 803, 805, PMOS, 804, NMOS, 8
06, 807: load, 811: input signal, 812: output signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/08

Claims (4)

(57) [Claims] A first NPN bipolar transistor having a collector-emitter path connected between a first operating potential point and an output for driving the output to a high potential; and an output and a second operating potential point. A second NPN bipolar transistor whose collector-emitter path is connected to drive the output to a low potential; a gate of which is responsive to an input signal and whose drain output is the base of the first NPN bipolar transistor. And a second P-channel MOS transistor whose gate is responsive to a signal opposite in phase to the input signal and whose drain output drives the base of the second NPN bipolar transistor. Wherein the gate is responsive to a signal in phase with the input signal and has a source output Wherein the semiconductor circuit further comprises an N-channel MOS transistor for driving the base of the second NPN bipolar transistor. 2. The semiconductor circuit according to claim 1, wherein said input signal is obtained from an output of a CMOS inverter responsive to said input signal. 3. An operating voltage between the first operating potential point and the second operating potential point is set to a value smaller than 5V. Semiconductor circuit. 4. The semiconductor circuit according to claim 1, wherein said input signal is directly applied to a gate of said N-channel MOS transistor.