JP3008426B2 - BiCMOS gate circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS gate circuit, and more particularly to a BiCMOS gate circuit capable of achieving both characteristics of high load driving capability and low power consumption even at a low voltage operation.

[Conventional technology]

Recently, a BiCMOS gate circuit, which is a composite circuit that takes advantage of both the low power consumption of CMOS circuits and the high current driving capability of bipolar transistors, has been developed and put into practical use. In this circuit, logic is performed by CMOS circuits. The load is driven by bipolar transistors. FIG. 3 is a circuit diagram of a conventional two-input NANAD gate. In the figure, P11 and P12 are P-channel MOSFETs, N11, N12, N13, N14, N15
Is an N-channel MOSFET, Q11 and Q12 are NPN bipolar transistors, 1 and 2 are two input terminals, 3 is an output terminal,
Is a high-potential power supply, and 5 is a low-potential power supply.

Next, the operation of the conventional circuit will be described. Two input terminals 1, 2
When a low level signal is applied to at least one of the transistors, at least one of the P-channel MOSFETs P11 and P12 is turned on to charge the base of the NPN bipolar transistor Q11. I do.
At this time, since at least one of the N-channel MOSFETs N13 and N14 is in the off state, it does not affect the operation state of Q11. Also, N-channel MOSFETs N11 and N12
At least one is in the off state, and N channel
Since the MOSFET N15 is turned on, the base of the NPN bipolar transistor Q12 is discharged and turned off. When a high level signal is applied to both of the two input terminals, both N-channel MOSFETs N11 and N12 are turned on, charging the base of the NPN bipolar transistor Q12 and turning on Q12 to speed up the load. Discharge. At this time, the P-channel MOSFETs P11 and P12 are both off, and the N-channel MOSFETs N13 and N14 are both on, so that the base of the NPN bipolar transistor Q11 is discharged and turned off. Has become.

[Problems to be solved by the invention]

However, the conventional BiCMOS gate circuit described above is
Since the miniaturization by scaling is performed to improve the performance of the SFET, when the gate length becomes less than Hercomicron, the power supply voltage has to be reduced due to various reliability problems. Now, N channel MOSF
Looking at ETN12, the lease terminal is connected to the base terminal of the bipolar transistor Q12. Therefore, when the base of Q12 is charged with N12, the base potential, that is, the source potential of N12 increases, and the gate-source potential of N12 decreases. Therefore, there is a disadvantage that the drain current of N12 becomes small and Q12 cannot be turned on at high speed, and the operating speed is deteriorated. This effect becomes more pronounced as the power supply voltage is lowered.For example, when the gate voltage of N12 is 3.0 V, for example, the base current of a bipolar transistor usually rises to about 1.0 V, and the drain current becomes less than half. The speed is greatly reduced.

[Means for Solving the Problems] In the BiCMOS gate circuit of the present invention, a base electrode of an NPN bipolar transistor and a base electrode of a PNP bipolar transistor are connected to an output of a CMOS logic circuit having first and second input terminals. The NPN-type bipolar transistor emitter electrode and the PNP-type bipolar transistor emitter electrode are connected in common to form an output terminal;
A BiCMOS gate circuit in which the collector electrode of the P-type bipolar transistor is connected to a high-potential power supply, and the collector electrode of the PNP-type bipolar transistor is connected to a low-potential power supply, and is connected in parallel between the high-potential power supply and the output terminal. First and second P-channel MOSFETs are connected, and first and second P-channel MOSFETs are connected in series between the low potential power supply and the output terminal.
N-channel MOSFET is connected to the first P-channel MOSFET.
A gate electrode of a MOSFET and a gate electrode of the first N-channel MOSFET are connected to the first input terminal, and a gate electrode of the second P-channel MOSFET and a gate electrode of the second N-channel MOSFET are connected to the first input terminal. 2 input terminal,
When the output terminal is at L level, the first and second P
The channel MOSFET is turned off, the first and second N-channel MOSFETs are turned on, and when the output terminal is at the H level, at least one of the first and second P-channel MOSFETs is turned on; At least one of the first and second N-channel MOSFETs is turned off.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a technique related to the present invention. First
In the figure, P1 and P2 are P-channel MOSFETs, N1 and N2 are N-channel MOSFETs, Q1 is an NPN-type bipolar transistor, and Q2 is a P-channel MOSFET.
NP-type bipolar transistors, 1, 2 are input terminals, 3 is an output terminal, 4 is a high-potential power supply, and 5 is a low-potential power supply. When a low-level signal is applied to at least one of the two input terminals, at least one of the P-channel MOSFETs P P1 and P2 is turned on, charging the base of the NPN bipolar transistor Q1, turning on Q1 and loading the load. Charge fast. At this time, at least one of the N-channel MOSFETs N1 and N2 is in an off state, and the base-emitter of the PNP bipolar transistor Q2 is in a reverse-biased state. There is no. When a high level signal is applied to both of the two input terminals, the N-channel MOSFETs N1 and N2 are turned on, and the PNP
The base of the bipolar transistor Q2 is discharged, and Q2 is turned on to rapidly discharge the load. At this time, both the P-channel MOSFETs P1 and P2 are off, and the base-emitter of the NPN bipolar transistor Q1 is in a reverse-biased state. Absent.

An example of a specific transistor size in FIG.
When the high-potential power supply voltage is 3.3 V, the low-potential power supply voltage is 0 V, and the load capacitance is 1.0 pF, the MOSFET has a gate oxide film thickness of 100 A, a channel length of 0.5 μm, a channel width of 20 μm, and a bipolar transistor emitter. Is 0.8 μm × 10 μm.
For high-speed operation, it is desirable to minimize the drain capacitance of the MOSFET and the capacitance around the base of the bipolar transistor as much as possible.

Next, an embodiment of the present invention will be described with reference to the circuit diagram of FIG. The circuit is an example of a two-input NAND gate. P1, P2, P3, P
4 is a P-channel MOSFET, N1, N2, N3 and N4 are N-channel MOSFETs
T and Q1 are NPN bipolar transistors, Q2 is a PNP bipolar transistor, 1, 2 are input terminals, 3 is an output terminal,
4 is a high-potential power supply and 5 is a low-potential power supply. In the second embodiment, P-channel MOSFETs P3 and P4 are connected in parallel with an NPN-type bipolar transistor Q1, and N-channel MOSFETs N3 and N4
Are connected in parallel with the PNP bipolar transistor Q2, and there is an advantage that the output potential swings completely from the low potential power supply voltage to the high potential power supply voltage.

[Effect of the Invention] As described above, according to the present invention, since the drain electrode of the MOSFET is connected to the base electrode of the bipolar transistor, a large voltage is always applied between the gate and the source of the MOSFET, and the present invention operates even when the power supply voltage is lowered. There is an effect that the speed does not rapidly deteriorate. For example, if the threshold voltage of the MOSFET is set to 0.5 V, it is practically impossible to use a power supply voltage of 3.0 V or less in the conventional BiCMOS gate circuit, but the Bi of the present invention
CMOS gate circuits can use up to about 2.0V.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a technique related to the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional BiCMOS gate circuit. P1, P2, P3, P4, P11, P12 …… P-channel MOSFET, N1, N2, N3,
N4, N11, N12, N13, N14, N15 …… N-channel MOSFET.Q1, Q11,
Q12: NPN-type bipolar transistor, Q2: PNP-type bipolar transistor, 1, 2 ... Input terminal, 3 ... Output terminal, 4 ... High-potential power supply, 5 ... Low-potential power supply.

Claims (1)

(57) [Claims] An output of a CMOS logic circuit having first and second input terminals is connected to a base electrode of an NPN-type bipolar transistor and a base electrode of a PNP-type bipolar transistor. An emitter terminal of the NPN type bipolar transistor is commonly connected to serve as an output terminal, and a collector electrode of the NPN type bipolar transistor is connected to a high potential power source, and the PNP
A BiCMOS gate circuit having a collector electrode of a bipolar transistor connected to a low-potential power supply, wherein first and second P-channel MOSFETs connected in parallel between the high-potential power supply and the output terminal are connected; First and second N-channel MOSFETs connected in parallel between a power supply and the output terminal
Are connected, the gate electrode of the first P-channel MOSFET and the gate electrode of the first N-channel MOSFET are connected to the first input terminal, and the gate electrode of the second P-channel MOSFET and the second The gate electrode of the N-channel MOSFET is connected to the second input terminal, and when the output terminal is at the L level, the first and second P-channel MOSFETs are off, and the first and second N-channel MOSFETs are turned off. When the channel MOSFET is turned on and the output terminal is at the H level, at least one of the first and second P-channel MOSFETs is turned on, and at least one of the first and second N-channel MOSFETs is turned on. A BiCMOS gate circuit which is turned off.