JP2757632B2 - Test signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generating circuit, and more particularly to a test signal generating circuit for generating a test signal when testing a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional example of such a test signal generating circuit.

In FIG. 3, a test signal generating circuit has a low transconductance having a source connected to a power supply voltage level and a gate connected to a ground level.
A channel-type MOS transistor 7, an N-channel MOS transistor 8 having a source connected to the input terminal 1 and the gate of the input buffer 2, a gate connected to the ground level, and the P-channel MOS transistor 7 connected to the drain And the two transistors 7, 8
, And an inverter 10 which supplies an output signal as a test signal 11 to an internal circuit.

During normal operation, a voltage between the ground level and the power supply voltage level is applied to the input terminal 1. In this case, the P-channel type MOS transistor 7 is conductive,
Since the N-channel MOS transistor 8 is turned off and the potential of the contact 9 is always at the “high” level,
The output signal of the inverter 10, that is, the test signal 11, does not become active.

During a test operation, the input terminal 1 is connected to GND-V
By applying a voltage equal to or lower than _TN (threshold voltage of the N-type transistor 8), the N-channel MOS transistor 8 can be made conductive. P-channel type MO
Since the transconductance of the S transistor 7 is set sufficiently smaller than that of the N-channel MOS transistor 8, the potential of the contact 9 becomes lower than the threshold voltage of the inverter 10, and the output signal 11 of the inverter 10 becomes active.

The relationship between the voltage at the input terminal 1 and the power supply voltage when the output signal 11 becomes active is shown by a dotted line in FIG.

[0007]

In the above-described conventional test signal generation circuit, the P-channel MOS transistor 7 is of the enhancement type, and the source is connected to V _DD and the gate is connected to GND. The voltage level required to enter the test state (hereinafter referred to as a test level) greatly depends on the power supply voltage. Therefore, when the power supply voltage is high, the absolute value of the test level becomes large,
In a process of a miniaturized semiconductor integrated circuit, the circuit is destroyed in a test state. In addition, when the power supply voltage is low, the absolute value of the test level becomes small, and the test state is easily entered, which causes a runaway during normal operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a novel test signal generating circuit which can eliminate the above-mentioned disadvantages inherent in the prior art. To provide.

[0009]

In order to achieve the above object, a test signal generating circuit according to the present invention comprises a depletion P-channel MOS transistor having a source and a gate connected to a power supply voltage level, and a source having an input circuit. An N-channel transistor whose gate is connected to the ground level and whose depletion P-channel MOS transistor and drain are connected to each other; an internal circuit which uses the drains of both transistors as inputs and outputs signals as test signals. Or a depletion N-channel MOS transistor having a source and a gate connected to the ground level, a source connected to the input terminal of the input circuit, and a gate connected to the power supply voltage level. The depression N And P-channel type MOS transistor Yan'neru type MOS transistor and a drain each other are connected, the configured a buffer supplied to the internal circuit output signal as input drains of the transistors as the test signal.

[0010]

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a test signal generating circuit according to the present invention.

Referring to FIG. 1, an input signal from an input terminal 1 is connected to an input buffer 2 and to a source of an N-channel MOS transistor 4.
The gate of the N-channel MOS transistor 4 is GND
Connected to the level. The V _DD level is connected to the source and gate of the depletion P-channel MOS transistor 3. The drains of the depletion P-channel MOS transistor 3 and the N-channel MOS transistor are connected, and the output of the contact 9 is connected to the inverter 10.

An output signal 11 of the inverter 10 is supplied as a test signal, and an output signal of the input buffer 2 is supplied to an internal gate of the semiconductor integrated circuit as an input signal for normal operation.

Next, the operation of the first embodiment will be described.

(1). During Normal Operation During normal operation, a voltage between the GND level and the _VDD level is applied to the input terminal 1. In this case, the depletion P-channel MOS transistor 3 becomes conductive, the N-channel MOS transistor 4 becomes non-conductive,
Since the potential of the contact 9 is always at the "high" level, the output signal of the inverter 10, that is, the test signal 11 is not activated. Therefore, during normal operation, normal operation can be performed without being taken into the test state, and since the output signal of the input buffer 2 is taken into the internal circuit as a normal input signal.

(2). During test operation By applying a voltage equal to or lower than GND-V _TN (threshold voltage of N-type transistor 4) to input terminal 1,
The N-channel MOS transistor 4 can be made conductive. When the V _DD level is applied to the gate of the depletion P-channel MOS transistor 3, the transconductance of the N-channel MOS transistor 4 is set to be sufficiently higher than the transconductance of this transistor. Inverter 1
0 is lower than the threshold voltage, and inverter 1
The output signal 11 of "0" becomes "high" level (active state).

The relationship between the voltage at the input terminal 1 and the power supply voltage when the output signal 11 is in the active state is shown by a solid line in FIG.

FIG. 2 is a circuit diagram showing a second embodiment of the test signal generating circuit according to the present invention.

The input signal from the input terminal 1 is connected to the input buffer 2 and to the source of the P-channel MOS transistor 6. P-channel type MO
The gate of the S transistor 6 is connected to the V _DD level. The drains of the depletion N-channel MOS transistor 5 and the P-channel MOS transistor are connected, and the output of the contact 9 is connected to the buffer 12.

The output signal 11 of the buffer 12 is supplied as a test signal, and the output signal of the input buffer 2 is supplied to the internal gate of the semiconductor integrated circuit as an input signal for normal operation.

Next, the operation of the second embodiment will be described.

(1). During Normal Operation During normal operation, a voltage between the GND level and the _VDD level is applied to the input terminal 1. In this case, the depletion N-channel MOS transistor 5 becomes conductive, the P-channel MOS transistor 6 becomes non-conductive,
Since the potential of the contact 9 is always at the "low" level, the output signal of the buffer 12, that is, the test signal 11 is not activated. Therefore, during normal operation, normal operation can be performed without being brought into the test state, and since the output signal of the input buffer 2 is taken into the internal circuit as a normal input signal.

(2). At the time of test operation By applying a voltage equal to or higher than V _DD + | V _TP | (threshold voltage of the P-channel transistor 6) to the input terminal 1, the P-channel MOS transistor 6 can be made conductive. Depletion N-channel type MO
When the GND level is applied to the gate of the S transistor 5, the transconductance of the P-channel MOS transistor 6 is set sufficiently higher than the transconductance of this transistor. And the output signal 11 of the buffer 12 becomes "high" level (active state).

[0024]

As described above, according to the present invention,
The test signal generating circuit is composed of an enhancement type MOS transistor and a depletion type MOS transistor, and the source and the gate of the depletion type MOS transistor are set to the same potential, so that the test level depends on the power supply voltage as shown by the solid line in FIG. Decrease.
Therefore, even when the power supply voltage is high, the absolute value of the test level does not increase, so that the test state can be drawn without breaking the circuit. Since the size does not decrease, an effect is obtained that it is difficult to enter the test state during normal operation.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a test signal generation circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the test signal generation circuit according to the present invention.

FIG. 3 is a circuit of a conventional example.

FIG. 4 is a characteristic diagram of the circuits shown in FIGS. 1 and 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Input buffer 3 ... Depletion P-channel type MOS transistor 4 ... Enhancement N-channel type MOS transistor 5 ... Depletion N-channel type MOS transistor 6 ... Enhancement P-channel type MOS transistor 7 ... Enhancement P-channel type with small mutual conductance MOS transistor 8 ... Enhancement N-channel type MOS transistor 9 ... Contact 10 ... Inverter 11 ... Test signal 12 ... Buffer 13 ... Characteristics of the present invention shown in FIG. 1 14 ... Characteristics of the conventional example shown in FIG.

Claims (2)

(57) [Claims] A depletion p-channel MOS transistor having a source and a gate connected to a power supply voltage level; a source connected to an input terminal of an input circuit; a gate connected to a ground level; A test signal generation circuit comprising: an N-channel MOS transistor having a drain connected to each other; and an inverter having a drain as an input and an output signal supplied to an internal circuit as a test signal. A depletion N-channel MOS transistor having a source and a gate connected to a ground level; a source connected to an input terminal of an input circuit; a gate connected to a power supply voltage level; and a P-channel type MOS transistor having a drain each other are connected, the inputs the drains of the transistors, the test signal generating circuit is characterized by having a buffer supplied to the internal circuit of the output signal as the test signal.