JPH05157813A - Test signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce the source voltage dependency of the voltage level necessary for entering the test condition by constituting a test signal generating circuit of a depression P channel type MOS transistor and an enhancement N channel type MOS transistor, and connecting the source and the gate of the depression P channel type MOS transistor to the source voltage dependency. CONSTITUTION:An input terminal 1 is connected to an input buffer and a source of N channel type MOS transistor 4, and its gate is earthed. The source and the gate of a depression P channel type MOS transistor 3 are connected to the power source. Drains of the transistors 3, 4 are connected to each other, a contact 9 is connected to an inverter 10, and the output is used as a test signal. During the test operation, the voltage below the threshold value of the transistor 4 is applied to the terminal 1, realizing an energized condition. The voltage of the contact 9 is lowered in comparison with the mutual conductance of the transistors 3, 4, and the output of an inverter 10 reaches the 'high' level, leading to the active condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generating circuit, and more particularly to a test signal generating circuit for generating a test signal when testing a CMOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional example of this type of test signal generating circuit.

In FIG. 3, this test signal generating circuit has a source connected to a power supply voltage level and a gate connected to a ground level, and has a small mutual conductance P.
A channel type MOS transistor 7 and an N channel type MOS transistor 8 whose source is connected to the input terminal 1 and the gate of the input buffer 2 and whose gate is connected to the ground level and whose P channel type MOS transistor 7 and its drain are connected to each other. And both transistors 7 and 8
And an inverter 10 which supplies the output signal as a test signal 11 to the internal circuit.

During normal operation, a voltage between the ground level and the power supply voltage level is applied to the input terminal 1. In this case, the P-channel MOS transistor 7 is in the conductive state,
Since the N-channel MOS transistor 8 becomes non-conductive and the potential of the contact 9 is always at "high" level,
The output signal of the inverter 10, that is, the test signal 11 is not in the active state.

At the time of test operation, the GND-V is applied to the input terminal 1.
By applying a voltage equal to or lower than _TN (threshold voltage of the N-type transistor 8), the N-channel MOS transistor 8 can be rendered conductive. P channel type MO
Since the transconductance of the S transistor 7 is set sufficiently smaller than that of the N-channel MOS transistor 8, the potential of the contact 9 becomes lower than the threshold voltage of the inverter 10, and the output signal 11 of the inverter 10 becomes active.

The relationship between the voltage of the input terminal 1 and the power supply voltage when the output signal 11 is in the active state is shown by the dotted line in FIG.

[0007]

In the conventional test signal generating circuit described above, the P-channel type MOS transistor 7 is an enhancement type, the source is connected to V _DD , and the gate is connected to GND. The voltage level required to enter the test state (hereinafter referred to as the test level) largely depends on the power supply voltage. Therefore, when the power supply voltage is high, the absolute value of the test level becomes large,
In a more miniaturized semiconductor integrated circuit process, the circuit is broken during a test state. Further, when the power supply voltage is low, the absolute value of the test level is small, and it is easy to enter the test state, so that there is a drawback that runaway during normal operation is caused.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel test signal generating circuit capable of solving the above-mentioned drawbacks inherent in the conventional technology. To provide.

[0009]

To achieve the above object, a test signal generating circuit according to the present invention is a depletion P-channel type MOS transistor having a source and a gate connected to a power supply voltage level, and a source having an input circuit. Of the depletion P-channel type MOS transistor connected to the ground level and the depletion P-channel type MOS transistor and the drains thereof are connected to each other, and the drains of the both transistors are input and the output signal is used as a test signal for an internal circuit. Or a depletion N-channel type MOS transistor having a source and a gate connected to the ground level, a source connected to the input terminal of the input circuit and a gate connected to the power supply voltage level. The depletion N And P-channel type MOS transistor Yan'neru type MOS transistor and a drain each other are connected, the configured a buffer supplied to the internal circuit output signal as input drains of the transistors as the test signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a circuit configuration diagram showing a first embodiment of a test signal generating circuit according to the present invention.

Referring to FIG. 1, the input signal from the input terminal 1 is connected to the input buffer 2 and the source of the N-channel type MOS transistor 4.
The gate of the N-channel MOS transistor 4 is GND
Connected to the level. The V _DD level is connected to the source and gate of the depletion P-channel type MOS transistor 3. The drains of the depletion P-channel MOS transistor 3 and the N-channel MOS transistor are connected to each other, and the output of the contact 9 is connected to the inverter 10.

The output signal 11 of the inverter 10 is supplied as a test signal, and the output signal of the input buffer 2 is supplied as an input signal for normal operation to the internal gate of the semiconductor integrated circuit.

Next, the operation of the first embodiment will be described.

(1). During normal operation During normal operation, a voltage between the GND level and the V _DD level is applied to the input terminal 1. In this case, the depletion P-channel MOS transistor 3 is conductive and the N-channel MOS transistor 4 is non-conductive.
Since the potential of the contact 9 is always at "high" level, the output signal of the inverter 10, that is, the test signal 11 does not become active. Therefore, during a normal operation, the output signal of the input buffer 2 is taken into the internal circuit as a normal input signal without being pulled into the test state, so that the normal operation can be performed.

(2). At the time of test operation By applying a voltage of GND-V _TN (threshold voltage of N-type transistor 4) or less to the input terminal 1,
The N-channel type MOS transistor 4 can be made conductive. When the V _DD level is applied to the gate of the depletion P-channel type MOS transistor 3, the mutual conductance of the N-channel type MOS transistor 4 is set sufficiently larger than the mutual conductance of this transistor, so that the potential of the contact 9 is Inverter 1
It becomes lower than the threshold voltage of 0, and the inverter 1
The output signal 11 of 0 becomes "high" level (active state).

The relationship between the voltage at the input terminal 1 and the power supply voltage when the output signal 11 is in the active state is shown by the solid line in FIG.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the test signal generating circuit according to the present invention.

The input signal from the input terminal 1 is connected to the input buffer 2 and the source of the P-channel type MOS transistor 6. P channel type MO
The gate of the S transistor 6 is connected to the V _DD level. The drains of the depletion N-channel type MOS transistor 5 and the P-channel type MOS transistor are connected to each other, and the output of the contact 9 is connected to the buffer 12.

The output signal 11 of the buffer 12 is supplied as a test signal, and the output signal of the input buffer 2 is supplied as an input signal for normal operation to the internal gate of the semiconductor integrated circuit.

Next, the operation of the second embodiment will be described.

(1). During normal operation During normal operation, a voltage between the GND level and the V _DD level is applied to the input terminal 1. In this case, the depletion N-channel MOS transistor 5 is conductive and the P-channel MOS transistor 6 is non-conductive.
Since the potential of the contact 9 is always at "low" level, the output signal of the buffer 12, that is, the test signal 11 does not become active. Therefore, during a normal operation, the output signal of the input buffer 2 is taken into the internal circuit as a normal input signal without being pulled into the test state, so that the normal operation can be performed.

(2). During the test operation, the P-channel MOS transistor 6 can be rendered conductive by applying a voltage equal to or higher than V _DD + | V _TP | (threshold voltage of the P-channel transistor 6) to the input terminal 1. Depletion N-channel MO
When the GND level is applied to the gate of the S-transistor 5, the transconductance of the P-channel MOS transistor 6 is set to be sufficiently larger than the transconductance of this transistor, so that the potential of the contact 9 is the threshold of the buffer 12. The output voltage 11 of the buffer 12 becomes "high" level (active state).

[0024]

As described above, according to the present invention,
By configuring the test signal generation circuit with enhancement type MOS transistors and depletion type MOS transistors and setting the source and gate of the depletion type MOS transistors to the same potential, as shown by the solid line in FIG. Is reduced.
Therefore, the absolute value of the test level does not become large even when the power supply voltage is high, so the circuit can be pulled into the test state without destroying the circuit. Since the size does not become small, it is difficult to enter the test state during normal operation.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a test signal generating circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the test signal generating circuit according to the present invention.

FIG. 3 is a circuit of a conventional example.

FIG. 4 is a characteristic diagram of the circuits shown in FIGS. 1 and 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Input buffer 3 ... Depletion P-channel type MOS transistor 4 ... Enhancement N-channel type MOS transistor 5 ... Depletion N-channel type MOS transistor 6 ... Enhancement P-channel type MOS transistor 7 ... Enhancement P-channel type with small mutual conductance MOS transistor 8 ... Enhancement N-channel MOS transistor 9 ... Contact 10 ... Inverter 11 ... Test signal 12 ... Buffer 13 ... Characteristics of the present invention shown in FIG. 1 ... Characteristics of conventional example shown in FIG.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H01L 27/092 7342-4M H01L 27/08 321 L

Claims (2)

[Claims] 1. In a CMOS type semiconductor integrated circuit, a depletion P-channel type MOS transistor having a source and a gate connected to a power supply voltage level, a source connected to an input terminal of an input circuit, and a gate connected to a ground level. The depletion P-channel type MOS transistor and an N-channel type MOS transistor having drains connected to each other; and an inverter which inputs the drains of the both transistors and supplies an output signal as a test signal to an internal circuit. Test signal generator circuit. 2. A CMOS type semiconductor integrated circuit comprising: a depletion N-channel type MOS transistor having a source and a gate connected to a ground level; a source connected to an input terminal of an input circuit; and a gate connected to a power supply voltage level. A test comprising: a depletion N-channel MOS transistor and a P-channel MOS transistor having drains connected to each other; and a buffer having the drains of both transistors as inputs and supplying an output signal as a test signal to an internal circuit. Signal generation circuit.