JPH06314964A - Semiconductor signal output circuit - Google Patents

Abstract

PURPOSE:To transmit a signal through the use of a same bus line from a semiconductor integrated circuit device operated by plural different power supply voltages in a CMOS semiconductor integrated circuit device. CONSTITUTION:The semiconductor signal output circuit is constituted of a Schottky diode 6 whose anode electrode connects to a power supply voltage 4, a PMOS transistor(TR) whose drain electrode connects to an output pad electrode 3, whose source electrode and base electrode are connected to a cathode electrode of the Schottky diode 6, and an N-channel MOS TR 8 whose drain electrode connects to the output pad electrode 3 and whose source electrode and base electrode are connected to a ground potential point 5, and a gate electrode of the P-channel MOS TR 7 and a gate electrode of the N- channel MOS TR 8 are controlled by a signal fed to a data signal input node 1 and an output enable signal input node 2. Through the constitution of the semiconductor signal output circuit above, even when a voltage higher than the power supply voltage is applied to the output pad electrode, flowing of a current to the semiconductor integrated circuit device is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit, and more particularly to a semiconductor signal output circuit for transmitting a signal between semiconductor devices operating at different power supply voltages.

[0002]

2. Description of the Related Art Conventionally, in a CMOS integrated circuit, a circuit for outputting a signal to the outside is directly connected to a ground potential and a P-type MOS transistor having a source electrode directly connected to the power supply potential as in the internal logic circuit. It is composed of a CMOS circuit in which an N-type MOS transistor having a formed source electrode is paired.

[0003]

However, when a CMOS type integrated circuit having a conventional signal output circuit is operated at a plurality of different power supply potentials and its output is signal-transmitted using a common bus line. Of the CMOS type integrated circuit operating at the high power supply voltage of the other, the CMOS operating at the other low power supply voltage
Type integrated circuit or CMOS without power supply voltage
Current flows through the parasitic diode formed in the output circuit of the integrated circuit, which not only increases power consumption, but also may cause malfunction or damage to the integrated circuit due to latch-up. .

In order to solve the above problems, an N-type MO
There is a method of forming a signal output circuit using only S transistors, but in this case, there is a problem that a sufficient amplitude voltage cannot be secured when the integrated circuit is operated at a low voltage.

[0005]

In order to solve the above problems, the present invention provides a P-type MOS transistor and an N-type MOS transistor.
A signal output circuit is constructed by inserting a rectifier element such as a Schottky diode having a small forward drop voltage between the transistor and the source electrode of the transistor and the power supply potential, or between the drain electrode and the output terminal electrode to the outside. did.

[0006]

By using the signal output circuit configured as described above, it is possible to operate CMOS integrated circuits operating at different power supply voltages safely and with low power consumption by using a common bus line. Becomes

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a tri-state signal output circuit according to the present invention.

In the figure, in the tri-state signal output circuit, the drain electrode is connected to the output pad electrode 3 and the source electrode and the substrate electrode are shot by a signal input to the data signal input node 1 and the output enable signal input node 2. The potential of the gate electrode and the drain electrode of the P-type MOS transistor 7 connected to the cathode electrode of the key diode 6 are connected to the output pad electrode 3, and the source electrode and the substrate electrode of the N-type MOS transistor 8 are connected to the ground potential 5. The potential of the gate electrode is controlled and the state of the output signal output to the output pad electrode 3 is controlled. The anode electrode of the Schottky diode 6 is connected to the power supply voltage potential 4.

Therefore, when there is no load, the output pad electrode 3
The amplitude voltage of the signal appearing at is expressed by VOUT = (VDD-VF) -VSS (Equation 1). In Expression 1, VOUT represents the amplitude voltage of the output signal, VDD represents the power supply voltage potential, VF represents the forward drop voltage of the diode, and VSS represents the ground voltage potential.

FIG. 2 shows a Schottky diode 6 and a P-type MOS formed on the P-type substrate in FIG.
6 is an example of a cross-sectional structure diagram of a transistor 7 and an N-type MOS transistor 8. FIG. FIG. 3 is a circuit diagram showing a second embodiment of the tri-state signal output circuit according to the present invention.

In the figure, the Schottky diode 6
Is connected in series with the drain electrode of the P-type MOS transistor 7, and the cathode electrode of the Schottky diode 6 is connected with the output pad electrode 3. The source electrode and the substrate electrode of the P-type MOS transistor 7 are connected to the power supply voltage potential 4.

The other elements have the same structure as that shown in FIG. 1, and finally the tristate signal output shown in FIG. 3 functions similarly to the circuit shown in FIG. Figure 4
FIG. 4 is an example of a sectional structural view of a Schottky diode 6, a P-type MOS transistor 7, and an N-type MOS transistor 8 formed on the P-type substrate in FIG. 3.

FIG. 5 is a circuit showing a third embodiment of the tri-state signal output circuit according to the present invention. In the tri-state signal output circuit in the same figure, in order to improve the high level output current characteristic of the tri-state signal output circuit in FIG. 1, the drain electrode is connected to the power supply voltage potential 4, and the source electrode is connected to the output pad electrode 3. This is a circuit to which an N-type MOS transistor 9 connected to the substrate electrode and connected to the ground potential 5 is added.

In these embodiments, the example of the semiconductor integrated circuit formed on the P-type substrate is shown, but the signal output circuit in the present invention is not limited to this, and a P-type MOS transistor and an N-type are provided. It relates to all signal output circuits composed of MOS transistors and rectifying elements such as Schottky diodes. The present invention is particularly suitable for a CMOS IC having a large logic amplitude.

[0015]

As described above, the present invention is a P-type M.
Between the source electrode of the OS transistor and the power supply voltage potential,
Alternatively, since the structure is such that it is inserted between the drain electrode of the P-type MOS transistor and the output pad electrode, even if a voltage higher than the power supply voltage potential is applied to the output pad electrode when the output has a high impedance, the current does not flow in. It has a preventive effect.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a circuit diagram of a first embodiment of a signal output circuit in the present invention.

FIG. 2 is a sectional structural view of a first embodiment of a signal output circuit according to the present invention.

FIG. 3 is an explanatory diagram showing a circuit diagram of a second embodiment of the signal output circuit in the present invention.

FIG. 4 is a sectional structural view of a second embodiment of the signal output circuit according to the present invention.

FIG. 5 is an explanatory diagram showing a circuit diagram of a third embodiment of the signal output circuit of the present invention.

[Explanation of symbols]

1 data signal input node 2 output enable signal input node 3 output pad electrode 4 power supply voltage potential 5 ground voltage potential 6 Schottky diode 7 P-type MOS transistor 8 N-type MOS transistor 9 N-type MOS transistor for improving high level output current 10 P Type substrate 11 P well 12 N well 13 Schottky junction 14 P ⁺ diffusion layer 15 N ⁺ diffusion layer 16 Schottky diode anode electrode 17 Schottky diode cathode electrode 18 N-type MOS transistor substrate electrode and source electrode 19 N Type MOS transistor drain electrode 20 P type MOS transistor drain electrode 21 P type MOS transistor substrate electrode and source electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H03K 19/0948 9170-4M H01L 27/08 321 L 8321-5J H03K 19/094 B

Claims (1)

[Claims] 1. A P-type MO in a CMOS integrated circuit
A push-pull type semiconductor signal output circuit comprising an S transistor, an N-type MOS transistor and a diode connected in series.