JPH098638A - Cmos input/output buffer circuit - Google Patents

Abstract

PURPOSE: To provide a CMOS input/output buffer circuit by which the semiconductor integrated circuits different in power supply voltages can be directly connected to each other. CONSTITUTION: The drain of a P type MOS transistor 3 is connected to the drain of an N type MOS transistor 2, further input circuits 4a and 4b of a CMOS are connected thereto to constitute this CMOS input/output buffer circuit as an input/output terminal 8. In this constitution, the anode of a diode 3 is connected to the source of a PMOS transistor 1, the cathode is connected to a power source VDD1, and the source of the NMOS transistor 2 is connected to a GND. Even when the power supply voltage of the opposite side connected to the terminal 8 is higher than its own power supply voltage, the current flowing through the source of the PMOS transistor 1 to the power source is avoided by a diode 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS input / output buffer circuit connected between semiconductor integrated circuits and operating with different power supply voltages.

[0002]

2. Description of the Related Art A conventional general CMOS input / output buffer circuit is shown in FIG. The input / output logic of the CMOS input / output buffer circuit of FIG. 4 is as follows. When the EN terminal is "0", the P-type MOS transistor 1 and the N-type MOS transistor 2 are both OFF, and the CMOS input / output buffer circuit is in the input state. At this time, a signal from another semiconductor integrated circuit applied to the input / output terminal 8 appears at the I terminal.

When the EN terminal is logic "1", the CMO
The S input / output buffer circuit enters the output state, and the signal at the D terminal is output to the input / output terminal 8. At this time, output High
The h level, that is, the potential of logic "1" is VDD of the power supply voltage.
It becomes 1. Further, the Low level, that is, the potential of the logic "0" becomes the GND level. The above operation is shown in the truth table of Table 1 below. The logical value "x" of the Y terminal and the I terminal when the EN terminal is logic "0" is the power supply voltage VDD1 of the CMOS input / output buffer circuit and the voltage VY applied to the Y terminal from another semiconductor integrated circuit. It is a value determined by the relationship with.

(Table 1) EN D Y I 0 0 x x 0 1 1 x x 1 0 0 0 1 1 1 1 1

FIG. 5 is a diagram for explaining the structure of the output transistor section 15 of FIG. An N well 12 and a P well 13 are formed on the surface of a P type semiconductor substrate, and a P type MOS transistor 1 and an N type MOS transistor 2 are formed therein.
Are formed. The N well contact 16 and the P well contact 17 are for applying a potential to the N well and the P well, respectively.

As a conventional example similar to the present invention in the technical field, the steady state current is reduced by controlling the input circuit section by the input signal of the enable terminal and the output circuit section.
No. 43, Japanese Patent Laid-Open No. 63-209219, which bidirectionally transfers data of a plurality of integrated circuits driven by different power supplies by using a voltage conversion circuit.

[0007]

However, in the above-mentioned conventional CMOS input / output buffer circuit, when connecting to a semiconductor integrated circuit having a different power supply voltage as shown in FIG. 3, the power supply voltage of the other party to be connected is higher than that of itself. Then, an excessive current i shown in FIGS. 4 and 5 flows from the partner input / output circuit from the partner side. For this reason, there is a drawback that direct connection is not possible. This phenomenon will be described below with reference to FIG. When a potential higher than the power supply VDD1 is applied to the input / output terminal 2, the input / output terminal 2
Through the drain 10 of the P-type MOS transistor to N
A current i flows from the well 12 through the N well contact 16 to the terminal side of the power supply voltage VDD1.

That is, when the relationship between the power supply voltage VDD1 and the voltage VY applied to the Y terminal is VDD1 ≧ VY, the current i does not flow and “x” in the truth table is x = VY. When VDD1 <VY, the current i flows and “x” in the truth table indicates the power supply voltage VDD1 and the applied voltage V to the Y terminal.
Y, output impedance of other semiconductor integrated circuit, P-type M
It is determined by each value such as the impedance of the drain 10 of the OS transistor. Generally, the impedance value of the drain 10 of the P-type MOS transistor is low, and VDD1 <
The value of the current i in the case of VY becomes an excessive value.

Since the current i flows into the CMOS input / output buffer circuit from the other side, a compensating circuit for preventing this is required. For the above reason, the CMOS input / output buffer circuits cannot be directly connected to each other, which complicates the circuit configuration of the device, and causes a problem of hindering cost reduction and size reduction.

It is an object of the present invention to provide a CMOS input / output buffer circuit which enables direct connection between semiconductor integrated circuits having different power supply voltages.

[0011]

In order to achieve the above object, a CMOS input / output buffer circuit of the present invention has a diode, a P-type MOS transistor and an N-type MOS transistor, and the cathode of the diode has a power source and an anode. P
P-type MOS connected to the source of the p-type MOS transistor
The drain of the transistor is connected to the drain of the N-type MOS transistor, the source of the N-type MOS transistor is connected to GND, and the gates of the P-type MOS transistor and the N-type MOS transistor are used as input terminals for the logic signal and connected. It is characterized in that the drain thus formed serves as an input / output terminal.

The N-type diffusion layer and the P-type diffusion layer in contact with the N-type diffusion layer are provided in the N-well forming the P-type MOS transistor, and the source and the N-type diffusion layer of the P-type MOS transistor are provided. It is preferable to have a structure in which the layer is electrically connected and the P-type diffusion layer is connected to a power source.

[0013]

Therefore, according to the CMOS input / output buffer circuit of the present invention, the cathode of the diode is connected to the power source, the anode is connected to the source of the P-type MOS transistor, and the drain of the P-type MOS transistor is connected to the drain of the N-type MOS transistor. The source of the N-type MOS transistor is connected to GND. In this connection configuration, P
The gates of the type MOS transistor and the N-type MOS transistor serve as input terminals for the logic signal, and the connected drains serve as input / output terminals. Therefore, even if the power supply voltage of the other side connected to the input terminal is higher than the power supply voltage of itself, the diode prevents the inflow of current.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CMO according to the present invention will now be described with reference to the accompanying drawings.
An embodiment of the S input / output buffer circuit will be described in detail. FIG.
2 and FIG. 2, there is shown an embodiment of the CMOS input / output buffer circuit of the present invention. FIG. 1 is a circuit configuration example of a CMOS input / output buffer circuit, and FIG. 2 is a diagram showing a partial structure example of the output transistor section 15 of FIG.

The CMOS input / output buffer circuit of FIG. 1 comprises an output transistor section 15 and an input / output buffer circuit section.

The output transistor section 15 is constructed by connecting a diode 3, a P-type MOS transistor 1 and an N-type MOS transistor 2 in series between the GND and the power supply voltage VDD1.

The input / output circuit section includes a NAND gate 5 whose output terminal is connected to the gate of the P-type MOS transistor 1.
A NOR gate 6 having an output terminal connected to the gate of the N-type MOS transistor 2 and three inverters 4a, 4b,
4c and.

The CMOS of this embodiment constructed as described above
When the EN terminal of the input / output buffer circuit is logic "0", both the P-type MOS transistor 1 and the N-type MOS transistor 2 are turned off. Therefore, CM in this state
The OS input / output buffer circuit enters the input state, and a signal from another semiconductor integrated circuit applied to the input / output terminal 8 appears at the I terminal.

When the EN terminal is logic "1",
This CMOS input / output buffer circuit is in the output state, and D
The terminal signal is output to the input / output terminal 8. At this time, the output High level is a voltage obtained by subtracting the forward voltage of the diode 3 from the power supply voltage VDD1, and the Low level is the GND level.

The above logical operation is the same as that of the conventional CMOS input / output buffer circuit shown in FIG. 4, and the truth table is basically the same as the truth table of the conventional CMOS input / output buffer circuit shown in Table 1. The behavior will be the same. However, the contents of the indefinite value "x" are different.

The CMOS input / output buffer circuit shown in FIG. 1 has, for example, the structure shown in FIG. In FIG. 2, an N well 12 and a P well 13 are formed on the surface of a P type semiconductor substrate, and a P type MOS transistor 1 and an N type MOS transistor 2 are formed therein. P-well contact 1
Reference numeral 7 is for applying a potential to the P well 13.
The N well contact 16 applies a potential to the N well 12, and at the same time forms the diode 3 together with the p ⁺⁺ diffusion layer 18. In addition, gates 9 and 9, drains 10 and 10, sources 11 and 1 of P-type and N-type MOS transistors
1 etc. are formed.

The characteristic feature of the CMOS input / output buffer circuit configured as described above is that the P-type M of the output transistor section 15 is used.
That is, the diode 3 is provided between the OS transistor 1 and the power supply. As a result, when the semiconductor integrated circuits 7, 7 having different power supply voltages as shown in FIG. 3 are connected to each other, the diode 3 is reversed even if the connected power supply voltage VDD2 is higher than the power supply voltage VDD1 of itself. It becomes a bias. Therefore, the inflow of current from the input / output circuit on the other side is blocked. Therefore, the excessive current i does not flow even when VDD1 <VY.

According to the CMOS input / output buffer circuit of the above-mentioned embodiment, it is possible to directly connect the semiconductor integrated circuits which operate with different power supply voltages, which simplifies the circuit, lowers the cost of the device and downsizes it. .

The above embodiment is a preferred embodiment of the present invention, but the present invention is not limited to this embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0025]

As described above, the CMOS of the present invention
In the input / output buffer circuit, the cathode of the diode is connected to the power source, the anode is connected to the source of the P-type MOS transistor, and the drain of the P-type MOS transistor is N-type MOS.
It is connected to the drain of the transistor and the source of the N-type MOS transistor is connected to GND. In this connection configuration, the gates of the P-type MOS transistor and the N-type MOS transistor are used as input terminals for logic signals, and the connected drains are used as input / output terminals. Even if the power supply voltage of the other side connected to this input terminal is higher than the power supply voltage of itself, the diode prevents the current from flowing into the power supply through the source of the P-type MOS transistor. Therefore, direct connection with a semiconductor integrated circuit that operates with different power supply voltages is possible, and the cost and size of the device can be easily reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a CMOS input / output buffer circuit of the present invention.

FIG. 2 is a diagram for explaining the structure of the CMOS input / output buffer circuit of FIG.

FIG. 3 is a block diagram for explaining an application form of a CMOS input / output buffer circuit.

FIG. 4 is a circuit diagram showing a configuration example of a conventional CMOS input / output buffer circuit.

5 is a diagram for explaining the structure of the CMOS input / output buffer circuit of FIG.

[Explanation of symbols]

1 P-type MOS transistor 2 N-type MOS transistor 3 Diode 4 Inverter 5 NAND gate 6 NOR gate 7 Semiconductor integrated circuit 8 Input / output terminal 9 MOS transistor gate 10 MOS transistor drain 11 MOS transistor source 12 N well 13 P well 15 Output transistor 16 N well contact 17 P well contact 18 p ⁺⁺ Diffusion layer

Claims (2)

[Claims] 1. A diode, a P-type MOS transistor, and an N-type MOS transistor, wherein a cathode of the diode is a power source and an anode of the diode is a P-type M transistor.
It is connected to the source of the OS transistor, and the drain of the P-type MOS transistor is the N-type MOS.
A drain of the transistor, a source of the N-type MOS transistor connected to GND, and gates of the P-type MOS transistor and the N-type MOS transistor serving as input terminals of a logic signal,
And a CMOS input / output buffer circuit in which the connected drain serves as an input / output terminal. 2. A source of the P-type MOS transistor and the N-type having an N-type diffusion layer and a P-type diffusion layer in contact with the N-type diffusion layer in an N-well forming the P-type MOS transistor. 2. The CMOS input / output buffer circuit according to claim 1, wherein the diffusion layer is electrically connected to the diffusion layer, and the P-type diffusion layer is connected to a power source.