WO2004075407A1

WO2004075407A1 - Input/output circuit

Info

Publication number: WO2004075407A1
Application number: PCT/JP2003/001812
Authority: WO
Inventors: Katsuhiko Senda; Kenji Hashimoto
Original assignee: Fujitsu Limited
Priority date: 2003-02-19
Filing date: 2003-02-19
Publication date: 2004-09-02

Abstract

An input/output circuit having a tolerance characteristic such that while the circuit device is off, even if a high voltage higher than the internal voltage is applied from outside, no high voltage is applied to A between the gate and drain of an NMOS transistor serving as an internal voltage transistor and hence the gate oxide film is not destroyed. The semiconductor input/output circuit is characterized by comprising a first PMOS transistor and a first NMOS transistor both connected between an internal power supply and GND, a second NMOS transistor inserted between the first PMOS transistor and the first NMOS transistor and having a gate connected to the internal power supply, a PAD terminal connected to the drain of the second NMOS transistor, a diode connected between the gate and drain of the second NMOS transistor, and a resistor connected between the gate of the second NMOS transistor and GND and used to control the current flowing through the diode.

Description

Description I / O circuit Technical field

The present invention relates to an input / output circuit of a semiconductor device, and more particularly to a technology of a tolerant circuit that copes with a high voltage applied to a low voltage chip. Background art

Figure 4 shows an example of a conventional general 5 V tolerant circuit. In this case, a 5 V tolerant circuit is a circuit whose output is 3.3 V but whose input can be received up to 5 V. In Figure 4, when the internal power supply VCC (3.3 V) is turned on, even if a voltage of 5 V is applied to the PAD pin from the outside, the voltage A between the gate and drain of the NMOS transistor Q 1 is Only a potential difference of 1.7 V (= 5 V-3.3 V) is applied. Therefore, even when the NMOS transistor Q1 has a withstand voltage of 3.3 V, it is possible to receive an external 5 V voltage without breaking the gate oxide film.

However, when the power of a circuit device having a built-in tolerant circuit as shown in FIG. 4 is turned off, the internal power supply V CC of the tolerant circuit is turned off. At that time, if a voltage of 5 V is externally applied to the PAD pin, a potential difference of 5 V is directly generated between the gate and drain A of the NMOS transistor Q 1, and the 3.3 V breakdown voltage NMOS transistor The gate oxide film of Q 1 is destroyed.

To avoid this, external high-voltage input must be prohibited when the power of the circuit device with the built-in tolerant circuit is turned off, or the NMOS transistor Therefore, it was necessary to configure the transistor Q 1 with an NMOS transistor with a withstand voltage higher than the external high voltage.

Note that a diode should be connected between the gate and drain A of the NMOS transistor Q1 to prevent the gate oxide film of the NMOS transistor from being damaged even when a positive surge voltage is applied to the PAD pin. There is also an example in which this can be done (for example, see Patent Document 1).

Patent Document 1

Japanese Patent Application Publication No. JP-A-2001-16601 discloses the invention

According to the present invention, even when a high voltage equal to or higher than the internal voltage is externally applied when the circuit device is turned off, a high voltage is not applied to the gate-drain A of the NMOS transistor Q1, which is an internal voltage transistor. It is another object of the present invention to provide an input / output circuit having a tolerant characteristic capable of protecting a gate oxide film from being destroyed. In order to prevent the NMOS transistor Q1 from being destroyed, a high voltage is not directly applied from the outside to the gate-drain A of the NMOS transistor Q1 even when the circuit device is turned off. It is effective to make the potential difference within the breakdown voltage range of transistor Q1.

In order to achieve the above object, in a semiconductor input / output circuit according to the present invention, a first PMOS transistor and a first NMOS transistor connected between an internal power supply and GND, and a first PMOS transistor A second NMOS transistor disposed between the first NMOS transistors and having a gate connected to the internal power supply, a pad terminal connected to a drain of the second NMOS transistor, and a second NMOS transistor A diode connected between the gate and drain of the transistor, and a gate connected between the gate of the second NMOS transistor and GND, and A resistor for controlling a current flowing through the diode. By controlling the current flowing through the diode using a resistor, the voltage drop caused by the diode prevents the second NMOS even if an external high voltage is applied to the PAD pin when the internal power supply is turned off. The structure is such that the transistor is not destroyed.

Further, in the semiconductor input / output circuit according to the present invention, when the output mode is set based on the enable signal, one of the first PMOS transistor and the first NMOS transistor is output so that data is output. Is on and the other is off,

When the input mode is entered based on the enable signal, the first PMOS transistor and the first NMOS transistor are turned off so that the signal input to the PAD terminal is input. Preferably, it is constructed.

Further, in the semiconductor input / output circuit according to the present invention, a third NMOS transistor in which a gate and a drain are connected to the internal power supply and a source is connected to the gate of the second NM'OS transistor It is preferred to have. This is to prevent the internal power supply line from rising when an external voltage is applied to the PAD pin, preventing the internal circuit from malfunctioning.

(The invention's effect)

According to the input / output circuit having a tolerant characteristic according to the present invention, when the internal power supply is turned off by turning off the circuit device, the NMOS transistor Q1 is broken even if a high voltage is applied from the outside. Can be prevented. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing an example of a semiconductor input / output circuit according to the present invention. FIG. 2 is a diagram showing another example of the semiconductor input / output circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of a semiconductor input / output circuit having 5 V tolerant characteristics.

FIG. 4 is a diagram showing a conventional tolerant circuit. Embodiment of the Invention

FIG. 1 shows an example of a semiconductor input / output circuit according to the present invention.

The semiconductor input / output circuit shown in FIG. 1 has NOR gates 1, 3, and NOR gate 3 to which the outputs of the inverters 1 and 2, the inverters 1 and 2 for inverting the enable signal EN and the data signal D, respectively, are input. And an NAND gate 5 to which the enable signal EN and the output of the inverter 2 are inputted, and an inverter 6 for inverting the output of the NAND gate 5. The source of the PMOS transistor Q4 is connected to the internal power supply VCC (3.3 V), the drain of the PMOS transistor Q4 is connected to the source of the PMOS transistor Q3, and the PMOS transistor Q3 The drain of NMOS transistor Q1 is connected to the drain of NMOS transistor Q1, the source of NMOS transistor Q1 is connected to the drain of NMOS transistor Q2, and the source of NMOS transistor Q2 is connected to GND. The PAD terminal is connected between the PMOS transistor Q3 and the NMOS transistor Q1. Further, the output of the inverter 4 is input to the gate of the PMOS transistor Q4, the output of the inverter 6 is input to the gate of the NMOS transistor Q2, and the gate of the PMOS transistor Q3 is connected to GND. Have been. Further, two comparators 7 and 8 are connected in series between the PAD terminal and the input terminal IN. Between the drain and the gate of the NMOS transistor Ql, there are four PSD-Nwe1 1 diodes D1 to D4 connected in series as shown in Fig. 1, and between the gate of the NMOS transistor Q1 and GND. Is connected to a current limiting resistor R1. Also, the current limiting resistor R 1 and the gate of the NMOS transistor Q 1 are connected to the internal power supply VCC.

Consider the case where the circuit device having the input / output circuit shown in Fig. 1 is powered on.

When the input / output circuit is in the output mode, the internal power supply V CC is 3.3 V and the enable signal EN is high. Here, when the data signal D is at a high level, the data signal D is inverted by the inverter 2 and input to the NOR gate 3 and the NAND data 5. NOR gate 3 and the output of NAND data 5 go high, respectively, and the outputs of inverters 4 and 6 go low, respectively, and input to the gates of PMOS transistor Q 4 and NMOS transistor Q 2. Then, the PMOS transistor Q4 is turned on and the NMOS transistor Q2 is turned off. The gate of the PMOS transistor Q3 is turned on because it is connected to GND, and the gate of the NMOS transistor Q1 is turned on because it is connected to the internal power supply VCC. Therefore, the same high-level signal as the data signal D is output to the PAD terminal.

When the data signal D is low, the data signal D is inverted by the inverter 2, so that the outputs of the NOR gate 3 and the NAND data 5 are respectively low and the outputs of the inverters 4 and 6 are high. Level, which is input to the gates of the PMOS transistor Q4 and the NMOS transistor Q2 to turn off the PMOS transistor Q4 and turn on the NMOS transistor Q2. . The gate of the PMOS transistor Q3 is turned on because it is connected to GND, and the gate of the NMOS transistor Q1 is turned on because it is connected to the internal power supply VCC. Therefore, a low-level signal opposite to the data signal D is output to the PAD terminal. Next, when the I / O circuit is in the input mode, the internal power supply VCC is 3.3 V and the enable signal EN is low. At this time, a low-level signal is output from the NOR gate 3 and a high-level signal is output from the NAND gate 5 irrespective of the data signal D, thereby turning off the PMOS transistor Q4 and the NMOS transistor Q2. You. Therefore, when a high-level signal is input to the PAD terminal, a high-level signal is input from the input terminal IN, and when a single-level signal is input to the PAD terminal, a single-level signal is input from the input terminal IN. It will be done.

As described above, when the power supply of the circuit device having the input / output circuit shown in FIG. 1 is turned on, the gate of the NMOS transistor Q1 can be operated even when a high voltage of 5 V is applied to the PAD terminal from the outside. Since the internal power supply VCC (3.3 V) is applied to the gate voltage, the potential difference between the gate and drain A of the NMOS transistor Q 1 is only 1.7 V (= 5 V-3.3 V). Not applied. Therefore, even when the NMOS transistor Q1 has a withstand voltage of 3.3 V, it is possible to receive an external 5 V voltage without destroying the gate oxide film.

Next, consider the case where the circuit device having the input / output circuit shown in FIG. 1 is turned off.

When the device circuit is turned off, VCC (3.3 V) is not applied to the gate of the NMOS transistor Q1. In this state, if a high voltage of 5 V is applied to the PAD pin from outside, a circuit is formed by the PAD pin, diodes D1 to D4, current control resistor Rl, and GND. The gate potential of the NMOS transistor Q1 is determined by the diodes D1 to D4 and the current limiting resistor R1. That is, a voltage drop corresponding to the operating voltage X4 of the diodes D1 to D4 can be expected. Therefore, by appropriately setting the current limiting resistor R 1, the potential difference between the gate and drain of the NMOS transistor Q 1 can be reduced from 5 V to the operating voltage X of the diodes D 1 to D 4. The potential difference is subtracted by 4.

In Fig. 1, four diodes were used in series, but this is only an example, and considering the external high voltage to be applied and the breakdown voltage of the NMOS transistor Q1, etc. The type and number can be determined as appropriate. That is, by properly selecting the type of diode and the number (1 to n) to be inserted, even if the NMOS transistor Q1 has a withstand voltage of 3.3 V, the gate oxide film is not destroyed and the external 5 V voltage from When used as a 5 V tolerant circuit, when a voltage of 5 V is externally applied to the PAD pin, the potential difference between the gate and drain of the NMOS transistor Q1 is reduced. It is preferable that the voltage be 1.7 V to 3.3 V.

Further, the current limiting resistor R 1 is particularly necessary for flowing a current for operating the diodes D 1 to D 4. If there is no current limiting resistor R1, no voltage drop due to diodes D1 to D4 will occur, so a high external 5V voltage is applied between the gate and drain of the NMOS transistor Q1 as it is. Would.

Thus, in the case of a semiconductor input / output circuit functioning as a 5 V tolerant circuit operating at 3.3 V of the internal power supply, the potential difference between the gate and drain A of the NMOS transistor Q1 is 1.7 V to 3 V. If the voltage is suppressed to about 3 V, the 3.3 V breakdown voltage NMOS transistor Q 1 is not broken. In order to obtain the effect, adjust the number of diodes (1-! 1) It is inserted between the gate and drain of the S transistor Ql, and is not directly connected to GND, but a current limiting resistor R1 is added to limit the flowing current.

In FIG. 1, two PMOS transistors Q 4 and Q 3 and two NMOS transistors Q 1 and Q 2 are connected in series between the internal power supply VCC and GND. It is also possible to insert a further PMOS transistor between S transistors Q 4 and Q 3. Further, if necessary, it is possible to insert an additional NMOS transistor between the NMOS transistors Q 1 and Q 2. The circuit configuration for switching the input / output circuit shown in FIG. 1 between the output mode and the input mode is merely an example, and various modifications are possible.

FIG. 2 shows another example of the semiconductor input / output circuit according to the present invention.

In FIG. 2, the circuit configuration for switching the input / output circuit between the output mode and the input mode is omitted, and the internal control signals C1 to C4 input to the NMOS transistor Q2, the PMOS transistor Q3, and the transistor Q4 are omitted. Shown as C 3.

The difference between the I / O circuit shown in Fig. 1 and the I / O circuit shown in Fig. 2 is that, in the I / O circuit shown in Fig. 2, an NMOS transistor Q5 is further added between the internal power supply VCC and the gate of the NMOS transistor Q1. This is the point provided. As shown in FIG. 2, the NMOS transistor Q5 has its gate and drain connected to the internal power supply VCC, and its source is the gate of the NMOS transistor Q1, the current control resistor R1 and the diode D1. Connected to connection point.

In the input / output circuit shown in Fig. 1, if a 5 V voltage is externally applied to the PAD pin when the circuit device is turned off, the line of the internal power supply VCC rises and the internal circuit may malfunction. There is. Therefore When the power supply of the circuit device is turned off, the gate of the NMOS transistor Q5 is closed, and the voltage rise of the internal power supply VCC is suppressed. When the power of the circuit device is turned on, the gate of the NMOS transistor Q5 is turned on, so that a voltage can be supplied from the NMOS transistor Q5. Therefore, the same circuit operation as that of FIG. 1 can be performed.

According to the input / output circuit example shown in FIG. 2, similarly to the circuit shown in FIG. 1, the power supply of a circuit device having a built-in input / output circuit having a tolerant function is turned off without using a high-voltage transistor. Even when a high voltage is externally applied to the PAD pin, the gate oxide film of the NMOS transistor Q1 can be prevented from being destroyed. In addition, in the input / output circuit example shown in Fig. 2, an additional NMOS transistor Q5 is provided between the internal power supply VCC and the gate of the NMOS transistor Q1, so that the internal circuit malfunctions when the circuit device is turned off. Can be prevented.

Fig. 3 shows the input of four PSD-Nwe 11 diodes with an operating voltage of 0.6 V and a 5 V tolerant input using a 30-Ω resistor as the current control resistor R 1. An example of an output circuit is shown. In Fig. 3, when a 5 V voltage is externally applied to the PAD pin when the circuit device is turned off, a voltage drop of 0.6 X 4 = 2.4 V occurs. Therefore, the potential difference between the gate and the drain A of the 3.3 V withstand voltage NMOS transistor Q 1 is 2.6 V (= 5 V−2.4 V), and the gate potential of the NMOS transistor Q 1 is Oxide film destruction was prevented.

Claims

1. In semiconductor I / O circuits with tolerant characteristics,

A first PMOS transistor and a first NMOS transistor connected between the internal power supply and GND;

The first PMO S transistor and the first NMO S transistor blue

And a second N connected to the internal power supply and having a gate connected thereto.

MOS transistors and

of

A PAD terminal connected to the drain of the second NMOS transistor;

A diode connected between the gate and the drain of the second NMOS transistor;

A semiconductor input / output circuit connected between a gate of the second NMOS transistor and GND, and having a resistor for controlling a current flowing through the diode.

2. When the output mode is set based on the enable signal, one of the first PMOS transistor and the first NMOS transistor is turned on so that data is output. And the other is turned off and enters the input mode based on the enable signal, so that the signal input to the PAD terminal is input to the first PMOS transistor and the first PMOS transistor. The semiconductor input / output circuit according to claim 1, wherein the NMOS transistor is turned off.

3. The diode is such that when a voltage is externally applied to the PAD terminal when the internal power supply is turned off, the voltage between the gate and the drain of the second NMOS transistor is maintained at a breakdown voltage or less. 3. The semiconductor input / output circuit according to claim 1, wherein a voltage drop occurs.

4. Further, a gate and a drain are connected to the internal power supply, 2. The semiconductor input / output circuit according to claim 1, further comprising a third NMOS transistor having a source connected to the gate of the second NMOS transistor.

5. The semiconductor input / output circuit according to claim 5, wherein the third NMOS transistor suppresses an increase in the internal power supply when a voltage is externally applied to the PAD terminal when the internal power supply is turned off.

6. The semiconductor input / output circuit according to claim 1, wherein the diode includes a plurality of diode elements.