JP2002314395A - Input-output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input-output buffer circuit which realizes a protection function against overvoltage from the outside without increasing the area of a semiconductor chip, is used by being mixed with a semiconductor integrated circuit that operates on voltage higher than that of the input-output buffer circuit itself and is applied to a semiconductor integrated circuit. SOLUTION: This input-output buffer circuit is provided with first and second PMOSs serially connected between a power supply and a pad, a third PMOS connected between the gate of the second PMOS and the pad, a plurality of diodes interconnected in series between the gate of the second PMOS and the power supply, and a first NMOS connected between the pad and a ground. The back gate of the first PMOS is connected to the power supply, the back gates of the second and third PMOS are connected to the pad, first and second signal lines are connected to the gates of the first and third PMOSs respectively, and a second signal line is connected to the gate of the first NMOS through an inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output buffer circuit applied to a semiconductor integrated circuit used in combination with a semiconductor integrated circuit (LSI) operating at a higher voltage than itself.

[0002]

2. Description of the Related Art Referring to specific examples shown in FIGS.
An input / output buffer circuit applied to a semiconductor integrated circuit operating at, for example, 3 V, which is used in combination with a semiconductor integrated circuit operating at a higher voltage than itself, for example, 5 V, will be described.

FIG. 2 is a circuit diagram showing an example of a conventional input protection circuit. The input protection circuit 52 shown in FIG.
An input protection circuit for a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 5-145088, comprising an input buffer 54, a resistance element (protection resistance) 56 connected between the input / output pad 18 and the input buffer 54, and , A diode 60 connected between the ground and the signal line N, and three diodes 58 connected in series between the signal line N and the power supply.

In this input protection circuit 52, a plurality of diodes 58 are connected in series in the forward direction between the signal line N and the power supply.
8, the voltage corresponding to the threshold voltage can be lowered for each stage. Therefore, even if an output signal of another semiconductor integrated circuit having a high power supply voltage is input, the voltage difference between the power supply and the input signal is reduced by each diode 58 Unless it exceeds the sum of the threshold voltages of
A large current does not flow constantly, and an input protection function can be provided.

However, the diode 5 used for overvoltage protection
8, in order to function sufficiently as a protection element,
The same size as the transistor constituting the final stage of the output circuit is required (for example, in the case of an input / output circuit operating with a power supply of 3 V, W / L (gate width / gate length) = 740 μm)
m / 0.5 μm). In the case of the input protection circuit 52, since a plurality of protection diodes 58 are required for each input terminal, when this is realized on a semiconductor chip, there is a problem that the chip area increases.

FIG. 3 is a circuit diagram showing an example of a conventional input / output buffer circuit. The input / output buffer circuit 62 shown in FIG. 1 is an input / output buffer of a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 7-183774 according to the present applicant, and comprises an input unit 12 and an output unit 14. I have.

First, an input section 12 includes an N-type MOS transistor (hereinafter referred to as an NMOS) 20 connected between a pad 18 and a signal line N4, and a P-type MOS transistor connected between a power supply and the signal line N4. MOS transistor (hereinafter, PMOS)
22), an inverter 24 connected between the signal lines N4 and N5, and an inverter 30 connected to the signal line N5.
It consists of.

Here, the gate of the NMOS 20 is connected to the power supply, and the gate of the PMOS 22 is connected to the signal line N5.

The inverter 24 is an input buffer and is a PMOS connected between a power supply and a signal line N5.
26 and an NM connected between the signal line N5 and the ground.
The gate is formed by the signal line N4.
It is connected to the.

On the other hand, the output section 14 includes two PMOSs 32 and 34 connected in series between the power supply and the pad 18 and a series connection between the pad 18 and the ground. Two NMOS3 connected
6, 38, two NMOSs 40, 42 connected in series between the signal lines N1, N3, the signal line N3 and the pad 18.
, The inverter 46 connected between the signal line D1 and the signal line N1, and the signal line D
2 and an inverter 48 connected between the signal line N2.

Here, the gate of the PMOS 32 is connected to the signal line N.
1, the gate of the PMOS 34 is connected to the signal line N3, the gate of the NMOS 36 is connected to the power supply,
The gate of 38 is connected to the signal line N2, the gate of the NMOS 40 is connected to the signal line EN, and the gates of the NMOS 42 and the PMOS 44 are both connected to the signal line D2. Also, PMOS
The back gate of 32 is connected to the power supply, and the back gates of the PMOSs 34 and 44 are both connected to the pad 18.

The input / output buffer circuit 62 is applied to input / output terminals (bidirectional terminals) of a semiconductor integrated circuit. When a signal is output, the pad 18 is driven to a high level or a low level by the output unit 14. Is done. On the other hand, when a signal is input, the output of the output unit 14 is set to a high impedance state, and a signal having a voltage higher than the power supply voltage of the semiconductor integrated circuit is input from the outside via the pad 18 and supplied to the input unit 12. You.

In the illustrated input / output buffer circuit 62, when the output of the output section 14 is set to a high impedance state when a signal is input, the signal line D1 is at a low level and the signal line D
2 is at a high level, and the signal line EN is at a low level. Here, the power supply voltage of the semiconductor integrated circuit using the input / output buffer circuit 62 is 3 V, and a signal of 5 V (high-level potential) higher than 3 V is input from an external semiconductor integrated circuit operating at a high voltage. The operation in the case of the above will be described.

At this time, since the signal line N1 is driven to 3V by the inverter 46, the PMOS 32 is turned off. The NMOS 40 is turned off, and the PMOS 44 is turned on because 5 V of the pad 18 is applied to its source and back gate and 3 V of the signal line D2 is applied to its gate. As a result, the signal line N3 is
It is charged up to the potential of 5 V applied to the pad 18 via 44, and the PMOS 34 is turned off.

The NMOS 36 has a gate connected to 3V.
Is always on because the power supply voltage of
Since the signal line N2 is driven to the ground potential by the inverter 48, the NMOS 38 is turned off. As described above, when a signal of 5 V is applied to the pad 18 at the time of inputting a signal, the PMOSs 32 and 34 and the NMOS 38 are turned off, so that the output unit 14 is in a high impedance state.

The 5 V signal applied to pad 18 is N
The signal is supplied to the input buffer inverter 24 via the MOS 20. Here, since a power supply voltage of 3V is applied to the gate of the NMOS 20, for example, if the threshold voltage of the NMOS 20 is 0.8V, the potential of the signal line N4 (input of the inverter 24) becomes 3V-0. .8V = 2.2
When the voltage reaches V, the NMOS 20 turns off and the inverter 2
4, a voltage of 2.2 V is applied.

The 2.2 V signal input to the inverter 24 is inverted and output by the inverter 24, and the signal line N5 is driven to the ground potential.
22 is turned on, so that the input of the inverter 24 is
It is charged up to a power supply potential of 3V. The ground potential signal inverted and output by the inverter 24 is further inverted and output by the inverter 30 and supplied to the internal circuit of the semiconductor integrated circuit as a high-level signal.

By the way, in the input / output buffer circuit 62 shown in FIG. 3, when a signal having a voltage higher than the absolute maximum rating, for example, a signal of 7 V is applied at the time of inputting the signal, the transistors constituting the input / output buffer circuit 62 May be destroyed. In this case, the input / output buffer circuit 62 shown in FIG.
By applying the protection diode 58 used in the input protection circuit 52 shown in FIG. 2, for example, the input / output buffer circuit 62 can be protected from a high-voltage signal.

However, as described above, when the protection diode 58 shown in FIG. 2 is applied to protect the input / output buffer circuit 62, similar to the case of the input protection circuit 58 in FIG.
There is a problem that the area of the semiconductor chip is increased.

[0020]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and realize a protection function against an external overvoltage without increasing the area of a semiconductor chip. Another object of the present invention is to provide an input / output buffer circuit applied to a semiconductor integrated circuit used in combination with a semiconductor integrated circuit operating at a high voltage.

[0021]

In order to achieve the above object, the present invention provides an input / output buffer circuit having an output section for driving a pad to a high level or a low level or for setting a high impedance state. The output part is
A first P-type MOS transistor connected in series between a power supply and the pad;
A third P-type MOS transistor connected between the gate of the S transistor and the pad;
At least two diodes connected in series between the gate of an OS transistor and the power supply, and a first N-type MOS transistor connected between the pad and ground; The back gate of the MOS transistor is connected to the power supply, and the second and third
The back gate of the P-type MOS transistor is connected to the pad, the first signal line is connected to the gate of the first P-type MOS transistor, and the third P-type MOS transistor
An input / output buffer circuit, wherein a gate of the transistor is connected to a second signal line, and a gate of the first N-type MOS transistor is connected to the second signal line via an inverter. Is provided.

Here, in the input / output buffer circuit described above, the output unit may further include the pad and the first
N-type MOS transistor
A type MOS transistor; and third and fourth N-type MOS transistors connected in series between the gate of the first P-type MOS transistor and the gate of the second P-type MOS transistor, The power supply is connected to the gate of the second N-type MOS transistor, and the third
Preferably, a third signal line is connected to the gate of the N-type MOS transistor, and the second signal line is connected to the gate of the fourth N-type MOS transistor.

The input / output buffer circuit according to any of the above, further comprising an input section for receiving a signal applied to the pad, wherein the input section is provided between the pad and the input buffer. It is preferable to include a resistance element connected to.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an input / output buffer circuit according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a circuit diagram of an input / output buffer circuit according to an embodiment of the present invention. The input / output buffer circuit 10 shown in FIG.
In that the configuration of the input unit 12 is different from that of the
The only difference is that 4 has three more diodes 50. Therefore, in the present embodiment, the same components as those of the conventional input / output buffer circuit 62 shown in FIG. 3 are denoted by the same reference numerals, and detailed description of the structure is omitted.

That is, the input / output buffer circuit 1 in the illustrated example
0 is constituted by the input unit 12 and the output unit 14.

First, the input section 12 includes a resistance element (protection resistance) 16 connected between a pad 18 and an input buffer (not shown). At the time of inputting a signal, a high-potential signal input via the pad 18 from another semiconductor integrated circuit operating at a higher voltage than the semiconductor integrated circuit to which the input / output buffer circuit 10 is applied is input via the resistor element 16. Supplied to the input buffer. Note that a conventionally known input buffer can be used.

On the other hand, like the output unit 14 of the conventional input / output buffer circuit 62 shown in FIG. 3, the output unit 14 has two PMOSs 32, 34 and two NMOs at the final output stage.
S36, 38, two NMOSs 40, 42, PMO
S44, two inverters 46 and 48, and three diodes 50 connected in series between the signal line N3 and the power supply. When outputting a signal, a high-level or low-level signal is driven from the output unit 14 to the pad 18.

Hereinafter, the operation of the input / output buffer circuit 10 will be described. The input / output buffer circuit 10 is applied to an input / output terminal (bidirectional terminal) of a semiconductor integrated circuit. When outputting a signal, the pad 18 is driven to a high level or a low level by the output unit 14. On the other hand, when a signal is input, the output of the output unit 14 is set to a high impedance state, and a signal input from the outside via the pad 18 is supplied to the input buffer via the input unit 12.

In the input / output buffer circuit 10, when a high level is output from the output unit 14 when a signal is output, the signal lines D1 and D2 are both at a high level, and the signal line EN is also at a high level.

At this time, the signal line N1 is driven to a low level by the inverter 46, and the PMOS 32 turns on. Since the NMOSs 40 and 42 are turned on and the PMOS 44 is turned off, the NMOSs 40 and 42 are turned on.
The signal line N3 is also driven to a low level by the inverter 46, and the PMOS 34 is also turned on. Therefore, pad 18
Is charged up to the potential of the power supply via the turned-on PMOSs 32 and 34.

The NMOS 36 has 3 V at its gate.
Is always on because the power supply voltage of
Since the signal line N2 is driven to a low level by the inverter 48, the NMOS 38 is turned off. As described above, when a high level is output from the output unit 14, the PMO
Since S32 and S34 are turned on and the NMOS 38 is turned off, the pad 18 is charged up to the potential of the power supply through the turned-on PMOSs 32 and 34.

When a low level is output from the output unit 14 when a signal is output, the signal lines D1 and D2 are both at a low level, and the signal line EN is at a high level.

At this time, the NMOS 36 is always on, and the signal line N2 is driven to a high level by the inverter 48, so that the NMOS 38 is also turned on. Therefore, the pad 18 is discharged to the ground potential via the NMOSs 36 and 38.

The signal line N1 is driven to a high level by the inverter 46, and the PMOS 32 is turned off. The NMOS 40 is turned on, and the NMOS 42 is turned off. The PMOSs 34 and 44 are turned off because their back gates are at a low level. As described above, when the output unit 14 outputs a low level, the PMOSs 32 and 34 are turned off and the NMOSs 36 and 38 are turned on.
Are discharged to the ground potential via the turned-on NMOSs 36 and 38.

On the other hand, when the output of the output section 14 is set to a high impedance state when a signal is input, the signal line D1 is at a low level, the signal line D2 is at a high level, and the signal line EN is at a low level. Here, the input / output buffer circuit 1
The operation in the case where the power supply voltage of a semiconductor integrated circuit using 0 is 3 V, and a signal of 5 V (high-level potential) higher than 3 V is input from an external semiconductor integrated circuit that operates at a high voltage will be described.

At this time, the NMOS 40 is off and the PMOS 4
4 is a pad 18 at its source and back gate.
Since V is applied and 3 V of the signal line D2 is applied to the gate, the transistor turns on. As a result, the signal line N3 receives the 5V voltage applied to the pad 18 through the turned-on PMOS 44.
And the PMOS 34 is turned off. Further, since the signal line N1 is driven to 3V by the inverter 46, the PMOS 32 is turned off.

Here, when the signal line N3 is charged up to 5V, the three diodes 50 are biased forward by 2V. In this embodiment, the sum of the threshold voltages of the diodes 50 is 2 V or more, that is, the pad 1
The number of diodes 50 is determined so as to be equal to or more than the voltage of the difference between the 5 V signal applied to 8 and 3 V of the power supply, and the diodes 50 do not conduct. Therefore, the signal line N3
Is kept at 5 V, the PMOS 34 is turned off,
No leak current occurs.

The NMOS 36 has a gate connected to 3V.
Is always on because the power supply voltage of
Since the signal line N2 is driven to the ground potential by the inverter 48, the NMOS 38 is turned off. As described above, when a signal of 5 V is applied to the pad 18 at the time of inputting a signal, the PMOSs 32 and 34 and the NMOS 38 are turned off, so that the output unit 14 is in a high impedance state.

The 5 V signal applied to the pad 18 is supplied to an input buffer (not shown) via the resistance element 16. A signal of a voltage lowered by a predetermined voltage by the resistance element 16 is supplied to the input buffer.

Next, an operation when a 7 V signal (positive overvoltage) higher than 5 V is input from an external semiconductor integrated circuit operating at a high voltage will be described.

In this case, 4 V is applied to the three diodes 50.
Forward bias is applied. In this embodiment, the diodes 50 are controlled so that the total value of the threshold voltages of the three diodes 50 is 4 V or less, that is, the voltage of the difference between the signal of 7 V applied to the pad 18 and 3 V of the power supply. The number is determined, and the pad 18, the NMOS 44, the signal line N
3. A current flows through the diode 50, and the potential of the signal line N3 decreases, for example, to 6V.

Accordingly, the PMOS 34 is turned on because 7 V of the pad 18 is applied to its source and back gate, and 6 V of the signal line N 3 is applied to its gate. When the PMOS 34 is turned on, the potential of the back gate of the PMOS 32 is 3 V, so that the parasitic diode including the drain of the PMOS 32 and the back gate (N well) is turned on. The PMOS 32 has a PMOS connected to its source.
Since 7 V is applied to the pad 18 via 34, and 3 V is applied to the gate of the pad 18 by the inverter 46, the pad 18 is turned on. As a result, the pad 18, the PMOS 34, 32
, The input / output buffer circuit 10 is protected.

In the illustrated input / output buffer circuit 10, when a negative overvoltage is applied to the pad 18,
Since the MOS 36 is always on and the potential of the back gate of the NMOS 38 is ground, the parasitic diode formed by the drain of the NMOS 38 and its back gate (P substrate) is turned on. The NMOS 38 has an N
Since the negative overvoltage of the pad 18 is applied via the MOS 36 and the ground potential is applied to the gate of the pad 18 by the inverter 48, the pad 18 is turned on. With this, NMO
Since current flows through the pads 18 at S14 and S13,
Even when a negative overvoltage is applied, the input / output buffer circuit 10
Is protected.

It is preferable that the number of the diodes 50 connected between the signal line N3 and the power supply is two or more, and is appropriately determined as necessary. That is, the first
Does not conduct when a signal up to a predetermined potential (eg, an absolute maximum rated potential) is applied, and a signal having a second predetermined potential or higher (ie, an overvoltage signal) higher than the first predetermined potential is applied. The number of diodes 50 connected in series may be determined so as to conduct when applied.

The diode 50 only needs to be capable of flowing a current that can cause a voltage drop that can turn on the PMOS 34 to the signal line N3. Equivalent to PMOS 44 (for example, in this embodiment, W / L
(Gate width / gate length) = about 30 μm / 0.5 μm)
Therefore, adding the diode 50 hardly increases the area of the semiconductor chip.

In the input / output buffer circuit 10 of the present invention, the PMOS 32,
34, the PMOSs 32 and 34 are originally transistors at the final output stage, and have a sufficient size as a protection element (in the present embodiment, W / L = 740 μm /
About 0.5 μm). Also, since the NMOSs 36 and 38 can be used as they are as protection elements against a negative overvoltage,
It is not necessary to separately prepare a diode corresponding to the diode 50.

The input / output buffer circuit according to the present invention is a circuit applied to input-only, output-only, and bidirectional input / output terminals of a semiconductor integrated circuit. In the example shown,
Although the input / output buffer circuit applied to the bidirectional terminal of the semiconductor integrated circuit has been described as an example, the input / output buffer circuit of the present invention is not limited to the input / output buffer circuit applied to the bidirectional terminal. Without the output unit 14
It is also applicable to an output buffer circuit for state output.

Although the NMOS 36 is provided in the example shown in FIG. 1, the NMOS 36 may not be provided. Further, the circuit composed of the NMOSs 40 and 42 may be realized by a different circuit that performs the same function. In the embodiment, the power supply voltage of the semiconductor integrated circuit to which the input / output buffer circuit of the present invention is applied is 3 V, the voltage of a signal applied from another semiconductor integrated circuit is 5 V, and the positive overvoltage is 7 V. Also, these voltage values are not limited at all.

The input / output buffer circuit of the present invention is basically as described above. As described above, the input / output buffer circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. It is.

[0051]

As described in detail above, the input / output buffer circuit according to the present invention comprises the first and second PMOSs connected in series between the power supply and the pad, and the gates of the second PMOSs. A third PMOS connected between the pad, a plurality of diodes connected in series between the gate of the second PMOS and the power supply, and an NMOS connected between the pad and the ground; , The back gate of the first PMOS is connected to a power supply, the back gates of the second and third PMOSs are connected to pads, and the first and second signal lines are connected to the gates of the first and third PMOSs, respectively. Connect and first
The second signal line is connected to the NMOS gate via an inverter. According to the above configuration, according to the input / output buffer circuit of the present invention, the transistor at the output final stage can be used as a protection element against overvoltage only by adding a plurality of diodes having a small size. As compared with the case where the protection function is realized by combining the input / output buffer circuit of the related art shown in FIG. 3, the effect of significantly increasing the chip area due to the addition of the diode can be obtained. Further, according to the input / output buffer circuit of the present invention, since the transistor at the final output stage can be used as it is for the protection element against a negative overvoltage, a diode is not required separately, and an increase in chip area is suppressed. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of one embodiment of an input / output buffer circuit of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a conventional input protection circuit.

FIG. 3 is a configuration circuit diagram of an example of a conventional input / output buffer circuit.

[Explanation of symbols]

10, 62 input / output buffer circuit 12 input unit 14 output unit 16, 56 resistance element 18 pad 20, 28, 36, 38, 40, 42 N-type MOS transistor (NMOS) 22, 26, 32, 34, 44 P-type MOS Transistor (PMOS) 24, 30, 46, 48 Inverter 50, 58, 60 Diode 52 Input protection circuit 54 Input buffer D1, D2, EN, N1, N2, N3, N4, N5, N
Signal line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BE07 BH04 BH13 CA10 CD08 DF06 EZ20 5J056 AA04 BB46 BB51 BB54 DD13 DD29 DD55 FF07 FF09 GG12

Claims (3)

[Claims] 1. An input / output buffer circuit comprising an output section for driving a pad to a high level or a low level or for entering a high impedance state, wherein said output section is connected in series between a power supply and said pad. First and second P-type MOS transistors, a third P-type MOS transistor connected between the gate of the second P-type MOS transistor and the pad, and the second P-type MOS transistor. At least two diodes connected in series between the power supply gate and the power supply, and a first N connected between the pad and ground.
A back gate of the first P-type MOS transistor is connected to the power supply; a back gate of the second and third P-type MOS transistors is connected to the pad; A gate of the P-type MOS transistor is connected to a first signal line, a gate of the third P-type MOS transistor is connected to a second signal line, and a gate of the first N-type MOS transistor is connected to a gate. An input / output buffer circuit, wherein the second signal line is connected via an inverter. 2. The input / output buffer circuit according to claim 1, wherein said output unit further comprises: said pad and said first N-type M.
Second N-type MOS connected between OS transistor
A transistor, and third and fourth N-type MOS transistors connected in series between a gate of the first P-type MOS transistor and a gate of the second P-type MOS transistor; The power supply is connected to the gate of the N-type MOS transistor, and the third signal line is connected to the gate of the third N-type MOS transistor.
An input / output buffer circuit, wherein the gate of the S transistor is connected to the second signal line. 3. The input / output buffer circuit according to claim 1, further comprising: an input section to which a signal applied to said pad is input, wherein said input section includes said pad, an input buffer, and an input buffer. An input / output buffer circuit comprising a resistor connected between the input and output.