JPH11317652A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit whose delay time is short, without generating unwanted current nor gate oxide film destruction, even at the inputting of a signal whose voltage is higher than power supply voltage. SOLUTION: A 1st P-channel type MOS transistor 12 is connected serially to a 2nd P-channel type MOS transistor 11. One end of the transistor 12 is connected to an input-output terminal IO. A gate control circuit 40 makes the transistor 12 a cutoff state, when the voltage of a signal that is inputted to the terminal IO exceeds power supply voltage. An enable signal EN and an input signal IN are inputted to a NAND circuit 19, the gate of the transistor 11 is controlled by an output signal of the circuit 19, and a signal is outputted from the IO from it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interface for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, power consumption has been increasing as semiconductor integrated circuits (hereinafter, referred to as LSIs) are being integrated and operated at higher speeds. As a means to suppress the increase in power consumption,
Many means for lowering the power supply voltage to operate the LSI are employed. However, if the power supply voltage cannot be reduced in all LSIs, an interface between an LSI that operates at a high power supply voltage (for example, 5 V) and an LSI that operates at a low power supply voltage (for example, 3.3 V) has become important. . When an input / output terminal of an LSI operating at a high power supply voltage such as 5 V is connected to an input / output terminal of an LSI operating at a low power supply voltage such as 3.3 V, the following two problems occur.

A first point is that, in a LSI operating at 3.3 V, when a voltage (5 V) higher than a power supply voltage (3.3 V) is input, a P-channel type which forms an output circuit portion of an input / output circuit is used. This is a point that the MOS transistor becomes conductive and current flows from the input / output terminal to the power supply line inside the LSI through the P-channel MOS transistor. The input / output terminals need to be in a high impedance state when in the input state. Therefore, if a current is supplied, an unnecessary increase in power consumption is caused.

Second, the gate oxide film of the MOS transistor inside the LSI operating at 3.3 V often does not have a withstand voltage exceeding its power supply voltage (3.3 V).
When a high voltage such as 5 V is input thereto, the breakdown voltage of the gate oxide film is exceeded, and the MOS transistor is destroyed.

[0005] Therefore, as means for solving the above problems,
For example, US Pat. No. 5,555,149 has already been proposed.

Hereinafter, a conventional input / output circuit will be described with reference to the drawings. In the input / output circuit described below, the above two problems have already been solved.

FIG. 3 shows a configuration diagram of a conventional input / output circuit.

In FIG. 3, IO is an input / output terminal for transmitting and receiving signals to and from the outside of the LSI. IN is an input terminal for inputting a signal from inside the LSI. OUT is an output terminal for outputting a signal inside the LSI. Further, EN is an enable terminal for switching between the output state and the input state of the input / output terminal IO.

An output circuit 1 is an enable terminal E
When N is at a high level (hereinafter, referred to as “H”), a signal from an input terminal IN is output from an input / output terminal IO, and when an enable terminal EN is at a low level (hereinafter, referred to as “L”),
The input / output terminal IO is set to a high impedance state.

Reference numerals 11, 12, and 13 denote P-channel MOS transistors (hereinafter, referred to as PMOS), 14, 15, 1
Reference numerals 6 and 17 denote N-channel MOS transistors (hereinafter referred to as N-channel MOS transistors).
MOS). Reference numeral 18 denotes an inverter circuit, 19 denotes a NAND circuit, and 20 denotes a NOR circuit. Further, 21 is a power supply terminal, and 22 is a ground terminal. PMOS 11,
Reference numeral 12 is connected in series between the power supply terminal 21 and the input / output terminal IO. The NMOSs 14 and 15 are connected in series between the input / output terminal IO and the ground terminal 22.

The output of the NAND circuit 19 is a PMOS 11
NMOS connected to the gate of
The signal is input to the gate of the PMOS 12 via the switches 17 and 16 in turn, and is input to the gate of the NMOS 17 via the inverter circuit 18. One input terminal of the NAND circuit 19 is connected to the enable terminal EN, and the other terminal is connected to the input terminal IN. Also, input / output terminals IO and PMOS
12 is connected via a PMOS 13. P
The gates of the MOS 13, NMOS 14, and NMOS 16 are connected to the power supply terminal 21.

The output of the NOR circuit 20 is input to the gate of the NMOS 15, the inverted signal of the enable terminal EN is input to one input terminal of the NOR circuit 20, and the other terminal is connected to the input terminal IN.

An input circuit 2 has an input / output terminal I
This is a function of outputting a signal from the output terminal OUT from the output terminal OUT and transmitting the signal to the inside of the LSI.

The operation of outputting a signal from the internal circuit of the output circuit 1 to the input / output terminal IO in the input / output circuit configured as described above will be described below.

To output a signal from the input / output terminal IO,
The enable terminal EN is set to “H”. First, when the input terminal IN is “H”, the input terminal IN is connected to the input / output terminal IO.
The output operation to the device will be described. At this time, the outputs of the NAND circuit 19 and the NOR circuit 20 both become "L". P
The gates of MOS13, NMOS14 and NMOS16 are
Since it is connected to the power supply terminal 21, the gate always has "
H ”signal is input, the PMOS 13 is turned off, and NM
The OS 14 is conducting, and the NMOS 16 is conducting. Since an “L” signal is input from the NAND circuit 19 to the inverter circuit 18, “H” is output and N
The MOS 17 is turned on. At this time, the PMOS 11,
The gates of the PMOS 12 and the NMOS 15 all become "L", the PMOSs 11 and 12 are in the conductive state, and the NMOS 15 is in the cut-off state. Therefore, the power supply terminal 21 and the two PMOSs
11, from the input / output terminal IO via the PMOS 12,
H "is output.

Next, an output operation from the input terminal IN to the input / output terminal IO when the input terminal IN is "L" will be described. At this time, the NAND circuit 19 and the NOR circuit 20
Are both "H". PMOS13, NMOS1
Since the gates of the NMOS transistor 4 and the NMOS 16 are connected to the power supply terminal 21, a signal of “H” is always input to the gate, the PMOS 13 is turned off, the NMOS 14 is turned on, and the NMOS 16 is turned on. Since the signal of “H” is input from the NAND circuit 19 to the inverter circuit 18, the inverter circuit 18 outputs “L” and turns off the NMOS 17. At this time, since the gate of the PMOS 13 is "H" and is in the cutoff state, the gate voltage of the PMOS 12 is undefined. Further, since the gates of the PMOS 11 and the NMOS 15 are at “H”, the PMOS 11 is in the cut-off state, and NM
OS15 is conductive. The gate of the NMOS 14 is also "
H ”, which indicates a conductive state.
2, input / output terminal I via NMOS 15 and NMOS 14
O outputs a signal of “L”.

Although the state of the PMOS 12 is undefined,
Since the PMOS 11 connected in series with the PMOS 12 is in the cutoff state, no current flows from the power supply terminal 21 to the input / output terminal IO.

Next, the operation of inputting a signal from the input / output terminal IO to the internal circuit will be described below.

To input a signal from the input / output terminal IO, the enable terminal EN is set to "L". At this time, the output circuit 1
Are in a high impedance state with respect to the input / output terminal IO. Hereinafter, the operation of the output circuit 1 in the high impedance state will be described below.

When the enable terminal EN is set to "L", N
The output of the AND circuit 19 becomes "H" and the output of the NOR circuit 20 becomes "L". An “H” signal is input to the gate of the PMOS 11, and an “L” signal is input to the gate of the NMOS 15. Therefore, there is no current path from the input / output terminal IO. In other words, PMOS
11 and the NMOS 15 are cut off, the power supply terminal 2
1 and a current path connecting the ground terminal 22 to the input / output terminal IO is eliminated. At this time, the output circuit 1 is in a high impedance state.

In this state, when a signal is input from the input / output terminal IO, a signal is input from the output terminal OUT to the internal circuit through the input circuit 2.

Here, the operation of the output circuit 1 when a voltage higher than the power supply voltage is input from the input / output terminal IO will be described. The case where the power supply voltage of the power supply terminal 21 is 3.3 V and a signal of a voltage (for example, 5 V) exceeding the power supply voltage is input from the input / output terminal IO will be described as an example.

In the PMOS 13, the gate voltage (3.
3V), the voltage at one end becomes higher (becomes 5V), so that the PMOS 13 becomes conductive and the input / output terminal I
An input signal (5 V) from O is propagated to the gate of the PMOS 12. Thus, the PMOS 12 has a gate of 5 V
And becomes a cutoff state. Therefore, the current from the input / output terminal IO to the power supply terminal 21 is cut off.

On the other hand, the signal (5 V) from the input / output terminal IO is also propagated to the NMOS 16, but the gate voltage (3.3
V) is the voltage at one end (5V) and the voltage at the other end (3.3V)
, So that it is in the cutoff state. Therefore, an input signal of 5 V propagated from the input / output terminal IO via the PMOS 13 does not reach the NMOS 17.

Further, since the NMOS 15 is also in the cutoff state, no current flows from the input / output terminal IO to the ground terminal 22.

5 V is applied to one end of each of the NMOS 14 and the NMOS 16. Since the gate voltage is 3.3 V, the difference between 5 V and 3.3 V, that is, 1.7 is applied to the gate oxide film.
Only V is applied, and the gate oxide film is not destroyed. In the PMOS 13, 5V is applied to both ends. However, since the gate voltage is 3.3V, only a difference between 5V and 3.3V, that is, 1.7V is applied to the gate oxide film.
The gate oxide film will not be destroyed. In the PMOS 12, 5V is applied to the gate, but the voltage at one end is also 5V and the voltage at the other end is 3.3V, so the voltage of the gate oxide film is 1.7V. The voltage at the other end of the NMOS 14 is a voltage (2.3 V) obtained by subtracting the threshold voltage of the NMOS 14 (1 V in consideration of the back bias effect) from the gate voltage (3.3 V), and does not adversely affect the NMOS 15. .

[0027]

However, in the conventional input / output circuit of FIG. 3 described above with reference to FIG. 3, in the output circuit 1, the input terminal IN is connected to the input / output terminal IO.
When an “H” signal is output to the NAND circuit 19, the signal from the input terminal IN, the inverter circuit 18, the NMOS 1
7, input / output terminals IO via NMOS16 and PMOS12
It is configured to output from. For this reason, there is a problem that the delay time from the input / output terminal IO to the output of the signal input to the input terminal IN becomes very long.

In the semiconductor integrated circuit technology, the purpose of lowering the power supply voltage is to suppress the increase in power consumption when the degree of integration of the LSI is increased and the operating speed is increased. It is contrary to this purpose and difficult to accept.

The NAND circuit 19 includes an inverter circuit 18, an NMOS 17, an NMOS 16, a PMOS 11,
It is necessary to drive PMOS12 and PMOS13,
To drive these at high speed, the NAND circuit 19
It is necessary to increase the size of the transistor that constitutes. However, this is contrary to the improvement in the degree of integration and the reduction in power consumption.

An object of the present invention is to provide an output having a shorter delay time than before without causing unnecessary current generation and gate oxide film destruction even when a signal having a voltage higher than the power supply voltage is input. It is to provide a circuit.

[0031]

In order to achieve the above object, an output circuit according to the present invention is an output circuit having an input / output terminal, the output circuit having one end connected to the input / output terminal. One P-channel MOS transistor, a second P-channel MOS transistor connected in series to the other end of the first P-channel MOS transistor, and a first P-channel MOS transistor connected to the input / output terminal. Type MOS
A gate control circuit that controls a gate voltage of the transistor, wherein a signal is input to a gate of the second P-channel MOS transistor, and a signal is output from the input / output terminal in accordance with the input signal. I do.

According to a second aspect of the present invention, in the output circuit of the first aspect, the gate control circuit lowers a gate voltage of the first P-channel MOS transistor below a power supply voltage when the output is enabled. The first P-channel MOS transistor is turned on. On the other hand, when the output is disabled, when the voltage of the input / output terminal exceeds the power supply voltage, the first P-channel MOS transistor is turned off.
A gate of the transistor is connected to the input / output terminal to shut off the first P-channel MOS transistor.

According to a third aspect of the present invention, in the output circuit of the first aspect, the gate control circuit includes a third P-type gate.
A third P-channel type MOS transistor having a channel type MOS transistor and a first N-channel type MOS transistor.
The OS transistor has one end connected to the input / output terminal, the other end connected to the gate of the first P-channel MOS transistor, a gate voltage set to a power supply voltage, and the first N-channel MOS transistor One end is connected to the gate of the first P-channel MOS transistor, the other end is set to a ground voltage or a voltage lower than a power supply voltage, and an enable signal is input to the gate.

According to a fourth aspect of the present invention, in the output circuit of the third aspect, the gate control circuit has a voltage dropping circuit, and the voltage dropping circuit is connected to the first P-channel MOS transistor. It is arranged between a gate and the one end of the first N-channel MOS transistor.

According to a fifth aspect of the present invention, in the output circuit of the third aspect, a fourth P-channel type MOS transistor is separately provided.
The fourth P-channel MOS transistor has a power supply voltage at one end, a power supply voltage at the other end, and a gate connected to the substrate of the first, second, and third P-channel MOS transistors; Is connected to the input / output terminal.

According to a sixth aspect of the present invention, in the output circuit of the first aspect, when the voltage of the input / output terminal is equal to or lower than a power supply voltage, the gate control circuit operates the first P-channel MOS transistor. The first P-channel MOS transistor is turned on by lowering the gate voltage from the power supply voltage, and when the voltage of the input / output terminal exceeds the power supply voltage, the gate of the first P-channel MOS transistor is turned off. To the input / output terminal to connect the first
Are turned off.

According to a seventh aspect of the present invention, in the output circuit of the sixth aspect, the gate control circuit comprises a third and a fourth P-channel MOS transistor, and a first and a second P-channel MOS transistor.
One end of the third P-channel MOS transistor, one end of the first N-channel MOS transistor.
One end of the channel-type MOS transistor and the gate of the second N-channel-type MOS transistor are connected to the gate of the first P-channel-type MOS transistor, respectively, and the fourth P-channel-type MOS transistor has one end thereof. Is connected to the gate of the first N-channel MOS transistor and one end of the second N-channel MOS transistor, the voltage at the other end is a power supply voltage, and the third P-channel MOS transistor has a gate voltage Is the power supply voltage, and one end is the fourth P-channel MOS.
The transistor is connected to the gate, and the other end is connected to the input / output terminal.

According to an eighth aspect of the present invention, in the output circuit according to the seventh aspect, the gate control circuit comprises a fifth P circuit.
The fifth P-channel MOS transistor has a gate connected to the input / output terminal, one end connected to one end of the second N-channel MOS transistor, and a voltage at the other end. Is a power supply voltage.

According to a ninth aspect of the present invention, in the output circuit of the seventh or eighth aspect, the gate control circuit comprises:
There are first and second voltage drop circuits, wherein the first voltage drop circuit is arranged between a gate of the first P-channel MOS transistor and one end of the first N-channel MOS transistor. And the second voltage drop circuit comprises:
One end of the fourth P-channel MOS transistor;
It is arranged between a gate of the first N-channel MOS transistor and a connection point between one end of the second N-channel MOS transistor.

According to a tenth aspect of the present invention, in the output circuit of the ninth aspect, the gate control circuit has a third voltage drop circuit, and the third voltage drop circuit performs a voltage drop function. A circuit portion, and a sixth P-channel MOS transistor. The sixth P-channel MOS transistor has one end connected to one end of the fifth P-channel MOS transistor and the other end connected to the fifth P-channel MOS transistor. The gate of the first N-channel MOS transistor is connected to the connection point between one end of the second N-channel MOS transistor, and the gate is connected to the input / output terminal via the circuit portion performing the voltage drop function. It is characterized by that.

According to an eleventh aspect of the present invention, in the output circuit of the seventh aspect, a seventh P-channel type MO is separately provided.
The seventh P-channel MOS having an S transistor
The transistor is characterized in that one end has a power supply voltage, the other end is connected to the substrate of the first, second and third P-channel MOS transistors, and the gate is connected to the input / output terminal. I do.

According to a twelfth aspect of the present invention, in the output circuit according to the fourth aspect, the voltage dropping circuit includes an N-channel MOS transistor having a gate as a power supply voltage, and a P-channel MOS transistor having a gate at a power supply voltage or less. It is characterized by comprising a transistor, a diode, or a circuit in which a plurality of these are connected in series.

According to a thirteenth aspect of the present invention, in the output circuit according to the ninth or tenth aspect, the first voltage dropping circuit includes an N-channel type MOS transistor having a gate as a power supply voltage.
It is characterized by comprising an S-transistor, a P-channel MOS transistor having a gate lower than the power supply voltage, a diode, or a circuit in which a plurality of these are connected in series.

According to a fourteenth aspect of the present invention, in the output circuit according to the ninth or tenth aspect, the second voltage dropping circuit includes an N-channel type MOS transistor having a gate as a power supply voltage.
It is characterized by comprising an S-transistor, a P-channel MOS transistor having a gate lower than the power supply voltage, a diode, or a circuit in which a plurality of these are connected in series.

According to a fifteenth aspect, in the tenth aspect,
In the output circuit, the third voltage drop circuit includes:
It is characterized by comprising an N-channel MOS transistor whose gate is a power supply voltage, a P-channel MOS transistor whose gate is not more than the power supply voltage, a diode, or a circuit in which a plurality of these are connected in series.

According to the above configuration, even when a signal having a voltage higher than the power supply voltage is input, an output circuit having a further shorter delay time can be obtained without generating unnecessary current and causing gate oxide film destruction.

[0047]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a configuration diagram of an input / output circuit according to the embodiment.

It should be noted that the present invention has a special feature in an output circuit section constituting an input / output circuit. Therefore, the description of the internal configuration of the input circuit, which is another component of the input / output circuit, is omitted.

In FIG. 1, IO is an input / output terminal for transmitting and receiving signals to and from the outside of the LSI. IN is an input terminal for inputting a signal from inside the LSI. OUT is an output terminal for outputting a signal inside the LSI. Further, EN is an enable terminal for switching between an output state and an input state of the input / output terminal IO.

Reference numeral 1 denotes an output circuit which outputs a signal from the input terminal IN from the input / output terminal IO when the enable terminal is "H", and sets the input / output terminal IO high when the enable terminal is "L". Set to impedance state.

12 is a first PMOS, 11 is a second PM
OS, 13 is a third PMOS, and 31 is a fourth PMOS. 14, 15, and 16 are NMOSs, and 17 is a first NM.
OS. 19 is a NAND circuit, and 20 is a NOR circuit. Further, 21 is a power supply terminal, and 22 is a ground terminal. A gate control circuit 40 controls a gate voltage of the first PMOS 12.
It comprises three and two NMOSs 16 and 17. The NMO
S16 forms a voltage drop circuit.

The PMOS 11 and the PMOS 12 are connected in series between the power supply terminal 21 and the input / output terminal IO. The NMOS 14 and the NMOS 15 are connected in series between the ground terminal 22 and the input / output terminal IO. The output of the NAND circuit 19 is input to the gate of the PMOS 11, and one input terminal of the NAND circuit 19 is connected to the enable terminal EN, and the other terminal is connected to the input terminal IN. The output of the NOR circuit 20 is input to the gate of the NMOS 15, the inverted signal of the enable terminal EN is input to one input terminal of the NOR circuit 20, and the input terminal IN is connected to the other terminal. The gate of the PMOS 12 is connected to the ground terminal 22 via the NMOS 16 and NMOS 17 connected in series, and the PMOS 1
3 and an input / output terminal IO.

PMOS 13, NMOS 14, NMOS 1
6 is connected to the power supply terminal 21 and the gate of the NMOS 17 is connected to the enable terminal EN.

Further, PMOS 11, PMOS 12, PM
The substrates of the OS 13 and the PMOS 31 are connected to the power supply terminal 21 via the PMOS 31 whose gate is connected to the input / output terminal IO.

The substrate of the PMOS 11 is not necessarily PM
It is not necessary to be connected in common with the substrate of the OS 12, but if the connection is made in common, the effect that the area can be reduced in design can be obtained.

The gates of the NMOS 14 and the NMOS 16 are connected to a power supply, and even if a voltage exceeding the power supply voltage is applied to one end, (gate potential-threshold voltage) is applied to the other end. ) Only transmitted,
It functions as a voltage drop circuit.

An input circuit 2 transmits a signal input to the input / output terminal IO to the inside of the LSI via the output terminal OUT.

The operation of the input / output circuit configured as described above, particularly, the operation of the output circuit 1 will be described below.

First, the operation when a signal is output from the internal circuit via the input terminal IN, the output circuit 1, and the input / output terminal IO will be described.

To output a signal from the input / output terminal IO,
The enable terminal EN is set to “H”. Input terminal IN is “
If it is "H", the outputs of the NAND circuit 19 and the NOR circuit 20 both become "L".
4. Since the gates of the NMOS 16 and the NMOS 16 are both "H" with the gate connected to the power supply terminal 21, the PMOS 13 is in the cut-off state, and NM
OS 14 and NMOS 16 are conducting. PMOS1
Numeral 1 indicates that the gate is "L" and is in a conductive state, NMOS 15 has a gate in "L" and is in a cut-off state, and NMOS 17 is in a conductive state with a gate "H". NMOS 16, N
Since the MOS 17 is in a conductive state, the gate of the PMOS 12 is set to “L” to be in a conductive state.

Therefore, the PMOS 11, PMOS 12, N
Since the MOS 14 is in the conductive state and the NMOS 15 is in the cutoff state, a signal of “H” is output from the power supply terminal 21 to the input / output terminal IO.

At this time, the gate of the PMOS 31 is "
H ”, and becomes a cut-off state.
The substrates of S12, PMOS 13, and PMOS 31 are in a floating state. In this case, PMOS 11, PMO
The substrate potential is a voltage obtained by subtracting the built-in voltage (about 0.7 V) of the diode from the power supply voltage due to the drain diffusion layer of S12 and the PMOS 31 and the parasitic diode of the substrate. If the power supply voltage is 3.3 V, the substrate voltage becomes 2 .6
V.

Next, the operation of the output circuit 1 when the input terminal IN is at "L" will be described. At this time, an "H" signal is output from the enable terminal EN.

When the input terminal IN is at "L", the outputs of the NAND circuit 19 and the NOR circuit 20 are both at "H".
At this time, since the NMOS 17 and the NMOS 16 are both conductive, the gate of the PMOS 12 is connected to the ground terminal 22.
, The signal of “L” is input, and the PMOS 12 remains conductive. On the other hand, the gate of the PMOS 11 has NAN
Since the “H” signal is input from the D circuit 19, the PMO
S11 is cut off, and the path from the power supply terminal 21 to the input / output terminal IO is cut off.

Since the NMOS 14 and the NMOS 15 are conductive, the ground terminal 22 is connected to the input / output terminal IO.
Output a signal of “L”.

At this time, the gate of the PMOS 31 is "L".
Therefore, the conduction state is established. Therefore, the PMOS 11, P
The substrates of the MOS 12, the PMOS 13, and the PMOS 31 have the potential of the power supply voltage (3.3 V).

Next, the operation when a signal is input from the input / output terminal IO to the internal circuit via the input circuit 2 and the output terminal OUT will be described.

At this time, an "L" signal is input to the enable terminal EN, and the output circuit 1 is brought into a high impedance state with respect to the input / output circuit IO.

The operation of the output circuit 1 at this time will be described in more detail.

When the enable terminal EN is set to "L", N
The output of the AND circuit 19 becomes "H" and the output of the NOR circuit 20 becomes "L". As a result, the gate of the PMOS 11 becomes "H" and the gate of the NMOS 15 becomes "L", and each of them becomes cut off. Further, the PMOS 13 whose gate is connected to the power supply terminal 21 is also in a cutoff state. Therefore,
There is no current path from the input / output terminal IO, and the output circuit 1
Is in a high impedance state. In this state, when a signal is input from the input / output terminal IO, this signal is input to the input circuit 2.
Output from the output terminal OUT.

Further, when a voltage higher than the power supply voltage is input, for example, when the power supply voltage is 3.3 V and a 5 V signal is input to the input / output terminal IO, the PMOS 13
In this case, the voltage at one end becomes higher than the gate voltage (3.3 V) (becomes 5 V), so that the PMOS 13 becomes conductive, and the input signal of 5 V is transmitted to the gate of the PMOS 12. Thus, the PMOS 12 has a gate voltage of 5
When the voltage becomes V, the state is cut off, and the current from the input / output terminal IO to the power supply terminal 21 is cut off. On the other hand, 5
Although V is propagated, since the gate of the NMOS 16 has 3.3 V, a voltage obtained by subtracting the threshold voltage of the NMOS 16 (1 V in consideration of the back bias effect) from the gate voltage (3.3 V) is applied to the NMOS 17. 2.3V). Since the NMOS 17 is in the cutoff state, the signal from the input / output terminal IO is output from the PMOS 13 and the NMOS
In step S16, the current does not flow into the ground terminal 22 via the NMOS 17. Further, since the NMOS 15 is also in the cutoff state, the NMOS 14 and the NMOS 15 are connected from the input / output terminal IO.
No current flows to the ground terminal 22 via the.

While 5 V is applied to one end of the NMOS 14 and the NMOS 16, since the gate voltage is 3.3 V, the difference between 5 V and 3.3 V, that is, 1.7 is applied to the gate oxide film.
V is applied, and the gate oxide film does not break down. In the PMOS 13, 5 V is applied to both ends. However, since the gate voltage is 3.3 V, only a difference between 5 V and 3.3 V, that is, 1.7 V is applied to the gate oxide film. The film does not break. Further, in the PMOS 12, 5V is applied to the gate, but the voltage at one end is also 5V and the voltage at the other end is 3.3V, so the voltage of the gate oxide film is 1.7V. Furthermore, N
The voltage at the other end of the MOS 14 is changed from the gate voltage (3.3 V) to the threshold of the NMOS 16 (1 in consideration of the back bias effect).
V) (2.3V) minus NM
There is no adverse effect on the OS 15. Also, PMOS
11 and the PMOS 31, PMOS 12, PM
The substrate potentials of the OS 13 and the PMOS 31 are connected to the input / output terminals IO
(5 V) minus the built-in voltage of the diode (approximately 0.7 V).

According to the above configuration, the input / output terminal I
When a signal is output from O, the PMOS 12 is always in a conductive state, and the signal from the input terminal IN is
9, input / output terminals IO via PMOS11 and PMOS12
, The delay time until the signal input to the input terminal IN is output from the input / output terminal IO can be reduced as compared with the conventional output circuit.

Since only the PMOS 11 is driven by the signal from the NAND circuit 19, the NAND
It is not necessary to increase the transistor size of the circuit 19, which can contribute to high integration of the LSI. Further, the load driven by the NAND circuit 19 is small.
Since the transistor size itself is small, it is also effective in reducing power consumption.

When the withstand voltage of each transistor constituting the LSI is 5 V and only the power supply voltage is 3.3 V, N
It is not always necessary to provide the MOS 14 and the NMOS 16.

Also, the PMOS 11, PMOS 12, PM
The substrate of the OS 13 may be connected to the input / output terminal IO as in the conventional example. However, as in this embodiment, the PMOS
When connected to the power supply terminal 21 via the base 31, the voltage of the substrate fluctuates from 0 V to 5 V in the conventional example, whereas the fluctuation width of the substrate voltage can be made as small as 3.3 V to 5 V in the present embodiment. Therefore, power consumption can be reduced.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
1 is a configuration diagram of an input / output circuit according to an embodiment.

The same components as those in the first embodiment described with reference to FIG. 1 are denoted by the same reference numerals.

In FIG. 2, IO is an input / output terminal, IN is an input terminal, OUT is an output terminal, EN is an enable terminal,
1 is an output circuit. 12 is a first PMOS, 11 is a second PMOS, 13 is a third PMOS, and 36 is a fourth PMOS.
MOS, 32 is a fifth PMOS, 35 is a sixth PMOS
S and 31 are a seventh PMOS, and 37 is another PMOS. 14, 15, and 16 are NMOS, 38 is a first NMOS, 39 is a second NMOS, and 34 is another NMOS.
It is. 19 is a NAND circuit, and 20 is a NOR circuit. The NMOS 16 constitutes a first voltage drop circuit,
The PMOS 37 forms a second voltage drop circuit. Further, 21 is a power supply terminal, 22 is a ground terminal, and 33 is a third terminal.
Of the NMOS 34 and the sixth P
MOS 35. The NMOS 34 is a circuit portion that performs a voltage drop function. Reference numeral 41 denotes a gate control circuit for controlling a gate voltage of the first PMOS 12, and the third to sixth PMOSs 13, 36, 32,
35 and the other PMOS 37 and the first and second NMs.
OSs 38 and 39 and another NMOS 34.

The PMOS 32 has a gate connected to the input / output terminal IO, one end connected to the power supply terminal 21, and the other end connected to the PMO terminal.
The gate of the NMOS 38, one end of the PMOS 37, and one end of the NMOS 39 are connected via S35. Also, PMO
The gate of S32 is connected to a PMOS 35 via an NMOS 34.
Connected to the gate. The gate of the NMOS 34 is connected to the power supply terminal 21. The gates of the PMOS 37 and the NMOS 39 are connected to each other.
38 is also connected to the intermediate node. The other end of the PMOS 37 is connected to the power supply terminal 21 via the PMOS 36,
The gate of the OS 36 is connected to an intermediate node between the NMOS 16 and the PMOS 13. The other ends of the NMOS 38 and the NMOS 39 are connected to the ground terminal 22.

The second embodiment differs from the first embodiment in that the first embodiment is different from the PMO in the first embodiment.
While the gate of S12 is controlled by the potential of the input / output terminal IO and the signal of the enable terminal EN, in the present embodiment, the gate of the PMOS 12 is connected to the input / output terminal IO.
Is controlled only by the potential of

In the input / output circuit configured as described above, the operation of the output circuit 1 will be particularly described below.

First, in the initial state where the power supply voltage is applied for the first time, the input / output terminal IO is normally at 0V. At this time, since the gate of the NMOS 34 is connected to the power supply terminal 21, the gate is turned on, and 0 V is applied to the gates of the PMOS 32 and the PMOS 35 from the input / output terminal IO, so that the gate is turned on. Subsequently, the NMOS 38 is turned on because a signal of “H” is input to the gate of the NMOS 38 via the power supply terminal 21, the PMOS 32, and the PMOS 35. NMOS 16
Is in a conductive state because the gate is connected to the power supply terminal 21 (3.3 V). Therefore, PMOS 12, PMO
S36, the gate voltages of the PMOS 37 and the NMOS 39 are 0
V. Thereby, the PMOS 12, the PMOS 36,
Since the PMOS 37 becomes conductive and the NMOS 39 becomes cut off, the gate voltage of the NMOS 38 is stabilized at 3.3V.

The PMOS 12 is also conductive, and the NMOS 14 is also conductive. Therefore, when outputting a signal of “H” from the input / output terminal IO, the output of the NAND circuit 19 and the output of the NOR circuit 20 are both set to “L” by setting the enable terminal EN to “H” and the input terminal IN to “H”. ”, The PMOS 11 is conducting, the NMOS 1
5 is turned off, and a signal of “H” is output from the input / output terminal IO.

On the other hand, when "L" is output from the input / output terminal IO, the enable terminal EN is set to "H" and the input terminal I
By setting N to "L", the NAND circuit 19, N
Both outputs of the OR circuit 20 become “H”, and the PMOS 11
Is turned off, the NMOS 15 is turned on, and an “L” signal is output from the input / output terminal IO.

To input a signal from the input / output terminal IO,
The enable terminal EN is set to “L” to bring the output circuit 1 into a high impedance state. That is, the enable terminal EN
Is “L”, the output of the NAND circuit 19 is “H”,
The output of the NOR circuit 20 becomes "L". This allows PM
The gate of OS11 is “H” and the gate of NMOS15 is “H”.
L ", and each is in a cut-off state. Therefore, there is no current path from the input / output terminal IO, and the output circuit 1 is in a high impedance state. A signal is input from the output circuit IO to the internal circuit via the input circuit 2 and the output terminal OUT.

Further, when a voltage higher than the power supply voltage is input, for example, when the power supply voltage is 3.3 V and a 5 V signal is input, the PMOS 13 has one end higher than the gate voltage (3.3 V). Is increased (to 5 V), the PMOS 13 becomes conductive and 5
An input signal of V is propagated to the gate of the PMOS 12. As a result, the gate of the PMOS 12 is turned off at 5 V, and the current from the input / output terminal IO to the power supply terminal 21 is cut off.

Although 5 V is also propagated to the NMOS 16, the gate of the NMOS 16 is 3.3 V. Therefore, the gate voltage (3.3 V) is changed to the threshold voltage of the NMOS 16 (1 V in consideration of the back bias effect). Is applied to one end of the NMOS 38, the gate of the PMOS 37, and the gate of the NMOS 39. Therefore, the NMOS 39 is turned on. PMO
S32 is in a cutoff state because the gate is at 5V. PM
Since the OS 32 and the PMOS 36 are in the cutoff state and the NMOS 39 is in the conductive state, the gate of the NMOS 38 is at 0 V, and the NMOS 38 is in the cutoff state. Therefore, the current flowing from the input / output terminal IO through the PMOS 13 and the NMOS 16 is cut off by the NMOS 38. PM
In OS32, the gate is at 5 V, but the PMOS
The gate voltage of the PMOS 35 also becomes 2.3 V due to the effect of the NMOS 34, whereby the voltage at one end of the PMOS 32 becomes 2.3 V.
To the threshold voltage of the PMOS 35 (PMOS 35
Is 0.6 V, the voltage of the gate oxide film of the PMOS 32 is not more than 2.9 V).
Only 1V.

If the input / output terminal is 3.3 V in the initial state when the power supply voltage is applied for the first time, PM
Since the OS 32 is in the cutoff state, the state of the output circuit 1 is undefined. In such a case, first, from the input / output terminal IO,
Outputting a signal of L ″ or inserting a high-resistance pull-up resistor in the gate of the NMOS 38 can solve the above-mentioned indefinite state.

According to the above configuration, the input / output terminal I
When a signal is output from O to the outside, the PMOS 12 is always in a conductive state, and the signal from the input terminal IN is NAND.
Since the signal is output from the input / output terminal IO through the circuit 19, the PMOS 11, and the PMOS 12, the delay time can be shorter than that of the conventional output circuit.

Further, since only the PMOS 11 is driven by the NAND circuit 19, it is not necessary to increase the transistor size of the NAND circuit 19, which can contribute to the high integration of the LSI. Further, the load driven by the NAND circuit 19 is small, and the transistor size itself of the NAND circuit 19 is also small, which is effective in reducing power consumption.

Further, the present embodiment has the following effects which are not provided by the first embodiment. That is, in the first embodiment, when the voltage of the enable terminal EN is kept at "H", the first NMOS 17 is in a conductive state, so that a signal having a voltage exceeding the power supply voltage is input to the input / output terminal IO. At this time, the PMOS 13 and the NMO
In S16, a current path is formed to reach the ground terminal 22 via the NMOS 17, and an unnecessary current flows. However, in the present embodiment, even when the voltage of the enable terminal EN remains “H”, when a signal having a voltage exceeding the power supply voltage is input to the input / output terminal IO, the gate control circuit 41 First
Of the PMOS 13, NMOS 16, and NMOS 3 from the input / output terminal IO.
Since the current path leading to the ground terminal 22 via 8 is cut off, unnecessary current does not flow. Therefore, according to the configuration of the present embodiment, a signal having a voltage higher than the power supply voltage can be input without using an enable signal.
Even in an output circuit that cannot be made high impedance without N, the output circuit 1 can be protected when a voltage higher than the power supply voltage is applied.

When the withstand voltage of each transistor constituting the output circuit 1 is 5 V and only the power supply voltage is 3.3 V, the NMOS 14, NMOS 16, NMOS 34, PM
The OS 35 and the PMOS 36 need not always be provided.

The PMOS 11, PMOS 12, PM
The substrate of the OS 13 may be connected to the input / output terminal IO as in the conventional example. However, as in this embodiment, the PMOS
When connected to the power supply terminal 21 via 31, the voltage of the substrate fluctuates from 0 V to 5 V in the conventional example, while the fluctuation width of the substrate voltage has a small amplitude from 3.3 V to 5 V in the present embodiment. Therefore, power consumption can be reduced.

In the first and second embodiments,
The first and third voltage drop circuits are constituted by N-channel MOS transistors 16 and 34 whose gates are used as power supply voltages. In the second embodiment, the second voltage drop circuit uses the gate as the power supply voltage. Although the P-channel MOS transistor 37 described below was used, the configuration of each voltage drop circuit may be a diode D as shown in FIG. 4A, or a configuration as shown in FIG. , (C), (d), the N-channel MOS transistor 16,
It goes without saying that any configuration such as the P-channel MOS transistor 37 or a circuit in which a plurality of diodes D are connected in series may be employed.

[0097]

As described above, according to the output circuit of the present invention, even when a signal having a voltage higher than the power supply voltage is input, unnecessary current is generated and the gate oxide film is destroyed. Thus, an output circuit having a shorter delay time than before can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an input / output circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an input / output circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional input / output circuit.

FIG. 4 is a diagram showing a modified example of the voltage drop circuit provided in the input / output circuit according to the first and second embodiments of the present invention.

[Explanation of symbols]

IN input terminal OUT output terminal EN enable terminal IO input / output terminal 1 output circuit 2 input circuit 11 second P-channel MOS transistor 12 first P-channel MOS transistor 13 third P-channel MOS transistor 16 N-channel type MOS transistor (voltage drop circuit and first voltage drop circuit) 17 first N-channel MOS transistor 19 NAND circuit 20 NOR circuit 21 power supply terminal 22 ground terminal 31 fourth and seventh P-channel MOS transistors 32 fifth 33 P-channel MOS transistor 33 Third voltage drop circuit 34 N-channel MOS transistor 35 Sixth P-channel MOS transistor 36 Fourth P-channel MOS transistor 37 P-channel MOS transistor (second
38) First N-channel MOS transistor 39 Second N-channel MOS transistor 40, 41 Gate control circuit

Claims (15)

[Claims] 1. An output circuit having an input / output terminal, a first P-channel MOS transistor having one end connected to the input / output terminal, and a series connected to the other end of the first P-channel MOS transistor. A second P-channel MOS transistor connected to the first P-channel MOS transistor connected to the input / output terminal;
A gate control circuit for controlling a gate voltage of an OS transistor, wherein a signal is input to a gate of the second P-channel MOS transistor, and a signal is output from the input / output terminal according to the input signal. Output circuit. 2. The gate control circuit, when output is enabled, lowering a gate voltage of the first P-channel MOS transistor below a power supply voltage to make the first P-channel MOS transistor conductive, On the other hand, when the output is disabled, when the voltage of the input / output terminal exceeds the power supply voltage, the gate of the first P-channel type MOS transistor is connected to the input / output terminal and the first
2. The output circuit according to claim 1, wherein said P-channel MOS transistor is turned off. 3. The gate control circuit has a third P-channel MOS transistor and a first N-channel MOS transistor, and one end of the third P-channel MOS transistor is connected to the input / output terminal. The other end is connected to the gate of the first P-channel MOS transistor, the gate voltage is set to the power supply voltage, and the first N-channel MOS transistor has one end connected to the first P-channel MOS transistor. 2. The output circuit according to claim 1, wherein the output circuit is connected to a gate of the transistor, a voltage at the other end is equal to or lower than a ground voltage or a power supply voltage, and an enable signal is input to the gate. 4. The gate control circuit has a voltage drop circuit, wherein the voltage drop circuit is provided between a gate of the first P-channel MOS transistor and the one end of the first N-channel MOS transistor. 4. The output circuit according to claim 3, wherein the output circuit is arranged between the output circuits. 5. Separately, there is provided a fourth P-channel MOS transistor, wherein the fourth P-channel MOS transistor has a power supply voltage at one end and a power supply voltage at the other end. 3
Connected to the substrate of the P-channel MOS transistor of
4. The output circuit according to claim 3, wherein a gate is connected to the input / output terminal. 6. The gate control circuit, wherein a voltage of the input / output terminal is equal to or lower than a power supply voltage,
The gate voltage of the P-channel MOS transistor is made lower than the power supply voltage to make the first P-channel MOS transistor conductive. On the other hand, when the voltage of the input / output terminal exceeds the power supply voltage, the first 2. The output circuit according to claim 1, wherein a gate of the P-channel MOS transistor is connected to the input / output terminal to shut off the first P-channel MOS transistor. 7. The gate control circuit comprises: a third and a fourth P-channel MOS transistor;
And one end of the third P-channel MOS transistor, one end of the first N-channel MOS transistor, and a gate of the second N-channel MOS transistor. Are connected to the gate of the first P-channel MOS transistor, respectively, and the fourth P-channel MOS transistor has one end connected to the gate of the first N-channel MOS transistor and the second N-channel MOS transistor. The third P-channel MOS transistor is connected to one end of the transistor, the other end is set to the power supply voltage, the third P-channel MOS transistor is set to the gate voltage as the power supply voltage, and one end is connected to the gate of the fourth P-channel MOS transistor The output circuit according to claim 6, wherein the output circuit is connected to the input / output terminal, and the other end is connected to the input / output terminal. 8. The gate control circuit has a fifth P-channel MOS transistor, wherein the fifth P-channel MOS transistor has a gate connected to the input / output terminal and one end connected to the second P-channel MOS transistor. 8. The output circuit according to claim 7, wherein the output circuit is connected to one end of the N-channel MOS transistor, and the voltage at the other end is a power supply voltage. 9. The gate control circuit includes a first and a second voltage drop circuit, wherein the first voltage drop circuit includes the first P-channel type M
The gate of the OS transistor and the first N-channel type M
The second voltage drop circuit is disposed between one end of the OS transistor and the fourth P-channel type M
One end of the OS transistor and the first N-channel type M
The gate of the OS transistor and the second N-channel type M
9. The output circuit according to claim 7, wherein the output circuit is arranged between the one end of the OS transistor and a connection point. 10. The gate control circuit has a third voltage drop circuit, and the third voltage drop circuit has a circuit portion performing a voltage drop function and a sixth P-channel MOS transistor. The sixth P-channel MOS transistor has one end connected to one end of the fifth P-channel MOS transistor, and the other end connected to the gate of the first N-channel MOS transistor and the second N-channel MOS transistor. 10. The output circuit according to claim 9, wherein the output circuit is connected to the connection point with one end of the type MOS transistor, and a gate is connected to the input / output terminal via a circuit portion performing the voltage drop function. 11. A seventh P-channel MOS transistor, wherein the seventh P-channel MOS transistor has a power supply voltage at one end and a power supply voltage at the other end. 3
Connected to the substrate of the P-channel MOS transistor of
The output circuit according to claim 7, wherein a gate is connected to the input / output terminal. 12. The voltage drop circuit is configured by an N-channel MOS transistor whose gate is a power supply voltage, a P-channel MOS transistor whose gate is lower than the power supply voltage, a diode, or a circuit in which a plurality of these are connected in series. The output circuit according to claim 4, wherein: 13. The first voltage drop circuit includes an N-channel MOS transistor having a gate as a power supply voltage, a P-channel MOS transistor having a gate at a power supply voltage or less, a diode, or a circuit in which a plurality of these are connected in series. The output circuit according to claim 9, wherein the output circuit comprises: 14. The second voltage drop circuit, wherein: an N-channel type MOS transistor whose gate is a power supply voltage; a P-channel type MOS transistor whose gate is lower than the power supply voltage; a diode; or a circuit in which a plurality of these are connected in series The output circuit according to claim 9, wherein the output circuit comprises: 15. The third voltage drop circuit includes an N-channel MOS transistor having a gate as a power supply voltage, a P-channel MOS transistor having a gate at a power supply voltage or less, a diode, or a circuit in which a plurality of these are connected in series. The output circuit according to claim 10, wherein: