JPH10154924A - Cmos hysteresis circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the hysteresis circuit with a simple configuration in which current consumption by a through-current is reduced. SOLUTION: The CMOS hysteresis circuit 10 is configured such that PMOS transistors(TRs) 11, 12 and NMOS TRs 13, 14 are connected in series between a power supply voltage and a reference potential, respective gates are connected in common to an input terminal IN, a connecting point of the PMOS TR 12 and the NMOS TR 13 is connected to an output terminal OUT via an inverter circuit 15, a PMOS TR 16 and an NMOS TR 17 are connected respectively in parallel with the PMOS TR 11 and the NMOS TR 14 and gates of the PMOS TR 16 and the NMOS TR, 17 are connected to the output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS hysteresis circuit, and more particularly, to a CMOS integrated circuit CMO.
The present invention relates to a circuit configuration of an S hysteresis circuit.

[0002]

2. Description of the Related Art In portable electric equipment or the like that operates using a battery or the like as a power source, a semiconductor integrated circuit device (hereinafter abbreviated as "CMOS IC") based on CMOS technology that can easily reduce power consumption in order to extend the operable time is used. In many cases, a hysteresis circuit having a hysteresis characteristic (also referred to as a “Schmitt trigger circuit”) is often used for an input circuit or the like in order to prevent chattering and noise mixing.

As such a hysteresis circuit, a hysteresis circuit including a gate circuit using a plurality of input circuits having different threshold voltages, and a hysteresis circuit disclosed in Japanese Patent Application Laid-Open No. Sho 56-725 are disclosed.
An output feedback type hysteresis circuit such as 22 is generally used.

[0004]

However, the above-mentioned hysteresis circuit based on the gate circuit tends to have a large circuit size and a large chip size, and has a power supply when the input voltage is near the threshold voltage due to a gradual change of the input signal. The consumption current tends to increase due to the flow of the through current between the voltage and the reference potential. Although the output feedback hysteresis circuit can be reduced in circuit scale, the current consumption tends to increase due to the through current when the input voltage is near the threshold voltage.

Accordingly, an object of the present invention is to solve these problems and to provide a hysteresis circuit having a simple configuration capable of reducing current consumption due to through current.

[0006]

In order to solve the above-mentioned problem, a CMOS hysteresis circuit according to the first aspect of the present invention comprises first and second PMOS transistors (11, 1).
2) and first and second NMOS transistors (13, 1
4) are connected in series between the power supply voltage and the reference potential, and their gates are commonly connected to the input terminal (IN), and the first PMOS transistor (12) and the first
Is connected to the output terminal (OUT) via the inverter circuit (15), and the second PMOS transistor (11) and the second N
The MOS transistor (14) includes a third PMOS transistor (16) and a third NMOS transistor (1
7) are connected in parallel, and the gates of the third PMOS transistor and the third NMOS transistor are connected to the output terminal.

According to a second aspect of the present invention, there is provided a CMOS hysteresis circuit according to the first aspect, wherein the driving capability of the second MOS transistors (11, 14) is equal to that of the first MOS transistors (12, 13). Or the third M
It is characterized in that it is set lower than the driving capability of the OS transistors (16, 17). By adopting the circuit configuration as in the present invention, the CMOS hysteresis circuit according to the first and second aspects of the present invention provides a large through-hole by a MOS transistor having a small driving capability even when the input voltage is near each threshold voltage having a hysteresis characteristic. Current does not flow between the power supply voltage and the reference potential.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. In this specification, the same or similar circuit elements are denoted by the same reference numerals throughout the drawings to simplify the description. FIG. 1 shows a C according to the invention.
2 shows a circuit configuration of a hysteresis circuit having a MOS configuration, and FIG.
Indicates its input / output characteristics. In FIG. 1, IN indicates an input terminal connected to a terminal of a semiconductor integrated circuit device or an output of another circuit, and OUT indicates an output terminal connected to an input of another circuit. A MOS transistor having a high driving capability is a MOS transistor having a larger channel width when the channel length is the same, or a MOS transistor having a shorter channel length when the channel width is the same. A smaller transistor.

The CMOS hysteresis circuit 10 shown in FIG.
P-channel MOS transistor (hereinafter "PMOS")
11 and 12 and N-channel MOS transistors (hereinafter abbreviated as “NMOS”) 13 and 14 are connected in series between a power supply voltage (VDD) and a reference potential (GND), and have respective gates. Are commonly connected to an input terminal IN, and a connection point between the PMOS 12 and the NMOS 13 is connected to an output terminal OUT via an inverter circuit 15;
The MOS 16 and the NMOS 14 have PMOS 16 and NM, respectively.
The OSs 17 are connected in parallel, and the gates of the PMOS 16 and the NMOS 17 are connected to the output terminal OUT.

The driving capability of each MOS transistor is set such that the PMOS 12 has the highest driving capability and the PMOS 11 has the lowest driving capability in a PMOS. Similarly, in the NMOS, the driving capability of the NMOS 13 is set to be the highest, and the driving capability of the NMOS 13 and the NMOS 14 is set to be lower in the following. With such a configuration, the hysteresis width can be easily changed by changing the drive capability of the PMOS 16 or the NMOS 17 by changing the channel width or the like.

The circuit operation will be described with reference to FIGS. In the following description, the voltage input to the input terminal IN is the input voltage, the voltage output from the output terminal OUT is the output voltage, and the threshold voltages on the high and low levels of the hysteresis characteristic are VTH (V) and VTH (V), respectively. V
TL (V), the input voltage of the inverter circuit 15 is the input level, the input threshold voltage of the inverter circuit 15 is VT (V), and the PMOS element threshold voltage is V
TP (V), NMOS element threshold voltage to VTN
(V). Arrows in FIG. 2 indicate the directions of changes in the output voltage.

First, the circuit state when the input voltage is the reference voltage will be described. When the input voltage is at the reference potential,
Since the PMOS 11 and the PMOS 12 are in the conductive state and the NMOS 13 and the NMOS 14 are in the cut-off state, the input level of the inverter circuit 15 is the power supply voltage. Accordingly, the voltages of the inverter circuit 15 and the output terminal OUT become the reference potential, the PMOS 16 becomes conductive and the NMOS 17 becomes cut off, so that no current flows from the power supply voltage to the reference potential.

Next, the case where the input voltage rises from the reference potential to the power supply voltage will be described. Until the input voltage reaches VTH (part a in FIG. 2), the PMOS 11 and the PMOS 12
The continuity resistance of the NM gradually increases with an increase in the input voltage.
The conduction resistance of the OS 13 and the NMOS 14 gradually decreases. During this time, the PMOS 11, the PMOS 12, and the PMOS 12
Since the input level of the inverter circuit 15 is higher than the voltage divided by the combined resistance of the NMOS 16 and the NMOS 13 and the NMOS 14, the output voltage does not change and the states of the PMOS 16 and the NMOS 17 do not change. When the input voltage approaches VTH, the input level of the inverter circuit 15 divided by each MOS transistor becomes substantially VT.

The input voltage further rises and exceeds VTH (FIG. 2)
B → c section) and the input level of the inverter circuit 15 is VT
, The output voltage of the inverter circuit 15 is inverted to a high level, the PMOS 16 is turned off, and N
Since the MOS 17 becomes conductive, the inverter circuit 15
Of the inverter circuit 15 rapidly decreases, and the input voltage must be reduced to VTL in order to bring the input level of the inverter circuit 15 back to near VT. Then, as the input voltage approaches the power supply voltage, the conduction resistance of the PMOS 11 and the PMOS 12 further increases, and the NMOS 13 and the NMO
When the conduction resistance of S14 further decreases and the input voltage is equal to or more than (power supply voltage -VTP), the PMOS 11 and the PMOS 1
2 is turned off, the input level of the inverter circuit 15 is substantially the reference potential, the inverter circuit 15 and the output terminal OUT.
Is approximately the power supply voltage.

When the input voltage is VTH, the PMOS
11, the combined resistance value of the PMOS 12 and the PMOS 16 is
Compared to the resistance values of PMOS 11 and PMOS 12, PMO
Since the resistance value of S16 is sufficiently small, the resistance value of the PMOS 12 can be approximately approximated. At this time, the combined resistance of each MOS transistor is minimized, so that the through current flowing between the power supply voltage and the reference potential is maximized. However, the driving capability of the NMOS 14 is reduced as compared with other MOS transistors to reduce the resistance. Since the value is set to be large, only a small through current flows as compared with the conventional case.

Next, a case where the input voltage decreases from the power supply voltage to the reference potential will be described. However, the state until the input voltage changes from the power supply voltage to VTL (portion c in FIG. 2) and from VTL to the reference potential (portion a in FIG. 2) is the same as the above-described state description, and thus the description is omitted. When the input voltage approaches VTL, the input level of the inverter circuit 15 divided by each MOS transistor becomes substantially VT. When the input voltage further decreases and falls below VTL (d → a in FIG. 2), the input voltage of the inverter circuit 15 falls below VT, so that the output voltage of the inverter circuit 15 is inverted and becomes low.
Since the MOS 16 is turned on and the NMOS 17 is turned off, the input level of the inverter circuit 15 rises sharply, and the input voltage must be raised to VTH in order to bring the input level of the inverter circuit 15 close to VT again. Disappears. Then, as the input voltage approaches the reference potential, the conduction resistance of the PMOS 11 and the PMOS 12 further decreases, and the conduction resistance of the NMOS 13 and the NMOS 14 further increases. When the input voltage is equal to or lower than (reference potential + VTN), the NMOS 13 and the NMOS 14 are cut off. And the input level of the inverter circuit 15 is approximately the power supply voltage,
The output voltages of the inverter circuit 15 and the output terminal OUT are substantially at the reference potential.

When the input voltage is about VTL, NM
The combined resistance of OS13, NMOS14 and NMOS17 is N compared to the resistance of NMOS13 and NMOS14.
Since the resistance value of the MOS 17 is sufficiently small, the resistance value of the MOS 13 can be approximately approximated. At this time, since the combined resistance of the MOS transistors is minimized, the through current flowing between the power supply voltage and the reference potential is maximized.
Since the resistance value is increased by lowering the driving capability of the first device, only a small through current flows as compared with the prior art.

When the input voltage rises from the reference potential to the power supply voltage by such a circuit operation, a → b →
When the output voltage changes along c and the input voltage decreases from the power supply voltage to the reference potential, a hysteresis characteristic in which the output voltage changes along c → d → a in FIG. 2 is obtained. . The hysteresis circuit 20 of FIG. 3 shows another embodiment of the present invention, and is different from the circuit of FIG.
The configuration is such that the output feedback by 17 is eliminated. With such a configuration, the low-level hysteresis voltage V
TL 'is higher than the VTL of the circuit of FIG. 1 and a hysteresis circuit having a hysteresis width smaller than that of the circuit of FIG. 1 can be formed. It is needless to say that a similar effect can be obtained even in a configuration in which the output feedback by the PMOS 16 is eliminated from the circuit of FIG.

[0019]

As described above, according to the present invention, the CMOS hysteresis circuit according to the first and second aspects of the present invention provides a MOS hysteresis circuit having a small driving capability even when the input voltage is near each threshold voltage having a hysteresis characteristic. Since a large through current does not flow between the power supply voltage and the reference potential by the transistor, the current consumption of the semiconductor integrated circuit can be reduced, and the operation time of a device using a battery or the like can be extended. There is. In particular, when the circuit of the present invention is used for a semiconductor integrated circuit in which a large number of hysteresis circuits are used, a voltage near each threshold voltage of the hysteresis characteristic is frequently input, or a signal whose input voltage varies greatly is input, Effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;

FIG. 2 is an explanatory diagram showing input / output characteristics of the embodiment of the present invention;

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

 10, 20: CMOS hysteresis circuit 11, 12, 16: PMOS 13, 14, 17: NMOS 15: inverter circuit IN: input terminal OUT: output terminal

Claims (2)

[Claims] 1. A first and a second PMOS transistor and a first and a second NMOS transistor are connected in series between a power supply voltage and a reference potential, and respective gates are commonly connected to an input terminal. , A connection point between the first PMOS transistor and the first NMOS transistor is connected to an output terminal via an inverter circuit, and the second PM transistor
A third PMOS transistor and a third NMOS transistor are respectively connected in parallel to the OS transistor and the second NMOS transistor, and gates of the third PMOS transistor and the third NMOS transistor are connected to an output terminal. A CMOS hysteresis circuit. 2. The CMOS hysteresis circuit according to claim 2, wherein
2. The CMOS hysteresis circuit according to claim 1, wherein the driving capability of the MOS transistor is set lower than the driving capability of the first MOS transistor or the third MOS transistor.