JP2005260602A - High hysteresis width input circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems of a conventional high hysteresis width input circuit that the hysteresis width is extremely small when a power supply voltage is decreased in the conventional method wherein a β ratio of an inverter circuit comprising a P-type MOSFET and an N-type MOSFET is changed to equivalently produce a hysteresis of a logic level, and that the operation of the circuit is susceptible to variations in the manufacturing process because the setting of a shape ratio is rather insufficient because the P and N type MOSFETs are employed to form the logic level. <P>SOLUTION: The hysteresis characteristic is obtained by providing an N type MOSFET connected to a positive power supply and a P type MOSFET connected to a negative power supply in parallel with a CMOS inverter circuit as an input circuit and passing an output signal of the CMOS inverter circuit and the circuit comprising the P type MOSFET and the N type MOSFET through a buffer circuit to turn ON / OFF the MOSFETs. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), the present invention provides noise when an input signal of an input circuit transits from a high potential to a low potential or from a low potential to a high potential. The present invention relates to a circuit configuration in which hysteresis characteristics are provided at a logic level in order to eliminate malfunctions and instabilities caused by the above, and a circuit configuration that ensures a sufficiently large hysteresis width even when a power supply voltage is lowered.

  Conventionally, an input signal terminal of an integrated circuit, particularly a digital circuit, has a difference between the rising and falling edges of the input signal in the logic level for determining a signal change in order to eliminate malfunction and instability due to noise. It is widely used to use a hysteresis input circuit having a hysteresis characteristic. However, in recent years, when an integrated circuit is miniaturized and a low power supply voltage is used with a decrease in breakdown voltage, a sufficient hysteresis width cannot be secured.

The conventional circuit will be described below. An input circuit having a general hysteresis in a conventional MOS integrated circuit constitutes a circuit equivalent to an inverter circuit, is always controlled by an input signal, and is a large factor that determines the logic level of the conductance constant of a P-type MOSFET. Two ratios of conductance constants β _N of β _P and N-type MOSFETs were provided, and a circuit configuration was adopted in which the ratio of the two types of β _P and β _N was changed according to the previous state.

  For example, FIG. 5 shows a first conventional circuit example, a first logic level determined by P-type MOSFETs 501 and 503 and N-type MOSFET 502, and a second logic determined by N-type MOSFETs 502 and 504 and P-type MOSFET 501. The inverter circuit 507, the P-type MOSFET 505, and the N-type MOSFET 506 have different hysteresis levels by using the first logic level and the second logic level according to the previous state.

  FIG. 6 shows a second conventional circuit example, which is shown in Patent Document 1. In FIG. 6, the first logic level determined by the P-type MOSFETs 601, 603, 605 and the N-type MOSFETs 602, 604 and the second logic level determined by the N-type MOSFETs 602, 604, 606 and the P-type MOSFETs 601, 603 are shown. With the inverter circuit 607, the P-type MOSFET 605, and the N-type MOSFET 606, the first logic level and the second logic level described above are selectively used according to the previous state to create a hysteresis characteristic.

  FIG. 7 shows a third conventional circuit example, which is shown in Patent Document 2. In FIG. 7, a first logic level determined by P-type MOSFETs 701, 703, 705 and N-type MOSFETs 702, 704, and a second logic level determined by N-type MOSFETs 702, 704, 706 and P-type MOSFETs 701, 703 are shown. With the inverter circuit 707, the P-type MOSFET 705, and the N-type MOSFET 706, the first logic level and the second logic level described above are selectively used according to the previous state to create a hysteresis characteristic.

  FIG. 8 shows a fourth conventional circuit example, which is shown in Patent Document 3. In FIG. 8, the first logic level determined by the P-type MOSFETs 811 and 815 and the N-type MOSFET 812 and the second logic level determined by the N-type MOSFETs 814 and 816 and the P-type MOSFET 813 are provided. NAND circuits 817 and 819 The latch circuit 824, the P-type MOSFET 815, and the N-type MOSFET 816 configured by the inverter circuit 819 use the first logic level and the second logic level, depending on the previous state, to create hysteresis characteristics.

Patent Publication Sho 58-182914 (Representative)

Patent Publication 10-154924 (Representative) Patent Publication 11-27114 (Representative)

  However, the conventional hysteresis input circuit has the following problems. As an equivalent circuit for forming the first and second logic levels of the circuits shown in FIGS. 5, 6, and 7, which are the conventional input circuits having hysteresis, the P-type MOSFET and the N-type MOSFET shown in FIG. This results in an inverter circuit.

As shown in FIG. 4, the logic level of the inverter circuit is such that the conductance constants of the P-type MOSFET and N-type MOSFET are β _P and β _N , the threshold voltages are V _TP and V _TN , respectively, and the power supply voltage is V _DD , when the reference ground potential is 0 and the logic level is V _GL , the driving current capability of the P-type MOSFET and the N-type MOSFET is antagonized at the logic level.
1/2 · β _P (V _DD −V _GL −V _TP ) ² = 1/2 · β _N (V _GL −V _TN ) ²
By solving this, the lock level V _GL becomes V _GL = {V _DD −V _TP + (β _N / β _P ) ^1/2 · V _TN } / {1+ (β _N / β _P ) ^{1 / 2} }
It becomes. Therefore, if the shape of the P-type MOSFET and the N-type MOSFET are variously changed and the conductance constant ratio (β _N / β _P ) is changed from 0 to infinity, the logic level changes within the following range.

_{V TN <V GL <V DD} -V TP
At this time, when the higher logic level V _IH is (β _N / β _P ) 0, V _IH = V _DD −V _TP
And the lower logic level V _IL is when (β _N / β _P ) is infinite, V _IL = V _TN
It is. Therefore, the hysteresis width V _WHL is V _WHL = V _DD −V _TP −V _TN
It becomes. However, since it is impossible in practice to set (β _N / β _P ) to 0 or infinity, the hysteresis width is actually smaller than this. Thus the power supply voltage _{V DD} is low voltage, for example because when becomes about 1.5V is _{V TP} and _{V TN} is about 0.7V from 0.5V hysteresis width becomes very small, not fulfill its original purpose. This is shown in FIG. In FIG. 3, the N-type MOSFET does not operate when 0 ≦ V _IN ≦ V _TN , and the P-type MOSFET does not operate when V _DD −V _TP ≦ V _IN ≦ V _DD , so that the logic level of the inverter circuit is V _TN < The range is limited to V _IN <V _DD −V _TP . Since the threshold voltages V _TP and V _TN do not fluctuate during operation, the logic level range (V _DD −V _TP −V _TN ) is narrowed when the power supply voltage V _DD is lowered, and the width of the hysteresis is greatly reduced as the power supply voltage is lowered. Get smaller.

  Therefore, the conventional hysteresis input circuit in which the equivalent circuits as shown in FIGS. 5, 6, and 7 are reduced to the inverter circuit has a problem that the hysteresis width cannot be sufficiently obtained when the voltage becomes low.

In addition, when (β _N / β _P ) is set in an attempt to secure a little hysteresis width during low voltage operation, the shape of the P-type MOSFET or N-type MOSFET needs to be changed unnaturally. There is a problem that a large chip area is occupied or the driving ability is reduced to reduce the response.

Further, in the fourth conventional example of FIG. 8, since the input terminal 820 is not connected to the gate electrodes of the P-type MOSFET 815 and the N-type MOSFET 816, the equivalent circuit of the inverter circuit of FIG. There are no level restrictions. However, the first logic level is effectively determined by the N-type MOSFET 812 and the P-type MOSFET 815 under the design conditions for which it is desired to ensure the hysteresis width, and the following problems arise. In FIG. 8, conductance constants of P-type MOSFET 815 and N-type MOSFET 812 are β _P and β _N , respectively, and threshold voltages are V _TP and V _TN , respectively. If the power supply voltage V _DD , the reference ground potential 0, and the logic level are V _GL , then approximately V _IL ≈ (V _DD −V _TP ) − (β _N / β _P ) ^1/2 · (V _DD -V _TN)
It becomes. Here, if the value of (β _P / β _N ) is changed from 0 to infinity, −∞ ≦ V _IL ≦ V _DD −V _TP
It can be set to a range exceeding the power supply potential. Further, at this time, (β _N / β _P ) ^1/2 = (V _DD −V _TP ) / (V _DD −V _TN )
When set to V _IL ≒ 0
Next is a method of spread compared to the lower limit of the V _IL inverter circuit described above has only to V _TN. However, at this time, as a condition for setting the second logic level _VIL ,
The point of setting the ratio between (β _N / β _P ) ^1/2 and (V _DD −V _TP ) / (V _DD −V _TN ) is the point, but between the different properties of P-type MOSFET and N-type MOSFET Since this is a setting, it is somewhat impossible to extend the hysteresis to the limit when considering manufacturing variations. Further, as can be understood from the equation of −∞ ≦ V _IL ≦ V _DD −V _TP , the V _IL is set too low so as to be understood from the expression of the input terminal 820 when V _IL becomes less than 0 due to variations in mass production. However, there is a risk that the recovery of the operation becomes impossible even if the signal potential is kept latched even if the range of the power supply voltage is changed. Even when the first logic level V _{IH is} set, if there is an excessive setting in order to ensure the same hysteresis width, there is a risk that V _IH will exceed V _DD and that the operation cannot be recovered while latched. There was a problem of being involved.

The present invention solves such problems, and an object of the present invention is to provide a hysteresis input circuit having a relatively large hysteresis width even at a low voltage.

  It is another object of the present invention to provide a circuit capable of realizing an input circuit having a relatively large hysteresis width with an appropriate chip area.

  In addition, when setting the first logic level and the second logic level that determine the hysteresis characteristics, the setting is made according to the β ratio between the MOSFETs of the same type, enabling the setting of a marginal limit, and large hysteresis. An object of the present invention is to provide a hysteresis input circuit that secures a width and does not cause an inoperable situation due to manufacturing variations.

  In the high hysteresis width input circuit of the present invention, a second N-type MOSFET is added in parallel to the positive power supply side and a second P-type MOSFET is added in parallel to the negative power supply side to the inverter circuit controlled by the input signal. The output of the inverter circuit is connected to the gate electrodes of the second N-type MOSFET and the second P-type MOSFET via a buffer circuit, and the previous state is reflected on the logic level. To do.

According to the above configuration, the logic level is not only the (β _N / β _P ) ratio of the inverter circuit controlled only by the input signal but also the overall effect of the β ratio of the MOSFET that is turned on (ON) by the previous state. Therefore, the above-described limitation on the logic level of the inverter circuit is released, and the range in which the logic level can be set is increased.

  Further, the main element for setting the logic level is the β ratio of the MOSFETs of the same type, that is, the shape ratio, and the conditions can be set with certainty, so that there is an effect that the influence of variations and variations in the manufacturing process is reduced.

  Further, since the β ratio is set to the same type of MOSFET and is set reliably, there is an effect that the risk of entering the latch state forever due to the difference between the design and the actual process can be eliminated.

In addition, since it is easy to set the logic level value without forcibly setting (β _N / β _P ) of the inverter circuit to an extreme value, an extreme MOSFET shape is not required, and a circuit having an appropriate chip area. Is effective.

  From the above, it is possible to stably provide a hysteresis input circuit having a large hysteresis width and being resistant to noise even when the voltage is lowered.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, 1 is a P-type MOSFET, and a source electrode is connected to a positive power source + V _DD . 2 is an N-type MOSFET, the source electrode is connected to the power supply _{-V SS} of the negative electrode. The gate electrodes of the P-type MOSFET 1 and the N-type MOSFET 2 are connected to each other, and the drain electrodes are also connected to each other to constitute an inverter circuit. Reference numeral 3 denotes an N-type MOSFET, the drain electrode is connected to the positive power supply + V _DD , and the source electrode is connected to the drain electrode of the P-type MOSFET 1. 4 is a P-type MOSFET, the drain electrode is connected to a power supply _{-V SS} of the negative electrode, the source electrode is connected to the drain electrode of the N-type MOSFET 2. Reference numerals 5 and 6 denote inverter circuits in which a P-type MOSFET and an N-type MOSFET are configured in a complementary manner as shown in FIG. Returning to FIG. 1, the buffer circuit 12 is configured by connecting the inverter circuit 5 and the inverter circuit 6 in two stages. The output of the buffer circuit 12 is connected to the gates of the N-type MOSFET 3 and the P-type MOSFET 4. An input terminal 10 as a hysteresis circuit is connected to gate electrodes of the P-type MOSFET 1 and the N-type MOSFET 2. The output terminal 11 as a hysteresis circuit is connected to the output of the buffer circuit 12.

  Assume that the input terminal 10 is initially at a low potential (Low). At this time, the output of the inverter circuit composed of the P-type MOSFET 1 and the N-type MOSFET 2 is high potential (High), the output 11 of the buffer circuit 12 is high potential, the N-type MOSFET 3 is on (ON), and the P-type MOSFET 4 is off. (OFF).

  Next, when the signal potential at the input terminal 10 gradually increases, a competition occurs between the total driving capability of the P-type MOSFET 1 and the N-type MOSFET 3 and the driving capability of the N-type MOSFET 2. When the driving capability of the N-type MOSFET 2 is won, the output of the inverter circuit composed of the P-type MOSFET 1 and the N-type MOSFET 2 changes from a high potential to a low potential, and the output 11 of the buffer circuit 12 also changes from a high potential to a low potential. . As a result, the N-type MOSFET 3 is turned off and the P-type MOSFET 4 is turned on.

  Next, when the signal potential of the input terminal 10 is changed from a high potential to a low potential, the N-type MOSFET 3 is in the off state and the P-type MOSFET 4 is in the on state, so that the N-type MOSFET 2 and the P-type MOSFET 4 This is a competition between the total drive capability of the P-type MOSFET 1 and the drive capability of the P-type MOSFET 1. When the driving capability of the P-type MOSFET 1 is won, the output of the inverter circuit composed of the P-type MOSFET 1 and the N-type MOSFET 2 changes from a low potential to a high potential, and the output 11 of the buffer circuit 12 also changes from a low potential to a high potential. As a result, the N-type MOSFET 3 is turned on again and the P-type MOSFET 4 is turned off.

  The difference between ON and OFF of the N-type MOSFET 3 and the P-type MOSFET 4 is a factor that causes a logic level hysteresis characteristic.

  Next, the hysteresis characteristic will be considered more specifically. Since the buffer circuit 12 is composed of a two-stage inverter circuit, even if the input potential of the buffer circuit is an intermediate potential, the output 11 of the buffer circuit has a high potential or a level as long as it does not exceed the logic level as the buffer circuit. It swings to the power supply potential at a low potential.

Now, the conductance constants of the P-type MOSFET 1 and the N-type MOSFETs 2 and 3 are β _P , β _N , β _NS , the respective threshold voltages are V _TP , V _TN , V _TN , and the power supply voltage is V _DD , The reference ground potential is set to zero. The gate electrode of the N-type MOSFET 3 is turned on by applying a high potential (V _DD ), and the source electrode is exactly half the power supply voltage (1/2 · V _DD ) at the time of transition at the logic level. If so, the logic level V _GL of the three MOSFETs satisfies Equation 1 below.

1/2 · β _P (V _DD −V _GL −V _TP ) ² + 1/2 · β _NS (1/2 · V _DD −V _TN ) ²
= 1/2 · β _N (V _GL -V _TN ) ²
The logic level V _GL (V _IH ) is set to the following conditional expression 2 in order to ensure the hysteresis width which is the original purpose and from the viewpoint of easy understanding.
V _DD −V _TP <V _GL <V _DD
Then, the P-type MOSFET 1 enters the off region,
1/2 · β _NS (1/2 · V _DD −V _TN ) ² = ½ · β _N (V _GL −V _TN ) ²
When this is solved, the following equation 3 is obtained.

_{V GL = V TN + (β} NS / β N) 1/2 · (1/2 · V DD -V TN)
Substituting Equation 3 into Conditional Expression 2 and solving it yields Conditional Expression 4 below.
(V _DD -V _TP -V _TN ) ² / (1/2 · V _DD -V _TN ) ² <(β _NS / β _N )
And,
(Β _NS / β _N ) <(V _DD −V _TN ) ² / (1/2 · V _DD −V _TN ) ²
here,
(V _DD -V _TP -V _TN ) ² / (1/2 · V _DD -V _TN ) ² <(β _NS / β _N )
Therefore, a large hysteresis width can be secured, and the following conditional expression 5
(Β _NS / β _N ) <(V _DD −V _TN ) ² / (1/2 · V _DD −V _TN ) ²
Then, since the logic level V _IH falls within the range of the power supply voltage V _DD , there is no possibility that the operation is not recovered by being locked by a circuit including the N-type MOSFET 3 and the buffer circuit 12.

If the right side of the inequality of conditional expression 5 is expressed as F5,
F5 = (V _DD −V _TN ) ² / (1/2 · V _DD −V _TN ) ²
Is realistic 0 <V _TN <1/2 · V _DD ,
4 <F5 <∞
The value of the range.
Also, if the left side of the inequality of conditional expression 4 is expressed as F4,
F4 = (V _DD −V _TP −V _TN ) ² / (1/2 · V _DD −V _TN ) ²
_Are realistic 0 <V _TN <1/2 · V _DD and 0 <V _TP <1/2 · V _DD
Then 1 <F4 <4
The value of the range.
From the above, if (β _NS / β _N ) is set to about 1 to 4, a hysteresis input circuit capable of increasing the hysteresis width to the limit can be realized. In addition, if the hysteresis width is too large, the input signal will not swing to the power supply voltage, and in order to avoid falling into the locked state, when safety is prioritized over the hysteresis width, (β _NS / β _N ) It can also be understood that it is sufficient to set 1 to about 1 or less. At this time, the logic level also includes the influence of the P-type MOSFET 1.

Setting (β _NS / β _N ) to about 1 to 4 or about 1 is a conductance constant ratio of the N-type MOSFET, that is, a shape ratio, and can be easily set. More specifically, if the channel lengths of the transistors of the N-type MOSFET 3 and the N-type MOSFET 2 are the same, the transistor width of the N-type MOSFET 3 may be set to the ratio of the transistor width of the N-type MOSFET 2.

Next, the conductance constants of the P-type MOSFETs 1 and 4 and the N-type MOSFET 2 are β _P , β _PS , β _N , the threshold voltages are V _TP , V _TP , V _TN , and the power supply voltage is V _DD , the reference ground potential is set to zero. The gate electrode of the P-type MOSFET 4 is turned on by applying a low potential (0), and the source electrode is exactly half of the power supply voltage (1/2 · V _DD ) at the time of transition at the logic level. The logic level V _GL by the three MOSFETs satisfies the equation 6 shown below.

1/2 · β _P (V _DD −V _GL −V _TP ) ² = 1/2 · β _N (V _GL −V _TN ) ²
+ 1/2 · β _PS (1/2 · V _DD −V _TP ) ²
The lock level V _GL (V _IL ) is set to the following conditional expression 7 in order to secure the hysteresis width which is the original purpose and from the viewpoint of easy understanding.
0 < _VGL < _VTN
Then, the N-type MOSFET 2 enters the off region,
1/2 · β _P (V _DD −V _GL −V _TP ) ² = 1/2 · β _PS (1/2 · V _DD −V _TP ) ²
When this is solved, the following equation 8 is obtained.

_VGL = ( _VDD - _VTP )-([beta] _PS / [beta] _P ) ^1/2 * (1/2 * _VDD - _VTP )
Substituting Equation 8 into Conditional Expression 7 and solving it yields Conditional Expression 9 below.
(V _DD -V _TP -V _TN ) ² / (1/2 · V _DD -V _TP ) ² <(β _PS / β _P )
And,
(Β _PS / β _P ) <(V _DD −V _TP ) ² / (1/2 · V _DD −V _TP ) ²
here,
(V _DD -V _TP -V _TN ) ² / (1/2 · V _DD -V _TP ) ² <(β _PS / β _P )
Therefore, a large hysteresis width can be secured, and the following conditional expression 10
(Β _PS / β _P ) <(V _DD −V _TP ) ² / (1/2 · V _DD −V _TP ) ²
Then, since the logic level V _IL falls within the range of the power supply voltage 0, the circuit including the P-type MOSFET 4 and the buffer circuit 12 is locked and the operation cannot be recovered.
If the right side of the inequality of conditional expression 10 is expressed as F10,
F10 = (V _DD −V _TP ) ² / (1/2 · V _DD −V _TP ) ²
Is realistic 0 <V _TP <1/2 · V _DD ,
4 <F10 <∞
The value of the range.
Moreover, if the left side of the inequality of conditional expression 9 is expressed as F9,
F9 = (V _DD −V _TP −V _TN ) ² / (1/2 · V _DD −V _TP ) ²
_Are realistic 0 <V _TP <1/2 · V _DD and 0 <V _TN <1/2 · V _DD
Then 1 <F9 <4
The value of the range.

From the above, if (β _PS / β _P ) is set to about 1 to 4, a hysteresis input circuit capable of taking the hysteresis width to the limit can be realized. In addition, if the hysteresis width is too large, the input signal will not swing to the power supply voltage, and in order to avoid falling into the locked state, when safety is given priority over the hysteresis width, (β _PS / β _P ) It can also be understood that it is sufficient to set 1 to about 1 or less. At this time, the logic level includes the influence of the N-type MOSFET 2.

Setting (β _PS / β _P ) to about 1 to 4 or about 1 is a conductance constant ratio of the P-type MOSFET, that is, a shape ratio, and can be easily set. More specifically, if the channel lengths of the transistors of the P-type MOSFET 4 and the P-type MOSFET 1 are the same, the transistor width of the P-type MOSFET 4 may be set to the ratio of the transistor width of the P-type MOSFET 1.

  The setting of the conductance constant β ratio between the N-type MOSFETs 2 and 3 and the P-type MOSFETs 1 and 4 is almost 1 to 4, and it is necessary to use an extremely large value or a small value as in the prior art. Absent. Therefore, since it is natural in designing the layout pattern, it can be understood that problems such as an increase in chip area and a decrease in responsiveness are not caused.

FIG. 2 shows a state in which V _IL is lower than V _TN and V _IH is higher than (V _DD −V _TP ). In FIG. 2, it can be seen from FIG. 3 that a large hysteresis width is secured.

  The present invention is not limited to the embodiment described above. For example, in FIG. 1, the buffer circuit 12 has a configuration example of two stages of inverter circuits 5 and 6, but this is merely an example. The role of the buffer circuit in FIG. 1 is to swing and fix the output potential of the buffer circuit to the power supply potential until the logic level of the buffer circuit is exceeded, even if the input signal of the buffer circuit is at an intermediate potential, as described above. . Therefore, the buffer circuit of FIG. 1 may be another circuit having the above function. For example, a four-stage inverter circuit configuration may be used, or a NAND circuit or a NOR circuit may be combined.

Further, in the setting of (β _NS / β _N ) in Conditional Expression 5 and (β _PS / β _P ) in Conditional Expression 10, the method of setting by changing the channel width of the MOSFET transistor has been described. A method of changing the length may be used. If the channel width is increased, β increases, but if the channel length is increased, β decreases.

  Although the main setting was made to increase the hysteresis width, if the hysteresis width is not required until the above method is obtained, or if a logic level exceeding the power supply voltage is set, the above conditional expression is used. It is not always necessary to be concerned. Even in that case, the circuit according to the present invention of FIG. 1 makes it easy to set the β ratio of the MOSFET, and is effective in applying an effective layout pattern design and ensuring response speed.

1 is a circuit diagram showing a first embodiment of the present invention. It is an electrical property figure which illustrated a mode with the hysteresis of the circuit of this invention. It is an electrical characteristic diagram illustrating a state of having a hysteresis of a conventional circuit. It is a circuit diagram which shows the structure of the inverter circuit used in the circuit of this invention, and a conventional circuit. It is a circuit diagram which shows the 1st example of the conventional hysteresis input circuit. It is a circuit diagram which shows the 2nd example of the conventional hysteresis input circuit. It is a circuit diagram which shows the 3rd example of the conventional hysteresis input circuit. It is a circuit diagram which shows the 4th example of the conventional hysteresis input circuit.

Explanation of symbols

1, 4, 401, 501, 503, 505, 601, 603, 605, 701, 703, 705, 811, 813, 815 ... P-type MOSFET
2, 3, 402, 502, 504, 506, 602, 604, 606, 702, 704, 706, 812, 814, 816 ... N-type MOSFET
5, 6, 507, 607, 707, 819, 822, 823 ... Inverter circuits 10, 410, 510, 610, 710, 820 ... Input terminals 11, 411, 511, 611, 711, 821 ... Output terminal 12... Buffer circuit 817, 818... NAND circuit 824... Latch circuit

Claims (4)

In a hysteresis input circuit of a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET),
A first P-type MOSFET whose source electrode is connected to a positive power supply + V _DD ;
A first N-type MOSFET whose source electrode is connected to the power supply _{-V SS} of the negative electrode,
A second N-type MOSFET whose drain electrode is connected to the positive power supply + V _DD ;
A second P-type MOSFET which has a drain electrode connected to a power supply _{-V SS} of the negative electrode,
Consisting of a buffer circuit,
The gate electrodes of the first P-type MOSFET and the first N-type MOSFET are connected to each other, and the drain electrodes are also connected to each other to form an inverter circuit.
The gate electrodes of the second N-type MOSFET and the second P-type MOSFET are connected to each other, and the source electrodes are also connected to each other to be connected to the drain electrodes of the first P-type MOSFET and the first N-type MOSFET. Connected,
The input terminal of the buffer circuit is connected to the drain electrodes of the first P-type MOSFET and the first N-type MOSFET, and the output terminal of the buffer circuit is the second N-type MOSFET and the second P-type MOSFET. Connected to each gate electrode and connected to the output terminal as a hysteresis circuit of the present invention,
A high hysteresis width input circuit, wherein the gate electrodes of the first P-type MOSFET and the first N-type MOSFET connected to each other are connected to an input terminal as a hysteresis circuit of the present invention.   2. The first and second P-type MOSFETs and the first and second N-type MOSFETs according to claim 1, wherein the conductance constant β of the second P-type MOSFET is one times the conductance constant β of the first P-type MOSFET. 4 and the conductance constant β of the second N-type MOSFET is 1 to 4 times the conductance constant β of the first N-type MOSFET.   The first and second P-type MOSFETs and the first and second N-type MOSFETs according to claim 1, wherein the conductance constant β of the first P-type MOSFET is larger than the conductance constant β of the second P-type MOSFET, A high hysteresis width input circuit, wherein the conductance constant β of the first N-type MOSFET is larger than the conductance constant β of the second N-type MOSFET. 2. The high hysteresis width input circuit according to claim 1, wherein the buffer circuit comprises a two-stage configuration of a complementary inverter circuit composed of a P-type MOSFET and an N-type MOSFET.

Images