JPH0188524U - - Google Patents
Info
- Publication number
- JPH0188524U JPH0188524U JP18552487U JP18552487U JPH0188524U JP H0188524 U JPH0188524 U JP H0188524U JP 18552487 U JP18552487 U JP 18552487U JP 18552487 U JP18552487 U JP 18552487U JP H0188524 U JPH0188524 U JP H0188524U
- Authority
- JP
- Japan
- Prior art keywords
- input
- type channel
- mos transistor
- circuit
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案のシユミツト回路、第２図は第
１図のシユミツト回路のヒステリシス特性、第３
図は従来のシユミツト回路。
１……入力端子、７……出力端子、２，４……
Ｐチヤンネル型ＭＯＳトランジスタ、３，５……
Ｎチヤンネル型ＭＯＳトランジスタ、６……イン
バータ、８……２入力ＮＡＮＤ、９……２入力Ｎ
ＯＲ、１０……選択端子。
Figure 1 shows the Schmitt circuit of the present invention, Figure 2 shows the hysteresis characteristics of the Schmitt circuit in Figure 1, and Figure 3 shows the hysteresis characteristics of the Schmitt circuit in Figure 1.
The figure shows a conventional Schmitt circuit. 1...Input terminal, 7...Output terminal, 2, 4...
P channel type MOS transistor, 3, 5...
N-channel MOS transistor, 6...Inverter, 8...2-input NAND, 9...2-input N
OR, 10...Selection terminal.
Claims (1)
型チヤンネルのＭＯＳトランジスタとを直列接続
した第１及び第２の直列回路を有し、前記第１の
直列回路の第１型及び第２型チヤンネルのＭＯＳ
トランジスタのそれぞれのゲートと入力端子を接
続し、前記第１及び第２の直列回路の第１型チヤ
ンネルのＭＯＳトランジスタと第２型チヤンネル
のＭＯＳトランジスタとの接続点とを共通に接続
し、前記接続点からインバータを介して出力を得
るシユミツト回路において、前記第２の直列回路
の第１型チヤンネルのＭＯＳトランジスタのゲー
トに前記接続点を一方の入力とする２入力ＮＡＮ
Ｄの出力を接続し、前記第２の直列回路の２型チ
ヤンネルのＭＯＳトランジスタのゲートに前記接
続点を一方の入力とする２入力ＮＯＲの出力を接
続し、前記２入力ＮＡＮＤ及び前記２入力ＮＯＲ
のそれぞれの他の入力には選択信号を入力してな
ることを特徴とするシユミツト回路。 1st type channel MOS transistor and 2nd type channel MOS transistor
MOS transistors of the first type channel and MOS transistors of the second type channel are connected in series.
The respective gates of the transistors are connected to the input terminals, and the connection points of the MOS transistors of the first type channel and the MOS transistor of the second type channel of the first and second series circuits are connected in common, and the connection point is connected in common. In a Schmitts circuit that obtains an output from a point via an inverter, a two-input NAN in which the connection point is one input to the gate of the MOS transistor of the first type channel of the second series circuit.
D, and the output of a 2-input NOR with the connection point as one input is connected to the gate of the type 2 channel MOS transistor of the second series circuit, and the output of the 2-input NAND and the 2-input NOR are connected.
A Schmitt circuit characterized in that a selection signal is input to each other input of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18552487U JPH0188524U (en) | 1987-12-04 | 1987-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18552487U JPH0188524U (en) | 1987-12-04 | 1987-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0188524U true JPH0188524U (en) | 1989-06-12 |
Family
ID=31476838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18552487U Pending JPH0188524U (en) | 1987-12-04 | 1987-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0188524U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260602A (en) * | 2004-03-11 | 2005-09-22 | Seiko Epson Corp | High hysteresis width input circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586620A (en) * | 1981-07-03 | 1983-01-14 | Toshiba Corp | Schmitt trigger circuit |
| JPS61237509A (en) * | 1985-04-12 | 1986-10-22 | Nec Corp | Schmitt trigger circuit |
-
1987
- 1987-12-04 JP JP18552487U patent/JPH0188524U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586620A (en) * | 1981-07-03 | 1983-01-14 | Toshiba Corp | Schmitt trigger circuit |
| JPS61237509A (en) * | 1985-04-12 | 1986-10-22 | Nec Corp | Schmitt trigger circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260602A (en) * | 2004-03-11 | 2005-09-22 | Seiko Epson Corp | High hysteresis width input circuit |
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