JPS62125937U - - Google Patents
Info
- Publication number
- JPS62125937U JPS62125937U JP1052086U JP1052086U JPS62125937U JP S62125937 U JPS62125937 U JP S62125937U JP 1052086 U JP1052086 U JP 1052086U JP 1052086 U JP1052086 U JP 1052086U JP S62125937 U JPS62125937 U JP S62125937U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- level
- microcomputer
- peripheral device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 2
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の実施例の半導体集積回路装置
を示す回路図、第２図は第１図の半導体集積回路
装置の入出力特性図、第３図ａは従来のＮＭＯＳ
による入力回路図、第３図ｂは第３図ａの入出力
特性図、第４図ａは従来のＣＭＯｓによる入力回
路図、第４図ｂは第４図ａの入出力特性図である
。
１……入力端子、２……制御信号端子、３，４
，７，１２，１３……Ｐチヤンネル・エンハンス
メント型トランジスタ、５……ＣＭＯＳレベル時
選択回路、６……インバータ、８，１５……Ｎチ
ヤンネル・デプレツシヨン型トランジスタ、９…
…ＴＴＬレベル時選択回路、１０，１４，１６，
１７……Ｎチヤンネル・エンハンスメント型トラ
ンジスタ、１１……入力回路の出力端子、１８…
…レベルシフタ回路、１９……レベルシフタ回路
の出力。
Fig. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of the semiconductor integrated circuit device of Fig. 1, and Fig. 3a is a conventional NMOS.
3b is an input/output characteristic diagram of FIG. 3a, FIG. 4a is an input circuit diagram of a conventional CMO, and FIG. 4b is an input/output characteristic diagram of FIG. 4a. 1...Input terminal, 2...Control signal terminal, 3, 4
, 7, 12, 13...P channel enhancement type transistor, 5...CMOS level selection circuit, 6...Inverter, 8, 15...N channel depletion type transistor, 9...
...TTL level selection circuit, 10, 14, 16,
17... N-channel enhancement type transistor, 11... Output terminal of input circuit, 18...
...Level shifter circuit, 19... Output of the level shifter circuit.
Claims (1)
介在して信号伝達を行い、ＭＯＳ型半導体集積回
路素子内に形成される入力回路を備えた半導体集
積回路装置において、前記マイクロコンピユータ
、前記周辺デバイスの論理スレツシヨールド・レ
ベルに応じて、ＴＴＬレベル、ＣＭＯＳレベルの
うちどちらかを選択して動作させる手段を前記入
力回路に設けていることを特徴とする半導体集積
回路装置。 A semiconductor integrated circuit device interposed between a microcomputer and a peripheral device for signal transmission and provided with an input circuit formed in a MOS type semiconductor integrated circuit element, wherein the logic threshold of the microcomputer and the peripheral device is A semiconductor integrated circuit device, characterized in that the input circuit is provided with means for selecting and operating either a TTL level or a CMOS level depending on the level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1052086U JPS62125937U (en) | 1986-01-27 | 1986-01-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1052086U JPS62125937U (en) | 1986-01-27 | 1986-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62125937U true JPS62125937U (en) | 1987-08-10 |
Family
ID=30796889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1052086U Pending JPS62125937U (en) | 1986-01-27 | 1986-01-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62125937U (en) |
-
1986
- 1986-01-27 JP JP1052086U patent/JPS62125937U/ja active Pending
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